JPH05243494A - Semiconductor device - Google Patents

Abstract

PURPOSE:To absorb carriers by a guard ring which carrier is generated by noise entering from an input terminal, by forming the guard ring of an impurity layer to a depth deeper than or equal to a well formed on the surface of a semiconductor substrate. CONSTITUTION:An input circuit consists of an input protecting circuit and a guard ring. The input protecting circuit consists of metal 8 turning to an electrode part and N<+>4 which serves as a resistor and a protective diode. The guard ring consists of the following which surround the input protecting circuits; an N well 1, an N<+> guard ring 2, and an N-type guard ring 3 which is formed to be deeper than the N well 1 and composed of an impurity layer of the same type as the well 1 and the N<+> guard ring 2. Since the N-type guard ring 3 of an impurity layer deeper than the N well 1 is formed and electrically connected with a positive power supply side, the greater part of carrier generated by noise entering from a power supply part is absorbed by the guard ring, and discharged through the positive power supply side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input and output circuit capable of improving the latch-up resistance of an IC.

[0002]

2. Description of the Related Art Conventionally, an impurity layer (hereinafter referred to as a guard layer) is formed on the surface of a semiconductor substrate so as to surround an input circuit and an output circuit in order to absorb a carrier moving in the semiconductor substrate generated by noise entering from input and output terminals. Ring) is formed. As shown in FIG. 3, this guard ring is formed at the same time when forming a protection circuit such as a protection diode in the case of an input circuit, and a transistor for an output buffer in the case of an output circuit when forming a well or a source / drain of a semiconductor device. The shallow diffusion layer 1 or 2 is used. FIG. 1 is a pattern diagram of the input circuit of the present invention, but the one without the N-type guard ring 3 is the conventional guard ring.

[0003]

However, in the conventional semiconductor device, since the impurity layer formed at the same time when the impurity layers for the well and the source / drain are formed is used as the guard ring layer, the guard ring layer is formed shallowly. Therefore, carriers that move on the surface when noise enters from the input and output terminals are absorbed by the guard ring, but carriers that move deep inside reach the inside without being absorbed by the guard ring. There is a problem that it triggers latch-up that causes malfunction of the circuit or destruction of the element.

Therefore, the object of the present invention is to solve the above-mentioned conventional problems by forming a deep guard ring capable of absorbing carriers moving deep in a well or a guard ring layer formed when forming a source / drain. The other is to provide.

[0005]

In order to solve the above-mentioned problems, the present invention forms another deep guard ring of a shallow impurity layer which is formed at the same time when forming a well and a source / drain. It has been designed to reduce the number of carriers that reach.

[0006]

In the guard ring formed as described above, carriers moving in a shallow or deep place generated by noise that has entered from the input and output terminals are deeply formed in the guard ring. Most of it is absorbed by the guard ring and does not reach the inside,
The trigger current that causes latch-up will not be generated.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a pattern diagram of an input circuit including a known input protection circuit and a guard ring of the present invention. This input circuit includes an input protection circuit formed of METAL 8 serving as an electrode part, a resistance and N ⁺ 4 which functions as a protection diode, and an N well 1, N ⁺ guard ring 2 and N surrounding the input protection circuit.
The guard ring is deeper than the well 1 and is formed of an N-type guard ring 3 made of the same type of impurity layer as the well 1 and the N ⁺ guard ring 2. The N well 1 is formed at the same time as forming the well of the semiconductor device, and the N ⁺ guard ring 2 is formed at the same time as forming the source / drain.

FIG. 2 shows a sectional view of the AA 'portion in FIG. In the cross section of the guard ring portion, there is the shallowest N ⁺ guard ring 2 and N well 1.
An N-type guard ring 3 having an impurity layer deeper than the well 1 is formed. Since this guard ring 3 is electrically connected to the V _cc side (positive power source side), most of the carriers generated by the noise that has entered from the electrode part are absorbed by the guard ring and then passed through this V _cc side. Is released. As a method of manufacturing the N-type guard ring 3, immediately after the N-type impurity (for example, Phos, As) is implanted into the N well 1 by using the ion implantation method, the same type of impurity is implanted with a higher acceleration energy than that. To do. After that, the N-type guard ring 3 that is deeper than the N well 1 can be provided by performing heat treatment in the impurity diffusion step of the well that is normally performed. In the above method, the depths of the N well 1 and the N type guard ring 3 are controlled by making a difference in the acceleration energy of the ion implantation, but the depths are made different by the impurities of the same type but different diffusion coefficients. It is also possible. In addition to the ion implantation for forming the N well 1, the ion implantation for forming the source / drain is followed by ion implantation with a very high acceleration energy (for example, 500 keV or more) to perform heat treatment at a high temperature. Even if not performed, a diffusion layer deeper than the N well 1 can be obtained. The depth of the N-type guard ring 3 can be controlled to an optimum value by changing the acceleration energy of ion implantation when the guard ring 3 is formed.

As described above, by providing the impurity layer deeper than the N well 1 as the guard ring, most of the carriers generated by the noise entering from the electrode portion can be absorbed.

[0010]

As described above, according to the present invention, by providing an impurity layer deeper than the impurity layer used in the conventional guard ring, carriers generated by noise entering from the input (output) terminal can be prevented. Even if the semiconductor substrate is moved to a shallow portion or a deep portion, it can be absorbed by the guard ring, and it is possible to prevent the arrival of carriers that trigger the latch-up inside the IC and prevent the latch-up. In addition, since the depth of only the impurity layer of the guard ring does not need to be changed and the depth of the well and the source / drain need not be changed, the guard ring with good carrier absorption efficiency does not affect the miniaturization of the IC. There is also an effect that can be obtained.

[Brief description of drawings]

FIG. 1 is a pattern diagram of an input circuit with a guard ring according to the present invention.

FIG. 2 is a cross-sectional view of the guard ring portion of the present invention taken along the line AA ′ in FIG.

FIG. 3 is a sectional view of a conventional guard ring portion.

[Explanation of symbols]

1 N well 2 N ⁺ guard ring 3 N type guard ring 4 N ⁺ 5 Poly Si 6 P ⁺ 7 contact 8 METAL 9 semiconductor substrate

Claims (1)

[Claims] 1. A circuit having an impurity layer, a so-called guard ring, formed on a surface of a semiconductor substrate so as to surround an input circuit or an output circuit of an IC used for transmitting a signal to an external circuit, wherein the guard of the impurity layer is provided. A semiconductor device characterized in that the ring is formed to a depth greater than that of a well formed on the surface of a semiconductor substrate during element formation.