JPH0729974A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a protective diode which can resist large surge such as load dump and to eliminate the need for change of a size thereof. CONSTITUTION:An N<->-silicon substrate 1 and a P<->-silicon substrate 2 wherein specified treatment is carried out are laminated, and a power element 10 and a control circuit 24 are formed on a surface of the N<->-silicon substrate 1. The silicon substrate 1 is divided into regions 10, 14, 19 which are subjected to dielectric isolation by the use of an oxide film 3 and a region 9 of direct junction. A PN junction 5 which becomes a Zener diode is formed in the silicon substrate 2 of the region 9 of direct junction. A surface electrode 6 of the direct junction region 9 of the substrate 1 and a rear electrode 7 of the substrate 2 become a cathode electrode and an anode electrode of a diode, respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device using an insulating separation substrate in which a high breakdown voltage device and a low breakdown voltage device are integrated.

[0002]

2. Description of the Related Art Conventionally, as a power IC used for driving a motor, a solenoid, etc., as shown in FIG. 2, a circuit having a protection diode for protecting the IC portion against various surges is known. This circuit uses a power M for the control circuit 32.
OS33 is connected, the source of power MOS33 and GN
The configuration is a high-side switch in which the load 34 is connected between D37. A parasitic diode 36 is formed between the source and drain of the power MOS 33, but the withstand voltage of this diode is usually as high as 60 V or higher, and this diode cannot protect a control circuit with a withstand voltage of 30 V at most. Therefore, the Zener diode 35 is connected between V _{DD and} GND. Conventionally, this diode is formed on the surface of a semiconductor chip, but if it is formed on the surface of the chip, there is a problem that the chip size increases and the cost increases.

Therefore, as a method for solving the above problems, there is a configuration disclosed in Japanese Patent Application No. 4-79076.
As shown in FIG. 15, the insulating separation layer 11 is formed on the P-type silicon substrate 21, and the N-type polycrystalline layer 13 is formed in the portion where the insulating separation layer 11 is not formed. A bipolar transistor 8 is formed so as to be insulated and separated from the P-type silicon substrate 21 by the insulating separation layer 11.
A protection diode is formed in the part where there is no 1. According to this structure, since the protection diode is formed in the vertical direction and the breakdown thereof can be set by the impurity concentration of the P-type silicon substrate 21, the protection diode can be formed without increasing its size.

[0004]

However, even in the case of a surge, it is said to be 50 to 50 which is called a load dump especially for automobile applications.
For a power surge of 100 V, it is necessary to pass a relatively large current, so a relatively large diode having a PN junction area of several mm ² or more is required. Therefore, the above-mentioned Japanese Patent Application No. 4-
In the configuration shown in No. 79076, the PN junction area is several mm ²
In order to secure the size as described above, in order to secure the size of the protection diode to some extent, a large occupied area on the substrate must be taken, which causes a problem that the size of the semiconductor device becomes large.

Therefore, in view of the above problems, it is an object of the present invention to provide a semiconductor device which has a protection diode capable of withstanding a large surge such as a load dump and does not need to change its size. .

[0006]

SUMMARY OF THE INVENTION A semiconductor device according to the present invention, which has been made to solve the above problems, has a semiconductor substrate having one conductivity type, a bottom portion and a sidewall formed by an insulating separation layer. And an insulating isolation region surrounded by a portion, and a semiconductor layer of a reverse conductivity type formed on the semiconductor substrate, the bottom of which is formed below the insulating isolation layer at the bottom of the insulating isolation region. I am trying.

[0007]

According to the present invention, the bottom of the semiconductor layer formed on the semiconductor substrate having one conductivity type and having the conductivity type opposite to that of the semiconductor substrate is formed on the bottom of the insulating isolation region formed on the semiconductor substrate. Since it is formed below the insulating separation layer, the PN junction area of the protection diode formed from the semiconductor substrate having the one conductivity type and the semiconductor layer having the opposite conductivity type has the PN junction area of the semiconductor layer of the semiconductor layer. It can be arbitrarily enlarged by simply expanding the bottom of the semiconductor layer without expanding the occupied area on the substrate.

[0008]

FIG. 1 shows a first embodiment of the present invention. The N ⁻ type silicon substrate 1 and the P ⁻ type silicon substrate 2 which have been subjected to a predetermined process are bonded to each other, and the power element 10 and the control circuit 24 are formed on the surface of the silicon substrate 1. The semiconductor substrate 1 is divided into regions 10, 14, 19 which are insulated and separated by the oxide film 3 and regions 9 of direct junction. High breakdown voltage power unit 10
The low breakdown voltage control circuit section 24 is insulated and isolated by the oxide film 3. Further, a PN junction 5 which is a Zener diode schematically drawn in the figure is formed on the semiconductor substrate 2, and a front surface electrode 6 of a direct junction region 9 of the substrate 1 and a back surface electrode 7 of the substrate 2 are respectively cathodes of the diode. It becomes an electrode and an anode electrode.

With the above structure, the PN junction 5
Can be formed under the region separated by the oxide film 3, so that a PN junction having a relatively large area can be formed. Further, even for a larger surge, the PN junction area can be arbitrarily increased only by increasing the N ⁺ layer region formed under the oxide film 3, so that it is not necessary to increase the region of the direct junction portion. Therefore, it is not necessary to increase the size of the semiconductor device.

The manufacturing process of the first embodiment will be described below with reference to FIGS.
This will be described using 1. First, as shown in FIG. 3, the N ⁻ type silicon substrate 1 is mirror-polished, and a convex portion 6a is formed by chemical etching or reactive ion etching (hereinafter referred to as RIE). Next, as shown in FIG. 4, ions are implanted into the convex portion 6a and a portion 11a which will be a DMOS region in the future by using a mask such as a resist to form an N ⁺ region.

Next, as shown in FIG. 5, the oxygen introducing groove 1a is formed.
Are formed by dicing, chemical etching or RIE. The oxygen introducing groove 1a is formed so as to communicate with the end of the silicon substrate 1. next,
As shown in FIG. 6, ions are partially implanted into the mirror-polished bonding surface side of the P ⁻ type silicon substrate 2 to form an N ⁺ layer. Further, by ion-implanting the entire surface on the opposite surface, P
⁺ Form a layer.

Next, as shown in FIG. 7, the silicon substrate 1
And N of the silicon substrate 2 respectively ⁺The layered surface
Laminate and bond. At this time, the convex portion 6a is
It comes into contact with the control board 2. After that, oxygen introduction groove
Oxygen is introduced from 1a to form the oxide film 3 on the groove wall. This
At this time, the groove is not completely filled with the oxide film and the cavity 4a
To remain.

Next, as shown in FIG. 9, the cavity 4a is exposed by grinding and polishing from the substrate 1 side. Next, as shown in FIG. 10, polycrystalline silicon 4 is deposited by the LPCVD method or the like to fill the cavity 4a. Thereafter, as shown in FIG. 11, excess polycrystalline silicon 4 is polished.

Then, a DMOS or other control section is formed in a region insulated and separated by the oxide film 3 to form an element as shown in FIG. In the first embodiment, the PN junction formed on the semiconductor substrate 2 can also be used as a photodiode. In this case, it is necessary to open a window in a part of the back surface electrode 7 so that light emitted from a light emitting diode or the like can pass through.

The element formed in the region of the semiconductor substrate 1 separated by the oxide film 3 is not limited to the MOS transistor, but may be a bipolar element or a thyristor. further,
In FIG. 1, the power element 10 is formed in a region separated by the oxide film 3 and the cathode of the diode is taken out independently, but in the second embodiment shown in FIG.
The same as the first embodiment except that the drain of S and the cathode of the diode are shared. When the drain and cathode of the power MOS are common as in the circuit configuration shown in FIG. 2, the same effect can be obtained with the structure of FIG.

The manufacturing process of the second embodiment differs from the manufacturing process of the first embodiment in that, as shown in FIG.
^- ion-implanted into the entire surface of the mirror-polished surface of the silicon substrate 1 of type to form a N ⁺ layer, then the protective diode region and DMO by selective etching as shown in FIG. 14
This is the point where the portion A which becomes the S region is formed. The subsequent steps follow FIGS. 5 to 11.

[0017]

As described above, according to the present invention, a PN junction area of a protection diode formed from a semiconductor substrate having one conductivity type and a semiconductor layer having the opposite conductivity type is provided on the semiconductor substrate of the semiconductor layer. It is possible to arbitrarily increase the size by simply expanding the bottom of the semiconductor layer without expanding the occupied area of the semiconductor layer. Therefore, even if a protection diode against a large surge is formed on the semiconductor substrate, it is not necessary to make the semiconductor region large. It is not necessary to increase the size of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a semiconductor device of a first embodiment.

FIG. 2 is a cross-sectional view showing a manufacturing process of the semiconductor device of the first embodiment.

FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device of the first embodiment.

FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor device of the first embodiment.

FIG. 5 is a cross-sectional view showing a manufacturing process of the semiconductor device of the first embodiment.

FIG. 6 is a cross-sectional view showing a manufacturing process of the semiconductor device of the first embodiment.

FIG. 7 is a cross-sectional view showing a manufacturing process of the semiconductor device of the first embodiment.

FIG. 8 is a cross-sectional view showing a manufacturing process of the semiconductor device of the first embodiment.

FIG. 9 is a cross-sectional view showing a manufacturing process of the semiconductor device of the first example.

FIG. 10 is a cross-sectional view showing a manufacturing process of the semiconductor device of the first example.

FIG. 11 is a cross-sectional view showing a manufacturing process of the semiconductor device of the first example.

FIG. 12 is a sectional view showing a semiconductor device according to a second embodiment.

FIG. 13 is a cross-sectional view showing a manufacturing process of a semiconductor device of a second example.

FIG. 14 is a cross-sectional view showing a manufacturing process of a semiconductor device of a second embodiment.

FIG. 15 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

1 N ⁻ type silicon substrate 2 P ⁻ type silicon substrate 3 oxide film 5 PN junction surface

Claims (1)

[Claims] 1. A semiconductor substrate having one conductivity type, an insulating isolation region formed on the semiconductor substrate and having a bottom portion and a side wall portion surrounded by an insulating isolation layer, and a semiconductor substrate having a bottom portion formed on the semiconductor substrate. And a semiconductor layer of a reverse conductivity type formed below the insulating separation layer at the bottom of the insulating separation region.