JPH05243289A - Hybrid integrted circuit device and its manufacture - Google Patents

Hybrid integrted circuit device and its manufacture

Info

Publication number
JPH05243289A
JPH05243289A JP4119792A JP4119792A JPH05243289A JP H05243289 A JPH05243289 A JP H05243289A JP 4119792 A JP4119792 A JP 4119792A JP 4119792 A JP4119792 A JP 4119792A JP H05243289 A JPH05243289 A JP H05243289A
Authority
JP
Japan
Prior art keywords
solder
lead
tin
semiconductor element
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4119792A
Other languages
Japanese (ja)
Inventor
Jun Sakano
純 坂野
Takeshi Nakamura
岳史 中村
Yuusuke Igarashi
優助 五十嵐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP4119792A priority Critical patent/JPH05243289A/en
Publication of JPH05243289A publication Critical patent/JPH05243289A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201Structure
    • H01L2224/32012Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32013Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

PURPOSE:To provide a hybrid integrated circuit capable of soldering of a very small size of semiconductor element and its manufacture. CONSTITUTION:This is one being plotted, seeking the ratio of the solder spread L and the height t after reflow in nitrogen atmosphere, as regards each kind of solder. It shows an extremely large L/t value in the range from 45:55 to 55:45 in the weight mixture ratio of tin to lead, as compared with the solder at mixture ratio beside the range. Accordingly, for the hybrid integrated circuit using the solder within the range from 45:55 to 55:45 in weight mixture ratio of tin to lead, being let reflow in nitrogen atmosphere, the solder flows enough even on a pad approximately 0.5mm in one side, and it hardens flatly. As a result, a very small size of semiconductor element is fixed horizontally.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は混成集積回路装置および
その製造方法に関し、詳細には、微小サイズの半導体素
子の固着技術に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device and a method of manufacturing the same, and more particularly, to a technique for fixing minute semiconductor elements.

【0002】[0002]

【従来の技術】図4を参照すると、従来の混成集積回路
装置は、絶縁金属基板(20)、この絶縁金属基板(20)上に
絶縁樹脂層(22)を介して所定形状に形成したダイボンド
パッド(24)(26)、ワイアボンディングパッド(28)等の回
路パターン、所定のダイボンドパッド(24)(26)に固着し
た半導体素子(34)(36)等から構成される。
2. Description of the Related Art Referring to FIG. 4, a conventional hybrid integrated circuit device includes an insulating metal substrate (20) and a die bond formed on the insulating metal substrate (20) with an insulating resin layer (22) in a predetermined shape. It is composed of circuit patterns such as pads (24) and (26), wire bonding pads (28), semiconductor elements (34) and (36) fixed to predetermined die bond pads (24) and (26), and the like.

【0003】絶縁金属基板(20)には放熱特性および加工
性を考慮して略2mm厚のアルミニウムが使用され、絶
縁性の向上のためにその表面が陽極酸化処理される。ダ
イボンドパッド(24)(26)、ワイアボンディングパッド(2
8)等の回路パターンは、ポリイミド樹脂等の接着性を有
する熱硬化性絶縁樹脂と略35μm厚の銅箔とのクラッ
ド材を温度150℃〜170℃、1平方センチメートル
当り50〜100Kgの圧力で絶縁金属基板(20)にホッ
トプレスした後、その銅箔をホトエッチングする等して
所定パターンに形成される。なお、現実の混成集積回路
装置では前記したパターンの他、バス等の導電路、チッ
プ抵抗あるいはチップコンデンサ等の異型部品を固着す
るパッド、混成集積回路装置の外部リードを固着する外
部リード用パッドが同時形成される。また、前記熱硬化
性絶縁樹脂はこのホットプレス工程で完全硬化して略3
5μm厚の絶縁樹脂層(22)となる。
Aluminum having a thickness of about 2 mm is used for the insulating metal substrate 20 in consideration of heat dissipation characteristics and workability, and the surface thereof is anodized to improve the insulating property. Die bond pads (24) (26), wire bonding pads (2
For the circuit pattern such as 8), a clad material made of a thermosetting insulating resin having adhesiveness such as polyimide resin and a copper foil having a thickness of about 35 μm is insulated at a temperature of 150 ° C. to 170 ° C. and a pressure of 50 to 100 Kg per square centimeter. After hot pressing on the metal substrate (20), the copper foil is photo-etched to form a predetermined pattern. In an actual hybrid integrated circuit device, in addition to the pattern described above, a conductive path such as a bus, a pad for fixing atypical parts such as a chip resistor or a chip capacitor, and an external lead pad for fixing an external lead of the hybrid integrated circuit device are provided. Simultaneously formed. In addition, the thermosetting insulating resin is completely cured in this hot pressing process to obtain approximately 3
The insulating resin layer 22 has a thickness of 5 μm.

【0004】半導体素子(34)(36)はチップ形状で使用さ
れ、小信号用のトランジスタあるいは集積回路素子等、
微小サイズの半導体素子(34)は銀ペースト(30)等のソル
ダペーストを使用して固着され、大電力トランジスタ等
の大サイズの半導体素子(36)は半田(32)を使用して固着
される。それら半導体素子(34)(36)は、所定のダイボン
ドパッド(24)(26)にクリーム状の銀ペースト(30)および
半田(32)を順次スクリーン印刷し、その粘性を利用し
て、先ず、大サイズの半導体素子(36)および図示しない
チップ抵抗あるいはチップコンデンサ等の異型部品が仮
固着され、リフローされて完全固着される。続いて、微
小サイズの半導体素子(34)が、同様に、銀ペースト(30)
上に仮固着され、リフローされて完全固着される。
The semiconductor elements (34) and (36) are used in a chip form, and are used for small signal transistors or integrated circuit elements, etc.
Small size semiconductor element (34) is fixed by using solder paste such as silver paste (30), and large size semiconductor element (36) such as high power transistor is fixed by using solder (32) .. The semiconductor elements (34) (36) are screen-printed with a creamy silver paste (30) and a solder (32) on a predetermined die bond pad (24) (26) in sequence, and by utilizing the viscosity, first, The large-sized semiconductor element (36) and odd-shaped components such as a chip resistor or a chip capacitor (not shown) are temporarily fixed and reflowed to be completely fixed. Then, the semiconductor element (34) of a minute size is similarly silver paste (30).
Temporarily fixed on top, reflowed and completely fixed.

【0005】この後、半導体素子(34)(36)の電極と所定
のワイアボンディングパッド(28)がワイアボンディング
され、外部接続のための外部リード(図示しない)が固
着され、さらに、樹脂製のケースで搭載素子が封止され
る。
Thereafter, the electrodes of the semiconductor elements (34) and (36) are wire-bonded to predetermined wire bonding pads (28), external leads (not shown) for external connection are fixed, and further, resin-made pads are used. The mounted element is sealed by the case.

【0006】[0006]

【発明が解決しようとする課題】上述したように、半田
リフローによりチップ状の半導体素子を固着する技術は
既に知られている。しかし、微小サイズの例えば小信号
系の半導体素子をリフロー工程を利用してダイボンドパ
ッド上に半田固着する場合には、以下のような問題が生
じる。
As described above, a technique for fixing a chip-shaped semiconductor element by solder reflow is already known. However, when soldering a small-sized semiconductor element of, for example, a small signal system onto the die bond pad using the reflow process, the following problems occur.

【0007】例えば、小信号用のトランジスタで微小サ
イズのものは一辺が0.3mm〜1.0mm程度であ
り、そのためのダイボンドパッド(24)のサイズは一辺が
0.5mm〜1.5mmである。半導体素子をダイボン
ドパッド(24)上に最適に固着する半田量は、例えばその
半導体素子のチップサイズの一辺が0.3mmであると
きは約0.018〜0.025mm3 位必要である。こ
れに対して、スクリーン印刷法により印刷されるロウ材
量はメタルマスク厚で決定され、0.1mm以下の厚さ
にロウ材を印刷することが困難である。これは印刷に限
らずディスペンサー方式においても同様である。
For example, a small signal transistor having a small size has a side of about 0.3 mm to 1.0 mm, and the size of the die bond pad (24) for this purpose is a side of 0.5 mm to 1.5 mm. .. The amount of solder that optimally fixes the semiconductor element on the die bond pad (24) needs to be about 0.018 to 0.025 mm 3 when one side of the chip size of the semiconductor element is 0.3 mm. On the other hand, the amount of the brazing material printed by the screen printing method is determined by the metal mask thickness, and it is difficult to print the brazing material to a thickness of 0.1 mm or less. This applies not only to printing but also to a dispenser method.

【0008】従って、印刷等の手段により微細サイズの
ダイボンドパッド(24)上に半田を塗布した場合には、半
導体素子を最適固着するのに必要以上の過剰半田が印刷
等される。この問題は現状の塗布技術では解決できない
問題である。このように、微小サイズの半導体素子を搭
載した従来の混成集積回路装置では、図4に示すよう
に、微小ダイボンドパッド(24)上ではロウ材が過剰とな
り、ダイボンドパッド(24)上の半田はリフロー時に半田
の表面張力により半球形を呈し、軽量且つ極めて微小な
半導体素子(34)は溶融半田の球面に沿って、傾いて固着
される。この場合、ワイヤーボンディングが行えず完全
不良となる問題があった。
Therefore, when solder is applied to the die bond pad (24) having a fine size by means of printing or the like, excessive solder is printed or printed more than necessary to optimally fix the semiconductor element. This problem is a problem that cannot be solved by the current coating technology. As described above, in the conventional hybrid integrated circuit device in which the minute-sized semiconductor element is mounted, as shown in FIG. 4, the brazing material becomes excessive on the minute die bond pad (24), and the solder on the die bond pad (24) is At the time of reflow, the semiconductor element (34), which has a hemispherical shape due to the surface tension of the solder and is lightweight and extremely minute, is fixed while being inclined along the spherical surface of the molten solder. In this case, there is a problem that wire bonding cannot be performed and a complete failure occurs.

【0009】この発明は上述した課題に鑑みてなされた
ものであり、この発明の目的は、極めて微小サイズのチ
ップ状の半導体素子をダイボンドパッド上に半田固着で
きる混成集積回路装置を提供することである。
The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a hybrid integrated circuit device capable of solder-fixing a chip-shaped semiconductor element having an extremely small size onto a die bond pad. is there.

【0010】[0010]

【課題を解決するための手段】上述した課題を解決し、
目的を達成するために、この発明に係わる混成集積回路
装置は、絶縁性基板と、この絶縁性基板上に所定形状に
形成された回路パターンと、この回路パターン上に半田
固着されたチップ状の半導体素子とを具備する混成集積
回路装置であって、前記半導体素子を固着する半田の錫
/鉛の重量混合比を錫/鉛=45/55〜錫/鉛=55
/45としたことを特徴としている。
[Means for Solving the Problems]
In order to achieve the object, a hybrid integrated circuit device according to the present invention is an insulative substrate, a circuit pattern formed in a predetermined shape on the insulative substrate, and a chip-shaped soldered on the circuit pattern. A hybrid integrated circuit device comprising a semiconductor element, wherein a tin / lead weight mixture ratio of solder for fixing the semiconductor element is tin / lead = 45/55 to tin / lead = 55.
The feature is that it is / 45.

【0011】また、この発明に係わる混成集積回路装置
の製造方法は、絶縁性基板上に所定形状の回路パターン
を形成し、その回路パターンの固着パッド上に錫/鉛の
重量混合比を錫/鉛=45/55〜錫/鉛=55/45
にしたクリーム半田を塗布し、固着パッド上にチップ状
の半導体素子を搭載した後、窒素雰囲気中でリフロー工
程を行い固着パッド上に半導体素子を固着することを特
徴としている。
Also, in the method for manufacturing a hybrid integrated circuit device according to the present invention, a circuit pattern having a predetermined shape is formed on an insulating substrate, and a tin / lead weight mixing ratio of tin / lead is set on the fixing pad of the circuit pattern. Lead = 45 / 55-tin / Lead = 55/45
It is characterized in that after applying the above-mentioned cream solder and mounting the chip-shaped semiconductor element on the fixing pad, a reflow process is performed in a nitrogen atmosphere to fix the semiconductor element on the fixing pad.

【0012】[0012]

【作用】以上のように構成される混成集積回路装置にお
いては、微小サイズの半導体素子を錫/鉛の重量混合比
Sn/Pb=45/55からSn/Pb=55/45の
半田を使用して固着することにより、半田溶融時にかか
る半田は固着パッド上に均一に流出され微小サイズの半
導体素子を略平坦に固着することができる。
In the hybrid integrated circuit device configured as described above, the solder having the tin / lead weight mixture ratio Sn / Pb = 45/55 to Sn / Pb = 55/45 is used for the small-sized semiconductor element. As a result of this fixing, the solder that is applied when the solder melts flows out evenly onto the fixing pad, and it is possible to fix the semiconductor element of minute size substantially flat.

【0013】[0013]

【実施例】図1および図2を参照して本発明の一実施例
を説明する。なお、本発明は集積回路基板に搭載素子を
固着するための半田の組成およびリフロー法に特徴を有
するものであり、先に、発明が解決すべき課題の項で説
明したような従来不可能とされていた混成集積回路構造
を実現するものである。そこで、実施例の構造の説明に
は先の図4を使用する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to FIGS. The present invention is characterized by the composition of the solder and the reflow method for fixing the mounted element to the integrated circuit board, and it is impossible to use the conventional method as described in the section of the problem to be solved by the invention. It realizes the conventional hybrid integrated circuit structure. Therefore, FIG. 4 described above is used to describe the structure of the embodiment.

【0014】図1は数種の半田のリフロー後の状態をプ
ロットした濡れ特性図であり、図2はリフロー後の半田
の状態を決定する手法を説明する図である。実験は0.
1mm厚のメタルマスクを使用して充分広い銅パターン
(10)上に半田クリームをスクリーン印刷し、これを窒素
雰囲気においてそれぞれの融点温度(液相線温度+20
〜30℃)でリフローすることによって行い、実験精度
を向上させるため、図2に示すように、リフロー後の半
田(10)の広がりLと高さtとの比L/tを特性値とし
た。
FIG. 1 is a wetting characteristic diagram in which the states of several kinds of solder after reflow are plotted, and FIG. 2 is a diagram for explaining a method of determining the state of solder after reflow. The experiment was 0.
Wide enough copper pattern using 1mm thick metal mask
(10) Solder cream is screen-printed on the surface, and the melting point temperature (liquidus temperature + 20
In order to improve the experimental accuracy, the ratio L / t of the spread L of solder (10) and the height t after reflow was used as a characteristic value in order to improve the experimental accuracy. ..

【0015】半田クリームには、従来から集積回路素子
あるいは部品の固着に広く使用されている錫(Sn)と
鉛(Pb)の混合比(重量比)が10/90および63
/37の2種の半田クリーム、混合比(重量比)が45
/55、50/50、55/45、60/40の4種の
計6種の半田クリームを使用し、例えば混合比が63/
37の半田クリームは183℃、また同50/50の半
田クリームは215℃というような予め求めたそれぞれ
の融点温度(液相線温度+20〜30℃)で窒素雰囲気
中においてリフローした。
In the solder cream, the mixture ratio (weight ratio) of tin (Sn) and lead (Pb), which has been widely used for fixing integrated circuit elements or parts, is 10/90 and 63.
/ 37 types of two solder creams, mixing ratio (weight ratio) is 45
/ 55, 50/50, 55/45, 60/40, total 6 types of solder cream are used, for example, the mixing ratio is 63 /
The solder cream of 37 was 183 ° C., and the solder cream of 50/50 was reflowed in a nitrogen atmosphere at respective melting points (liquidus temperature + 20 to 30 ° C.) determined in advance such as 215 ° C.

【0016】そして、この結果、図1に示すように、錫
(Sn)と鉛(Pb)の混合比(重量比)が50/50
の半田クリームによれば混合比(重量比)が10/90
および63/37の2種の従来の半田クリームの数倍の
L/t値=500が得られることが判明した。また、混
合比が45/55、55/45の半田クリームのL/t
値が比較的大きいに対して、同60/40の半田クリー
ムのそれが従来の半田クリームと同等であることからし
て、錫(Sn)と鉛(Pb)の混合比の変化に対して臨
界的な傾向があることも判明した。なお、空気中におけ
るリフローでも同様の傾向が見られたが、50/50組
成でもL/t値は150程度である。
As a result, as shown in FIG. 1, the mixing ratio (weight ratio) of tin (Sn) and lead (Pb) is 50/50.
According to the solder cream, the mixing ratio (weight ratio) is 10/90.
It was found that an L / t value of 500, which is several times that of the two conventional solder creams of 63 and 37, was obtained. Also, the L / t of solder cream with a mixing ratio of 45/55, 55/45
Although the value of the solder cream of 60/40 is the same as that of the conventional solder cream, the value is relatively large, so it is critical for the change of the mixing ratio of tin (Sn) and lead (Pb). It turned out that there is a tendency. A similar tendency was observed in reflow in air, but the L / t value was about 150 even with a 50/50 composition.

【0017】ここで、再び図3を参照して本発明の混成
集積回路装置およびその製造方法を説明する。本発明の
混成集積回路装置は、図4に示すように、絶縁金属基板
(20)、絶縁樹脂層(22)を介して所定形状にダイボンドパ
ッド(24)(26)、ワイアボンディングパッド(28)等を形成
した回路パターン、ダイボンドパッド(24)(26)に半田固
着した半導体素子(34)(36)等からなる構造を備える。そ
して、従来銀ペースト等のロウ材を使用して固着しなけ
ればならなかった微小サイズの半導体素子(34)を含めた
全ての半導体素子(34)(36)を錫(Sn)と鉛(Pb)の
重量混合比が略50/50の半田を使用し、単一のリフ
ロー工程により固着した点を第1の特徴とし、従来のリ
フロー温度より高い温度で、窒素雰囲気中でリフローす
る点を第2の特徴とする。
Here, referring again to FIG. 3, the hybrid integrated circuit device of the present invention and the manufacturing method thereof will be described. The hybrid integrated circuit device of the present invention, as shown in FIG.
(20), a circuit pattern formed with a die bonding pad (24) (26), a wire bonding pad (28), etc. in a predetermined shape via an insulating resin layer (22), and soldered to the die bond pad (24) (26) It has a structure including semiconductor elements (34), (36) and the like. Then, all the semiconductor elements (34) and (36) including the minute-sized semiconductor elements (34), which had to be fixed by using a brazing material such as silver paste, are tin (Sn) and lead (Pb). The first feature is that solder having a weight mixing ratio of 50) is used in a single reflow process and the reflow is performed in a nitrogen atmosphere at a temperature higher than the conventional reflow temperature. There are two characteristics.

【0018】絶縁金属基板(20)には耐熱性、放熱特性お
よび加工性を考慮して略2mm厚のアルミニウムが使用
され、絶縁性の向上のためにその表面が陽極酸化処理さ
れる。ダイボンドパッド(24)(26)、ワイアボンディング
パッド(28)等の回路パターンは、ポリイミド樹脂等の接
着性を有する熱硬化性絶縁樹脂と略35μm厚の銅箔と
のクラッド材を温度150℃〜170℃、1平方センチ
メートル当り50〜100Kgの圧力で絶縁金属基板(2
0)にホットプレスした後、その銅箔をホトエッチングす
る等して所定パターンに形成される。なお、現実の混成
集積回路装置では前記したパターンの他、バス等の導電
路、チップ抵抗あるいはチップコンデンサ等の異型部品
を固着するパッド、混成集積回路装置の外部リードを固
着する外部リード用パッドが同時形成される。また、前
記熱硬化性絶縁樹脂はこのホットプレス工程で完全硬化
して略35μm厚の絶縁樹脂層(22)となる。
Aluminum having a thickness of about 2 mm is used for the insulating metal substrate (20) in consideration of heat resistance, heat radiation characteristics and workability, and its surface is anodized to improve the insulating property. The circuit patterns of the die bond pads (24) (26), the wire bonding pads (28), etc. are made of a thermosetting insulating resin having adhesiveness such as polyimide resin and a clad material of approximately 35 μm thick copper foil at a temperature of 150 ° C. At 170 ° C, pressure of 50 to 100 kg per square centimeter, insulating metal substrate (2
After hot pressing to 0), the copper foil is photo-etched to form a predetermined pattern. In an actual hybrid integrated circuit device, in addition to the pattern described above, a conductive path such as a bus, a pad for fixing atypical parts such as a chip resistor or a chip capacitor, and an external lead pad for fixing an external lead of the hybrid integrated circuit device are provided. Simultaneously formed. Further, the thermosetting insulating resin is completely cured in this hot pressing process to form an insulating resin layer (22) having a thickness of about 35 μm.

【0019】次に、重量混合比が略45/55から55
/45の錫(Sn)と鉛(Pb)および少量のフラック
スを混合した半田クリームを0.1mm厚のメタルマス
クを使用して所定のダイボンドパッド(24)(26)上にスク
リーン印刷し、半田クリームの粘性を利用して全ての半
導体素子(34)(36)が連続的に仮固着される。その後、従
来例より高温の215℃程度の温度でリフローして半導
体素子(34)(36)が完全固着される。本発明の混成集積回
路装置では、比較的高温のリフローが必要であるもの
の、集積回路基板として金属基板を使用するため、基板
の耐熱性の制限を受けない
Next, the weight mixing ratio is about 45/55 to 55.
/ 45 tin (Sn), lead (Pb) and a small amount of flux mixed solder cream is screen-printed on a predetermined die bond pad (24) (26) using a 0.1 mm thick metal mask, and solder All the semiconductor elements (34) and (36) are temporarily temporarily fixed by utilizing the viscosity of the cream. Then, the semiconductor elements 34 and 36 are completely fixed by reflowing at a temperature of about 215 ° C., which is higher than that of the conventional example. In the hybrid integrated circuit device of the present invention, although relatively high temperature reflow is required, since the metal substrate is used as the integrated circuit substrate, the heat resistance of the substrate is not limited.

【0020】[0020]

【発明の効果】以上述べたように本発明の混成集積回路
装置は、従来銀ペースト等、比較的高価なロウ材を使用
しなければ水平な固着が得られなかった微小サイズの集
積回路素子を安価な半田を使用して固着することができ
る。また、他の大サイズの集積回路素子および部品と同
様に半田固着するため、ロウ材のスクリーン印刷工程お
よびリフロー工程が簡素化される。
As described above, according to the hybrid integrated circuit device of the present invention, a micro-sized integrated circuit element which could not be horizontally fixed unless a relatively expensive brazing material such as silver paste was used. It can be fixed using inexpensive solder. Moreover, since soldering is performed similarly to other large-sized integrated circuit elements and parts, the screen printing process and the reflow process of the brazing material are simplified.

【0021】また、単一リフローであるため、全ての集
積回路素子、部品をロウ材に連続的に仮固着できる利点
も有する。さらには、集積回路基板として金属基板を使
用するため、リフロー温度の制限を受けない利点を有す
る。
Further, since it is a single reflow, there is an advantage that all the integrated circuit elements and parts can be continuously temporarily fixed to the brazing material. Furthermore, since a metal substrate is used as the integrated circuit substrate, there is an advantage that the reflow temperature is not limited.

【図面の簡単な説明】[Brief description of drawings]

【図1】半田の濡れ特性図。FIG. 1 is a solder wetting characteristic diagram.

【図2】濡れ特性の決定手法を説明する半田の断面図。FIG. 2 is a sectional view of solder for explaining a method of determining the wetting characteristics.

【図3】複数のロウ材固着を採用する混成集積回路装置
の要部断面図。
FIG. 3 is a cross-sectional view of a main part of a hybrid integrated circuit device that employs a plurality of brazing materials fixed together.

【図4】半田固着のみを採用する混成集積回路装置の要
部断面図。
FIG. 4 is a cross-sectional view of essential parts of a hybrid integrated circuit device that employs only soldering.

【符号の説明】[Explanation of symbols]

20 絶縁金属基板 22 絶縁樹脂層 24 ダイボンドパッド 26 ダイボンドパッド 28 ワイアボンディングパッド 32 半田 34 小信号用半導体素子 36 大電力用半導体素子 20 Insulating Metal Substrate 22 Insulating Resin Layer 24 Die Bond Pad 26 Die Bond Pad 28 Wire Bonding Pad 32 Solder 34 Small Signal Semiconductor Element 36 High Power Semiconductor Element

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】絶縁性基板と、この絶縁性基板上に所定形
状に形成された回路パターンと、この回路パターン上に
半田固着されたチップ状の半導体素子とを具備する混成
集積回路装置であって、 前記半導体素子を固着する半田の錫/鉛の重量混合比を
錫/鉛=45/55〜錫/鉛=55/45としたことを
特徴とする混成集積回路装置。
1. A hybrid integrated circuit device comprising an insulative substrate, a circuit pattern formed in a predetermined shape on the insulative substrate, and a chip-shaped semiconductor element soldered and fixed onto the circuit pattern. And a tin / lead weight mixture ratio of solder for fixing the semiconductor element is tin / lead = 45/55 to tin / lead = 55/45.
【請求項2】絶縁性基板上に所定形状の回路パターンを
形成し、その回路パターンの固着パッド上に錫/鉛の重
量混合比を錫/鉛=45/55〜錫/鉛=55/45に
したクリーム半田を塗布し、固着パッド上にチップ状の
半導体素子を搭載した後、窒素雰囲気中でリフロー工程
を行い固着パッド上に半導体素子を固着することを特徴
とする混成集積回路装置の製造方法。
2. A circuit pattern having a predetermined shape is formed on an insulating substrate, and the weight mixing ratio of tin / lead is tin / lead = 45/55 to tin / lead = 55/45 on the fixing pad of the circuit pattern. Manufacturing of a hybrid integrated circuit device characterized by applying the above-mentioned cream solder, mounting a chip-shaped semiconductor element on the fixing pad, and then performing a reflow process in a nitrogen atmosphere to fix the semiconductor element on the fixing pad. Method.
JP4119792A 1992-02-27 1992-02-27 Hybrid integrted circuit device and its manufacture Pending JPH05243289A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4119792A JPH05243289A (en) 1992-02-27 1992-02-27 Hybrid integrted circuit device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4119792A JPH05243289A (en) 1992-02-27 1992-02-27 Hybrid integrted circuit device and its manufacture

Publications (1)

Publication Number Publication Date
JPH05243289A true JPH05243289A (en) 1993-09-21

Family

ID=12601699

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4119792A Pending JPH05243289A (en) 1992-02-27 1992-02-27 Hybrid integrted circuit device and its manufacture

Country Status (1)

Country Link
JP (1) JPH05243289A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000299553A (en) * 1999-04-13 2000-10-24 Ricoh Microelectronics Co Ltd Manufacture of electronic circuit board
US7601625B2 (en) 2004-04-20 2009-10-13 Denso Corporation Method for manufacturing semiconductor device having solder layer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000299553A (en) * 1999-04-13 2000-10-24 Ricoh Microelectronics Co Ltd Manufacture of electronic circuit board
US7601625B2 (en) 2004-04-20 2009-10-13 Denso Corporation Method for manufacturing semiconductor device having solder layer

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