JPH05241953A - Cache memory - Google Patents

Abstract

PURPOSE:To provide cache memory in which the latency time of a memory hierarchy at the pre-stage can be reduced when the memory hierarchy at the pre-stage makes a plural number of times of access a memory hierarchy at the next stage. CONSTITUTION:While data (A0) in accordance with a first request address (a0) generating mis-cache is received from memory 99 after the decision result of the first request address (a0) from a CPU 4 is judged as mis-cache, a new second request address (b1) is received from the CPU 4 by a decision means and a data transfer request output means, and it is decided whether the request address (b1) is judged as cache-hit or mis-cache, thereby, decision as cache-hit for the second request address (b1) can be eliminated apparently.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory which accelerates memory access in a microprocessor.

[0002]

2. Description of the Related Art In recent years, cache memories have been used for speeding up memory access of microprocessors. Up to now, the memory access time has been reduced by increasing the cache hit rate, but since there is a limit to increasing the hit rate, attention has recently been focused on reducing the penalty at the time of a cache miss.

A conventional cache memory will be described below with reference to the drawings. FIG. 3 is a block diagram showing the configuration of a conventional cache memory. In FIG.
Reference numeral 1 is a tag memory, which stores previously accessed addresses. Reference numeral 2 is a data memory, which stores data of previously accessed addresses. 30 is a control unit, 4 is a CPU, 8 is a comparison circuit, 80, 96, 97, 3
00 is a latch, 21 and 93 are selectors, 98 is a tri-state buffer, and 90 is a memory control circuit. The tag memory 1, the data memory 2 and the control unit 30 are main constituent elements of the cache memory.

The operation of the conventional cache memory thus configured will be described. C for cache memory
The PU 4 outputs the request address to the bus 51 and outputs the request signal 60 to the control unit 30. In the tag memory 1, the tag address is read onto the bus 53 from the entry designated by the request address on the bus 50.

The comparison circuit 8 compares the tag portion of the request address of the bus 50 with the tag address of the bus 53. At this time, if there is no match, that is, if there is a cache miss, the request address of the bus 50 is output to the memory control circuit 90, and at the same time, the control unit 30 outputs a request signal 62 to the memory control circuit 90. In the memory control circuit 90 to which the request signal 62 is input, the bus 5
Bus 99 from memory 99 with a request address of 0
The data is read to 0, and the acknowledge signal 63 is output to the control unit 30.

When the control unit 30 receives the acknowledge signal 63, it outputs the acknowledge signal 61 to the CPU 4. The cache memory also receives data from the memory control circuit 90 via the bus 70, and stores this data in C
The data is written to the data memory 2 at the same time as it is transferred to the PU 4.
Then, the memory control circuit 90 reads the remaining data of the cache line from the memory 99 to the bus 70 and transfers it to the cache memory. The cache memory is bus 7
The data of 0 is received and written in the data memory 2.

After that, the above operation is repeated.

[0008]

However, in the conventional cache memory thus configured, the CPU 4
Even if the CPU 4 prepares a new request address after issuing the request address and before receiving the data corresponding to the request address, the cache memory cannot receive the new request address. Therefore, until the CPU 4 receives the data corresponding to the first request address,
There was a problem of waiting for the output of a new request address.

When one request address causes a cache miss, an operation for transferring not only the data requested by the CPU 4 but also the data that need not be transferred to the CPU 4 to the data memory 2 in the cache memory occurs. .. Therefore, there is a problem that the CPU 4 has to wait for the output of a new request address for this unnecessary data transfer operation.

In view of the above problems, it is an object of the present invention to provide a cache memory which can reduce the access waiting time of the memory hierarchy in the preceding stage which outputs a data transfer request.

[0011]

According to a first aspect of the present invention, there is provided a cache memory, which comprises a determining means for determining a cache hit or a cache miss for a data transfer request output from a preceding memory layer, and a data transfer request. A data transfer request output unit that holds the data and outputs the data transfer request having the cache miss to the memory hierarchy of the next stage when the determination result is the cache miss, and the data transfer having the cache miss from the memory hierarchy of the next stage. It is provided with a data transfer means for receiving data corresponding to the request, transferring this data to the preceding memory hierarchy and storing it, and from the time when the determination result of the data transfer request by the determination means is a cache miss, Until the data corresponding to the data transfer request that resulted in this cache miss is received from the next memory layer It is obtained so as to perform the determining means and the data transfer request output means with respect to receiving a new data transfer request from the preceding stage of the memory hierarchy the new data transfer request.

According to another aspect of the present invention, when the data transfer means transfers the data from the memory hierarchy of the next stage to the memory hierarchy of the previous stage, it is not necessary to transfer to the memory hierarchy of the previous stage, but it is necessary to store the cache memory. The data corresponding to the new data transfer request output from the previous memory hierarchy is preferentially transferred over the data of the same cache line as the data corresponding to the data transfer request.

[0013]

According to the structure of the first aspect, from the time when the determination result of the first data transfer request by the determination means is a cache miss, the first data transfer request that is the cache miss is handled. Until the received data is received from the memory hierarchy of the next stage, the determining means and the data transfer request output means receive a new second data transfer request from the memory hierarchy of the previous stage, and the second data transfer request It is possible to apparently eliminate the above-described determination for the second data transfer request by determining whether the cache hit or the cache miss. Therefore,
It is possible to reduce the waiting time of the preceding memory hierarchy.

According to the structure of claim 2, in the structure of claim 1, when the data transfer means transfers data from the memory hierarchy of the next stage to the memory hierarchy of the preceding stage,
It is not necessary to transfer the data to the previous memory hierarchy, but rather than the data of the same cache line as the data corresponding to the first data transfer request that needs to be stored, a new second data output from the previous memory hierarchy is used. By preferentially transferring the data corresponding to the data transfer request, the data requested by the preceding memory hierarchy can be preferentially transferred from the next memory hierarchy to the preceding memory hierarchy. Therefore, the waiting time of the preceding memory hierarchy can be reduced.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A cache memory according to an embodiment of the present invention will be described below with reference to the drawings. 1 is a block diagram showing the configuration of a cache memory according to an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation of the cache memory. In FIG. 1, reference numeral 100 is a tag memory 1, data memory 2, a control unit 3, a cache memory mainly composed of a comparison circuit 8 and a holding unit 200, 4 is a CPU serving as a previous memory hierarchy, and 99 is a next memory hierarchy. Is the memory. Further, the judging means is mainly constituted by the tag memory 1, the control unit 3 and the comparison circuit 8.
The data transfer request output means is mainly composed of the control unit 3 and the holding unit 200. The data transfer means mainly comprises the control unit 3, the data memory 2 and the bus 70.

Hereinafter, each part will be described in detail with reference to FIG. 90 is a memory control circuit, 5, 6, 7, 80,
81, 96 and 97 are clock-synchronized latches, 2
0, 21, 22, and 93 are selectors, 8 is a comparison circuit,
Reference numeral 98 is a tri-state buffer. Bus 51 is C
The request address output of PU4 and the input of latch 7 are connected.

The bus 50 is provided with the output of the latch 7, the inputs of the latches 5 and 6, the data input of the comparison circuit 8, and the selector 20.
And the control input of the selector 21 are connected. The bus 52 connects between the output of the selector 20 and the index input of the tag memory 1 and the index input of the data memory 2.

The bus 53 connects between the output of the tag memory 1 and the data input of the comparison circuit 8. Bus 55
The output of the latch 5 and the data input of the selector 22 are connected. Further, the bus 56 connects the output of the latch 6 and the data input of the selector 22.

The bus 54 connects the output of the selector 22 with the input of the latch 81 and the request address input of the memory control circuit 90. The bus 49 connects the output of the latch 81, the data input of the selector 20, the data input of the tag memory 1, the data input of the selector 93, and the input of the inverter 89.

The signal line 87 connects the output of the inverter 89 and the input of the selector 93. Bus 92
The output of the selector 93 and the entry selection signal input of the data memory 2 are connected. The bus 70 includes an output of the tri-state buffer 98, an input of the latch 80, the CPU 4
And the data input / output of the memory control circuit 90.

The bus 71 connects between the output of the latch 80 and the data input of the data memory 2. Bus 58
Connects the data output of the data memory 2 and the data input of the selector 21. Further, the bus 59 connects the data output of the data memory 2 and the data input of the selector 21.

The bus 57 connects between the output of the selector 21 and the input of the latch 96, and the bus 48 connects between the output of the latch 96 and the data input of the tri-state buffer 98. The hit signal 10 is input from the comparison circuit 8 to the control unit 3 and the latch 97. The bus 95 connects between the output of the latch 97 and the control input of the tri-state buffer 98.

The read / write enable signal 13 is input from the control section 3 to the control terminals of the selector 20, the tag memory 1 and the data memory 2. The control signal 94 is input from the control unit 3 to the control terminal of the selector 93. The latch enable signal 11 is input from the control unit 3 to the enable input terminal of the latch 5, and the latch enable signal 1
2 is input from the control unit 3 to the enable input terminal of the latch 6.

The control signal 19 is sent from the control unit 3 to the selector 2
2 is input to the control terminal of the selector 93, and the control signal 94 is input from the control unit 3 to the control terminal of the selector 93. The request signal 60 is input from the CPU 4 to the control unit 3, the acknowledge signal 61 is input from the control unit 3 to the CPU 4, and the request signal 62 is input from the control unit 3 to the memory control circuit 90. Also, acknowledge signal 6
3 is input to the control unit 3 from the memory control circuit 90.
Further, the data request signal 64 is input from the control unit 3 to the memory control circuit 90, and the data request signal 65 is input.
Is input to the memory control circuit 90 from the control unit 3.

Here, the data which can be transferred by one bus transfer on the bus 70 are "A0", "A1", "B0" and "B1". In this case, the transfer of one cache line is completed by the bus transfer of the data “A0” and the data “A1”. Similarly, data "B0" and data "B1"
The bus transfer completes the transfer of one cache line.

Further, each data "A0", "A1", "B"
Addresses corresponding to "0" and "B1" are referred to as addresses "a0", "a1", "b0" and "b1", respectively. In the embodiment, the data “A0” and the data “B1” are data requested by the CPU 4. The memory control circuit 90 reads the data corresponding to the request address from the memory 99. Two data transfers are required to complete the transfer of the cache line. The memory control circuit 90 can receive two request addresses, and when receiving the two request addresses, the data request signal 6 output from the control unit 3
4 and data request signal 65 to transfer data. That is, when the data request signal 64 is at the high level, the data corresponding to the first request address is transferred, and when the data request signal 65 is at the high level, the data corresponding to the second request address is transferred. ..

The address for accessing the cache memory is divided into three parts. These three parts are the tag part, the select part, and the offset part, respectively. Further, the tag memory 1 has a plurality of entries, and the tag portion of the address of the cache line is stored in each entry. The address stored in the tag memory 1 is the tag address.

Further, the data memory 2 has the same number of entries as the tag memory 1, and each entry stores the data of the cache line. Each entry is composed of two parts, which are referred to as entry 0a and entry 1a, respectively. For example, assuming that the address of the cache line is the address "a0" or the address "a1", the data "A0" is stored in the entry 0a and the data "A1" is stored in the entry 1a. The control unit 3 has two state machines, each of which is a state machine M.
0 and state machine M1. State machine M
0 and state machine M1 are S0, S1 and S, respectively.
It has the states of 2 and S3.

The cache memory configured as described above operates as follows. The request address of the address "a0" is received from the CPU 4, the cache hit is judged, and in the case of a cache miss, the memory control circuit 9
0 to the data "A" of the cache line at address "a0"
0 ”and“ A1 ”are requested. During this time, the request address of the address "b1" is also received from the CPU 4 and a cache hit is determined. In the case of a cache miss, the memory control circuit 90 is requested for the data "B0" and "B1" of the cache line of the address "b1". To do. As a result, the cache memory receives the data “A0” of the address “a0” from the memory control circuit 90, and the CPU 4
At the same time, the data is written in the data memory 2, and the data “B1” at the address “b1” is requested to the memory control circuit 90. Then, the data “B1” at the address “b1” is received and transferred to the CPU 4, and at the same time the data memory 2
Write in. After that, the data "A" at the address "a1"
1 ”and the data“ B0 ”of the address“ b0 ”are sequentially received and written in the data memory 2.

The operation of the cache memory for each clock will be described below with reference to FIGS. 1 and 2. In addition, in FIG. 2, reference numerals 1a to 18b indicate periods of each clock. (Period 1a) The CPU 4 sets the request signal 60 to the high level and sets the address “a0” as the request address.
Is output to the bus 51. At this time, since the acknowledge signal 63 output from the memory control circuit 90 is at low level, the control unit 3 sets the read / write enable signal 13 at high level.

(Period 1b) Address "a0" of the bus 51
Is latched by the latch 7 and output to the bus 50. Further, since the read / write enable signal 13 is at the high level, the selector 20 outputs the select unit of the address “a0” of the bus 50 to the bus 52.

Further, the tag memory 1 selects an entry using the selector of the address "a0" of the bus 52 and outputs the tag address TA1 of the selected entry to the bus 53. In addition, the comparison circuit 8 uses the address “a” of the bus 50.
Compare the tag part of "0" and the tag address of the bus 53,
When they match, that is, when a cache hit occurs, the hit signal 10 is set to a high level, and when they do not match, that is, a cache miss, the hit signal 10 is set to a low level. Since the example of the cache miss is shown in FIG. 2, the hit signal 10 is at the low level.

Further, the data memory 2 selects an entry by using the select part of the address "a0" of the bus 52,
The data of the selected entry ET0 is output to the bus 58, and the data of the entry ET1 is output to the bus 59. Further, the selector 21 selects one of the bus 58 and the bus 59 by using the most significant bit of the offset part of the address “a0” of the bus 50. Here, since the bus 50 has the address “a0”, the bus 58 is selected and the data of the entry ET0 is output to the bus 57.

Further, the control section 3 determines that the request signal 60 is at the high level and the state machine M1 is in the S state.
Since it is 0, the state of the state machine M0 is set to S1. As a result, the control unit 3 causes the latch enable signal 11
To high level. (Period 2a) The CPU 4 sets the request signal 60 to the high level and outputs the address "b1" to the bus 51.

Since the latch enable signal 11 is at the high level, the latch 5 latches the address "a0" of the bus 50 and outputs it to the bus 55. Since the hit signal 10 for the address "a0" is at the low level and the state machine M0 is in the state S1, the control unit 3 controls the selector 22 by using the control signal 19 to change the address "a0" of the bus 55 to the address "a0". It is output to the bus 54 as a request address to the memory control circuit 90. At the same time, the request signal 62 to the memory control circuit 90 is set to high level.

The state of the state machine M0 of the control unit 3 is S
Since it is 1, and the state of the state machine M1 is S0, the read / write enable signal 13 is set to the high level.
The latch 96 latches the data on the bus 57 and
Output to. The latch 97 latches the hit signal 10,
The signal 95 is output. The tri-state buffer 98 sets the bus 70 to high impedance because the signal 95 is at low level. That is, since it is a mishit operation, the data on the bus 48 is not used.

(Period 2b) Address "b1" is latched 7
Is latched by and output to the bus 50. Since the read / write enable signal 13 is at high level, the selector 20
The bus 50 is selected, and the selector unit of the address “b1” of the bus 50 is output to the bus 52. Tag memory 1 is bus 52
An entry is selected using the selector unit of the address "b1" of and the tag address TA2 is output to the bus 53.

The comparator circuit 8 includes a tag portion of the bus 50 and a bus 53.
The tag signal TA2 is compared with the tag address TA2 and the hit signal 10 is set to the high level when they match, and the hit signal 10 is set to the low level when they do not match. FIG. 2 shows an example of non-coincidence, so it is at a low level. The data memory 2 selects an entry using the selector unit of the address “b1” of the bus 52, outputs the data of the entry ET0 to the bus 58, and outputs the data of the entry ET1 to the bus 59.

The selector 21 selects the address "b" of the bus 50.
The bus 58 or the bus 59 is selected by using the most significant bit of the offset portion of "1" and output to the bus 57. Since the address is "b1" here, the bus 59 is selected. In the control unit 3, since the request signal 60 is at the high level and the state of the state machine M0 is not S0, the state of the state machine M1 is set to S1.

The state of the state machine M1 of the control unit 3 is S
Since it becomes 1, the latch enable signal 12 becomes high level. Since the state of the state machine M0 is S1,
Set it to S2. Since the state of the state machine M0 has changed to S2, the data request signal 64 is set to high level. As a result, the memory control circuit 90 reads the data “A0” from the memory 99.

(Period 3a) Since the latch enable signal 12 is at the high level, the latch 6 latches the address "b1" of the bus 50 and outputs it to the bus 56. The hit signal 10 for the address "b1" is at low level,
Moreover, since the state of the state machine M1 is S1, the control unit 3 controls the selector 22 using the control signal 19 and outputs the address "b1" of the bus 56 to the bus 54 as a request address to the memory control circuit 90. .. Further, the control unit 3 sets the request signal 61 to the memory control circuit 90 to the high level.

The latch 96 latches the data on the bus 57 and outputs it to the bus 48. Latch 97 is hit signal 10
Are latched and output to the signal 95. The tri-state buffer 98 sets the bus 70 to high impedance because the signal 95 is at low level. That is, since it is a mishit operation, the data on the bus 48 is not used. (Period 3b) Since the state of the state machine M1 is S1, it is set to S2.

(Period 4a) Since the state machine M0 is in the state S2 and the state machine M1 is in the state S2, the control unit 3 uses the control signal 19 to select the selector 22.
And outputs the address “a0” of the bus 55 to the bus 54. That is, the cache memory responds to the two request addresses “a0” and “b1” from the CPU 4 with the first data “A1” (C
Since the PU4 is waiting for the requested data), the first request address "a0" is prioritized.

(Period 4b) The latch 81 latches the address "a0" of the bus 54 and outputs it to the bus 49. (Periods 5a to 6b) The state is waiting for the data "A0" from the memory control circuit 90. (Period 7a) Since the data request signal 64 is at the high level, the memory control circuit 90 outputs the data "A0" corresponding to the address "a0" to the bus 70 and sets the acknowledge signal 63 to the high level.

Since the data "A0" is the data requested by the CPU 4, the acknowledge signal 61 for the CPU 4 is set to the high level. The CPU 4 can receive the data “A0” on the bus 70. The latch 80 latches the data “A0” on the bus 70 and outputs it to the bus 71. (Period 7b) The state of the state machine M0 is S2,
Since the acknowledge signal 63 is at high level, the read / write enable signal 13 is set at low level.

When the read / write enable signal 13 becomes low level, the selector 20 outputs the selector portion of the address “a0” of the bus 49 to the bus 52. The tag memory 1 selects one entry using the selector unit of the bus 52. Since the read / write enable signal 13 is at the low level, the tag memory 1 is in the address "a" of the bus 49.
Write the tag portion of "0" to the selected entry.

The selector 93 outputs the most significant bit of the offset portion of the address “a0” of the bus 49, which is controlled by the control signal 94, to the signal 92. The data memory 2 is
One of the entries is selected using the selector section of the bus 52. Since the read / write enable signal 13 is at the low level, the data memory 2 writes the data “A0” on the bus 71 to the selected entry. At this time, the signal 92 is used to write to the entry ET0 or the entry ET1.
Here, the entry ET0 is written.

The state of the state machine M0 of the control unit 3 is changed to S
Change from 2 to S3. The state of the state machine M0 of the control unit 3 is S3, and the state of the state machine M1 is S2.
Therefore, the data request signal 64 is set to low level and the data request signal 65 is set to high level. As a result, the memory control circuit 90 reads the data “B1” from the memory 99.

(Period 8a) State machine M of control unit 3
Since the state of 0 is S3 and the state of the state machine M1 is S2, the control unit 3 controls the selector 22 using the control signal 19 and outputs the address "b1" of the bus 56 to the bus 54. In other words, the cache memory is CP
The second data "A1" for the first request address "a0" from U4 (data unnecessary for CPU4)
And waiting for the first data "B1" (data requested by the CPU 4) for the second request address "b1", but the second request address "b"
1 ”has priority.

(Period 8b) The latch 81 latches the address "b1" of the bus 54 and outputs it to the bus 49. Since the acknowledge signal 63 is at low level, the read / write enable signal 13 is set at high level. (Periods 9a to 11b) The state is waiting for the data "B1" from the memory control circuit 90.

(Period 12a) Data request signal 65
Is high level, the memory control circuit 90 causes the data "B1" for the second request address "b1".
Is output to the bus 70, and the acknowledge signal 63 is set to the high level. Since the data “B1” is the data requested by the CPU 4, the control unit 3 sets the acknowledge signal 61 to the high level for the CPU 4. CPU4 is bus 7
When the data "B1" of 0 is received, the next process can be started.

The latch 80 latches the data “B1” on the bus 70 and outputs it to the bus 71. (Period 12b) Since the state of the state machine M1 of the control unit 3 is S2 and the acknowledge signal 63 is at high level, the read / write enable signal 13 is set at low level. When the read / write enable signal 13 becomes low level, the selector 20 outputs the selector unit of the address “b1” of the bus 49 to the bus 52.

The tag memory 1 has the address "b" of the bus 52.
Select one entry using the selector unit of "1". Since the read / write enable 13 is at the low level, the tag memory 1 writes the tag portion of the address “b1” on the bus 49 into the selected entry. The selector 93 is controlled by the control signal 94 and outputs the most significant bit of the offset portion of the address “b1” of the bus 49 to the signal 92.

The data memory 2 selects one entry by using the selector unit of the address "b1" of the bus 52. Since the read / write enable signal 13 is at low level, the data memory 2 writes the data “B1” on the bus 71 to the selected entry. At this time, the signal 92 is used to write to the entry ET0 or the entry ET1.
Here, the entry ET1 is written.

The state of the state machine M1 of the control unit 3 is changed to S
Change from 2 to S3. The state of the state machine M0 of the control unit 3 is S3, and the state of the state machine M1 is S3.
Therefore, the data request signal 64 is set to the high level and the data request signal 65 is set to the low level. As a result, the memory control circuit 90 reads the data “A1”.

(Period 13a) Since the state of the state machine M0 is S3 and the state of the state machine M1 is S3, the control unit 3 uses the control signal 19 to select the selector 2
2 is controlled and the address “a1” of the bus 55 is output to the bus 54. (Period 13b) Latch 81 uses address "a" of bus 54
1 ”is latched and output to the bus 49.

(Period 14a-14b) Memory control circuit 9
It is in a state of waiting for data "A1" from 0. (Period 15a) Since the data request signal 64 is at the high level, the memory control circuit 90 outputs the data “A1” to the bus 70 and sets the acknowledge signal 63 to the high level.

The latch 80 latches the data “A1” on the bus 70 and outputs it to the bus 71. (Period 15b) Since the state of the state machine M0 is S3 and the acknowledge signal 63 is at high level, the read / write enable signal 13 is set at low level. When the read / write enable signal 13 becomes low level, the selector 20 outputs the selector unit of the address “a1” of the bus 49 to the bus 52.

The tag memory 1 has the address "a" of the bus 52.
Select one entry using the selector unit of "1". Since the read / write enable signal 13 is at the low level, the tag memory 1 writes the tag portion of the address “a1” on the bus 49 into the selected entry. The selector 93 is
Controlled by the control signal 94, the inverted signal of the most significant bit of the offset portion of the address “a1” of the bus 49 is output to the signal 92.

The data memory 2 selects one entry using the selector unit of the address "a1" of the bus 52. Since the read / write enable signal 13 is at the low level, the data memory 2 writes the data “A1” on the bus 71 to the selected entry. At this time, the signal 92 is used to write to the entry ET0 or the entry ET1.
Here, it is written in the entry ET1.

The state of the state machine M0 of the control unit 3 is changed to S
Change from 3 to S0. Since the state of the state machine M1 of the control unit 3 is S3, the data request signal 64 is set to low level and the data request signal 65 is set to high level. As a result, the memory control circuit 90 reads the data “B0” from the memory 99. (Period 16a) Since the state of the state machine M0 is S0 and the state of the state machine M1 is S3, the control unit 3
Controls the selector 22 using the control signal 19 and the bus 5
The address "b0" of 6 is output to the bus 54.

(Period 16b) The latch 81 latches the address “b0” of the bus 54 and outputs it to the bus 49. (Periods 17a to 17b) The state is waiting for the data "B0" from the memory control circuit 90.

(Period 18a) Data request signal 65
Is high level, the memory control circuit 90 outputs the data “B0” to the bus 70 and sets the acknowledge signal 63 to high level. The latch 80 is the data “B” of the bus 70.
0 ”is latched and output to the bus 71. (Period 18b) Since the state of the state machine M1 is S3 and the acknowledge signal 63 is at high level, the read / write enable signal 13 is set at low level.

When the read / write enable signal 13 goes low, the selector 20 selects the address "b" of the bus 49.
The selector unit of "0" is output to the bus 52. Tag memory 1
Selects one entry using the selector unit of the address "b0" of the bus 52. Read / write enable 13
Is low level, the tag memory 1 writes the tag portion of the address “b0” of the bus 49 into the selected entry.

The selector 93 is controlled by the control signal 94 and outputs the inverted signal of the most significant bit of the offset portion of the address “b0” of the bus 49 to the signal 92. The data memory 2 selects one entry using the selector unit of the address “b0” of the bus 52. Since the read / write enable signal 13 is at the low level, the data memory 2
Writes the data B0 on the bus 71 to the selected entry. At this time, the signal 92 is used to write to the entry ET0 or the entry ET1. Here, the entry ET0 is written.

The state of the state machine M1 of the control unit 3 is changed to S
Change from 3 to S0. As described above, according to the embodiment, the CP
From the time when the determination result of the first request address “a0” from U4 is a cache miss until the data “A0” corresponding to the request address “a0” that is the cache miss is received from the memory 99. To
By the determination means and the data transfer request output means, the CPU
By receiving a new second request address "b1" from 4, and determining whether the request address "b1" is a cache hit or a cache miss, a cache hit for the second request address "b1" is made. It is possible to eliminate the judgment of. Therefore, the waiting time of the CPU 4 can be reduced.

Further, the second request address "b
If a cache hit of "1" is determined and it is a cache miss, first, the data "A0" requested by the CPU 4 corresponding to the first request address "a0" is requested.
To the CPU 4, and then the data “B1” requested by the CPU 4 corresponding to the second request address “b1”.
Data to the CPU 4 and then the data “A0” and “B
Data of the same cache line as 1 ", that is, CPU
The data "A1" and "B0" which are not required by the No. 4 are transferred from the memory 99. That is, the data “A” corresponding to the first request address “a0” from the CPU 4
0 ”and the same cache line data“ A1 ”,
CPU corresponding to the second request address "b1"
4 preferentially transfers the data “B1” requested by No. 4 from the memory 99. As a result, the data "A1" that does not need to be transferred to the CPU 4 due to the second cache miss is transferred from the memory 99 to the cache memory for the CPU time.
The waiting time of 4 can be reduced.

In the embodiment, the CPU 4 makes a request once in one clock, but it may make a plurality of requests in one clock as in parallel processing such as the superscalar method. Further, the cache memory can obtain the same effect not only by the direct map method but also by the set associative method. Furthermore, the cache memory cache line does not have to be two bus transfers,
The effect increases as the number of times increases. In that case, it is better to provide the memory control circuit 90 with a read buffer for storing all the data of the cache line.

Further, the CPU 4 may be a memory at the preceding stage in the plurality of memory hierarchies, and the memory control circuit 90 may be the memory stage at the next stage. Further, in the embodiment, the cache memory accepts two requests from the CPU 4, but the number may be three or more, and a cache hit may occur in the requests from a plurality of CPUs 4.

Further, although this embodiment shows an embodiment corresponding to claim 2, even if it corresponds only to claim 1, the effect of speeding up can be obtained.

[0071]

According to the cache memory of the first aspect, from the time when the determination result of the first data transfer request by the determination means is a cache miss, the first data transfer that has this cache miss. Until the data corresponding to the request is received from the memory hierarchy of the next stage, the determining means and the data transfer request output means receive a new second data transfer request from the memory hierarchy of the previous stage, and the second data transfer request is received. By determining whether the data transfer request is a cache hit or a cache miss, it is possible to apparently eliminate the above determination for the second data transfer request.

As a result, it is possible to obtain a cache memory in which the access waiting time of the preceding memory hierarchy can be shortened. Further, according to the cache memory of the second aspect, in the cache memory of the first aspect, when data is transferred from the memory hierarchy of the next stage to the memory hierarchy of the previous stage by the data transfer means, the data is transferred to the memory hierarchy of the previous stage. It corresponds to the new second data transfer request output from the previous memory hierarchy rather than the data of the same cache line as the data corresponding to the first data transfer request that does not need to be stored. By preferentially transferring data, it is possible to preferentially transfer the data requested by the previous memory hierarchy from the next memory hierarchy to the previous memory hierarchy. As a result, it is possible to reduce the access waiting time of the previous memory hierarchy.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a cache memory according to an embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the cache memory.

FIG. 3 is a block diagram showing a configuration of a conventional cache memory.

[Explanation of symbols]

 1 Tag Memory 2 Data Memory 3 Control Unit 4 CPU (Previous Memory Hierarchy) 99 Memory (Next Memory Hierarchy) 8 Comparison Circuit 200 Holding Unit

Claims (2)

[Claims] 1. A cache memory interposed between a memory hierarchy of a previous stage and a memory hierarchy of a next stage, wherein a cache hit or a cache miss is determined for a data transfer request output from the memory hierarchy of the preceding stage. And a data transfer request output unit that holds the data transfer request and outputs the data transfer request resulting in the cache miss to the memory hierarchy of the next stage when the determination result is a cache miss, A data transfer unit that receives data corresponding to the data transfer request resulting in the cache miss from the memory layer of the next stage, transfers the data to the memory layer of the previous stage, and stores the data, From the time when the transfer request judgment result is a cache miss, the data transfer request that resulted in this cache miss During the period until the corresponding data is received from the memory hierarchy of the next stage, a new data transfer request is received from the memory hierarchy of the previous stage, and the determination means and the data transfer request output means are operated in response to the new data transfer request. Cache memory that you want to run. 2. When the data transfer means transfers data from the memory hierarchy of the next stage to the memory hierarchy of the previous stage, the data transfer request which does not need to be transferred to the memory hierarchy of the previous stage but needs to be stored is dealt with. 2. The cache memory according to claim 1, wherein the data corresponding to the new data transfer request output from the preceding memory hierarchy is preferentially transferred over the data on the same cache line as the data.