JPH05241880A - Microprocessor and emulator - Google Patents

Abstract

PURPOSE:To provide a technique enabling the external output of much more debug information with few number of exclusive lead terminal. CONSTITUTION:The number of exclusive lead terminal for a debug information output is reduced by providing a debug monitor 78 including a serial data transmission part 78A for converting the debug information of the inside of a chip into serial data and outputting it to the outside of the chip and a data transmission control part 78B for controlling the serial data output by this serial data transmission part 78A, converting the debug information at the inside of a processor 74 into serial data and outputting it to the outside of the chip.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for outputting debug information inside a chip of a microprocessor to the outside of the chip. Related to effective technology.

[0002]

2. Description of the Related Art A single-chip microcomputer is a CPU (Central Processing Unit)
The peripheral circuits required for the above are included in one semiconductor substrate, and in the case of a specific application or a specific user, a ROM holding an operation program thereof is built in.
On the other hand, a general-purpose single-chip microcomputer does not have its operation program built-in, and a necessary operation program is obtained from an external memory according to its application. In developing a system to which such a microcomputer is applied, an in-circuit emulator is used for debugging the application system and performing detailed evaluation of the system. Such in-circuit
The emulator is connected between a system development device such as a parent computer (host computer) for software development and an application device under development, and substitutes the function of a microprocessor (target microprocessor) included in the application device. On the other hand, it has a function as a debugger and supports detailed system debugging.

Incidentally, as an example of a document describing a single chip microcomputer, 1988 12
Published by Hitachi, Ltd. "Hitachi single-chip microcomputer H8 / 532, HD6475328,
HD6435328 Hardware Manual ”,
As an example of a document describing the in-circuit emulator, "Hitachi Microcomputer Technical Report (Vol. 2, No. 2)" issued by Hitachi Microcomputer Engineering Co., Ltd. on October 1, 1988 is available. is there.

[0004]

In order to output debug information of the emulation processor, for example, register value, port value, internal bus value, etc. to the outside, it is necessary to provide the processor with a plurality of dedicated read terminals.
However, due to the limitation of the number of lead terminals that can be attached to the package of the emulation processor, it is difficult to provide as many dedicated lead terminals as necessary to output all the information required for debugging to the outside. is there. Therefore, in the conventional emulation processor, the debug information output to the outside is limited.

An object of the present invention is to provide a technique capable of outputting more debug information to the outside with a small number of dedicated lead terminals.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, as a first means, a data transmission unit for converting debug information in the chip into serial data and outputting the serial data to the outside of the chip, and controlling the serial data output by the data transmission unit. And a data transmission control unit of (1) to configure a microprocessor. At this time, the data transmission control unit controls the data transmission unit so that the serial data output is performed at a predetermined time interval, and the serial data output is performed each time the debug information in the chip changes. Further, the serial data output can be performed when there is a data transfer request from the outside of the chip.

As a second means, the emulator is configured to include the microprocessor configured as described above and a conversion circuit for converting the debug information output from the microprocessor in serial format into parallel format. To do.

[0010]

According to the above means, the data transmission section is
The debug information inside the chip is converted into serial data and output to the outside of the chip, which enables the number of dedicated lead terminals required for external output of the debug information to be reduced.

[0011]

1 shows a system including an in-circuit emulator which is an embodiment of the present invention.

In FIG. 1, the in-circuit emulator includes an emulator main body 40 and a pod 70 coupled to the emulator main body 40 via an emulation bus 60. An interface cable 90 is connected to the pod 70 via a connector 76. The tip of the interface cable 90 is coupled to a target processor mounting socket (referred to as an IC socket or the like) provided in the target system 80 as a microprocessor application device. The pod 70 is provided with a socket 75, and an emulation processor 74 equivalent to a microprocessor to be mounted on the target system 80 is mounted on the socket 75, and the target program can be executed by the processor 74. .. This emulation processor 7
4 is provided with a plurality of lead terminals Pi, of which P1
From the lead terminal indicated by 00, debug information inside the chip is output as serial data as described later in detail. A conversion unit 73 for converting the serial data output from the lead terminal P100 into parallel data is coupled to the lead terminal P100, and the parallel output data of the conversion unit 73 is provided at the subsequent stage of the conversion unit 73. A latch circuit 72 for holding is arranged. The data held in the latch circuit 72 is the connector 7
1 to the emulator main body 40.

FIG. 2 shows a detailed configuration example of the emulator main body 40.

As shown in FIG. 2, the emulation bus 60 includes an emulation control circuit 42 for switching a predetermined state of the emulation processor 74 when the emulation processor 74 substitutes the function of the target microprocessor. Control circuit 4 for substantially stopping the execution of the target program by monitoring the control state of processor 74 for emulation and the state of emulation bus 60
3, a trace circuit 44 for sequentially tracing and storing addresses, data and control signals given to the emulation bus 60, and a proxy memory 41 for substituting a data memory or a program memory to be included in the target system 80, respectively. The emulation control circuit 42, the break control circuit 43, the trace circuit 44, and the substitute memory 41 are the system bus 45.
It is designed to be controlled by a control microprocessor (referred to as a control processor) 46 through. A host interface 47 is connected to the system bus 45, and a system development device 50 is connected via the host interface 47.

FIG. 3 shows a configuration example of the emulation processor 74.

As shown in FIG. 3, the emulation processor 74 is not particularly limited, but is a CPU (central processing unit) 3, a ROM having a storage capacity of 32 kbytes.
(Read-only memory) 5, RAM (random access memory) 7 having a storage capacity of 1 kbyte, timer 9, serial communication interface (S
CI) 11, A / D converter 13, interrupt controller 1
5, the first to ninth ports 21 to 29, and a functional block such as a debug monitor 78 for converting debug information in the chip into serial data, which are common to the internal address bus 31 and the internal data bus 33. They are connected and formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The built-in memory of the emulation processor 74 in this embodiment is the RAM 7 and the ROM 5, and the RAM 7 is used as a work area of the CPU 3 or a temporary storage area for data. Although not particularly limited, the ROM 5 has an operation program for a specific purpose or a specific user, and is constituted by the mask ROM 5. The ROM 5 has a large number of memory cell transistors arranged in a matrix, and information is written by, for example, selectively implanting ions into a predetermined memory cell transistor using a unique photomask based on the specifications required by the user.

Further, the processor 74 of this embodiment has a large number of lead terminals, for example, the first to ninth ports 21 to 29.
Lead terminals P10 to P17 coupled to the input / output terminals of
P20-P24, P30-P37, P40-P47, P
50-P57, P60-P63, P70-P77, P8
0 to P87, P90 to P97, and lead terminals P100 to P104 coupled to the debug monitor 78 are arranged. Here, P100 is the serial data D
A TXD output lead terminal, P101 is a serial clock DSCK output lead terminal for serial data output, and P102 to P104 are serial data transfer mode switching signal input lead terminals.

FIG. 4 shows a configuration example of the debug monitor 78.

As shown in FIG. 4, the debug monitor 78 is provided with on-chip debug information such as the third port 2.
Serial data transmitter 78A for converting the values of the third and fourth ports 24 into serial data and outputting the serial data to the outside of the chip
And a data transmission controller 78B for controlling serial data output by the serial data transmitter 78A. The serial data transmitter 78A is coupled to the internal data bus 33, the third port 23, and the fourth port 24,
The debug information obtained as parallel data is converted into serial data, which can be externally output from the lead terminal P100. The data transmission control unit 78B controls the serial data output. This data transmission control unit 78B
Is connected to lead terminals P102 to P104 for taking in a control signal for switching the data transfer mode, so that the debug information transfer mode can be switched from outside the chip. For example, it is possible to select a first mode in which serial data output of debug information is performed at predetermined time intervals or a second mode in which serial data output is started when a transfer request is made from outside the chip. In the second mode, the lead terminals P102 to P104 are used to fetch a serial data output start instruction from outside the chip. By configuring such that the debug information is output to the outside of the chip in a serial format, the dedicated terminal for outputting the debug information to the outside of the chip can use the serial data DTX.
D output lead terminal P100 and serial clock D
It becomes the lead terminal P101 for SCK output, and it is possible to reduce the number of dedicated terminals for outputting debug information, as compared with the conventional chip configured to output various debug information in parallel format outside the chip. In other words, by outputting the debug information in a serial format, it is possible to output more debug information to the outside with a small number of dedicated read terminals.

According to the above embodiment, the following operational effects can be obtained.

(1) By configuring the emulation processor including the debug monitor 78, the debug information inside the processor is converted into serial data and output to the outside of the chip. External output of more debug information is enabled.

(2) By providing the data transfer mode switching signal read terminals P102 to P104, the serial data transfer mode can be changed in response to a transfer mode request from the outside of the chip.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, the data transmission control unit 78B may control so that serial data output is performed every time the debug information inside the chip changes. Further, when the serial output of the debug information is performed at a predetermined time interval, the time interval may be changeable from outside the chip. Further, in the above embodiment, the values of the third port 23 and the fourth port 24 are converted into serial data and output to the outside of the chip. However, by expanding the internal bus, the values of other ports, Can be configured to output various information that can be used for debugging, such as values of various registers in the chip and internal bus values of the CPU 3, to the outside of the chip in a serial format.

In the above description, the case where the invention made by the present inventor is mainly applied to the emulation processor which is the field of application which is the background of the invention has been described. It can also be applied to real chips such as.

The present invention can be applied on condition that at least the target program to be debugged is executed.

[0028]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, since the debug information inside the chip is converted into serial data and output to the outside of the chip by the data transmission unit, it is possible to output more debug information to the outside with a small number of dedicated lead terminals. It

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a system including an in-circuit emulator according to an embodiment of the present invention.

FIG. 2 is a configuration block diagram of an emulator main body in the in-circuit emulator.

FIG. 3 is a configuration block diagram of an emulation processor mounted on the in-circuit emulator.

FIG. 4 is a configuration block diagram of a debug monitor included in the emulation processor.

[Explanation of symbols]

 3 CPU 5 ROM 7 RAM 9 Timer 11 SCI 13 A / D Converter 15 Interrupt Controller 21 1st Port 22 2nd Port 23 3rd Port 24 4th Port 25 5th Port 26 6th Port 27 7th Port 28 8th Port 29 9th port 40 Emulator main body 41 Proxy memory 42 Emulation control circuit 43 Break control circuit 44 Trace circuit 45 System bus 46 Control processor 47 Host interface 50 System development device 60 Emulation bus 71 Connector 72 Latch circuit 73 Converter 74 Emulation processor 75 socket section 76 connector 78 debug monitor 78A serial data transmission section 78B data transmission control section 80 target system 90 interface Source cable P10 to P17 Lead terminal P20 to P24 Lead terminal P30 to P37 Lead terminal P40 to P47 Lead terminal P50 to P57 Lead terminal P60 to P63 Lead terminal P70 to P77 Lead terminal P80 to P87 Lead terminal P90 to P97 Lead terminal P100 to P104 Lead Terminal

Claims (5)

[Claims] 1. In a microprocessor for executing a target program to be debugged, a data transmission unit for converting debug information in a chip into serial data and outputting the serial data to the outside of the chip, and this data transmission unit. And a data transmission control unit for controlling serial data output by the microprocessor. 2. The microprocessor according to claim 1, wherein the data transmission control unit controls the data transmission unit so that serial data output is performed at predetermined time intervals. 3. The microprocessor according to claim 1, wherein the data transmission control unit controls the data transmission unit so that serial data output is performed every time the debug information inside the chip changes. 4. The data transmission control unit controls the data transmission unit so that serial data output is performed when a data transfer request is made from outside the chip.
The described microprocessor. 5. The microprocessor according to claim 1, 2, 3 or 4, and a conversion circuit for converting debug information output from the microprocessor in serial format into parallel format, the processor comprising: An emulator that enables you to debug a target program by executing it.