JPH05235381A - Semiconductor device with capacitance - Google Patents

Abstract

PURPOSE:To obtain a capacitance of high capacity and low seriesresistance by forming a gate electrode and an ohmic electrode in a comb shape and by arranging them so as to mesh with each other. CONSTITUTION:An N-type conductive layer (N<+> layer) 21 is overlaid with a comb-shaped Schottky contact type electrode 23, and an N-type conductive layer 21 with a comb-shaped ohmic contact type electrode 22: the Schottky contact type electrode 23 and the ohmic contact type electrode 22 are so arranged as to mesh with each other, where the former is wider than the latter and used for the latter always at a negative bias lower than a Schottky reverse withstand voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a large capacitance formed in a semiconductor element that does not require a high breakdown voltage.

[0002]

2. Description of the Related Art Conventionally, as a structure of a capacitance formed in a semiconductor element, a parallel plate type as shown in FIG. 5 is generally used. Here, FIG.
5A is a sectional view of the capacitance, and FIG. 5B is a transparent plan view of the capacitance.

As shown in FIG. 5, in order to form a capacitance, an insulating film 3 is sandwiched between the metal electrodes 1 and 2. Due to the structure of this capacitance, a high breakdown voltage can be secured between both electrodes, and the series resistance is low. The capacitance value of the capacitance of this structure can be calculated by the following formula. C = Ε _o × Ε _r × (S / d) where, Ε _o is the vacuum dielectric constant, Ε _r is the relative dielectric constant of the insulating film 3, d is the film thickness of the insulating film 3, and S [Fig. ) Is the area of the metal electrodes 1 and 2 that sandwich the insulating film 3.

With this capacitance structure, an arbitrary capacitance can be created relatively easily, but the drawback is that when a large capacitance is formed, its area (region) becomes very large. If it is attempted to realize a large capacity by thinning the film thickness of the insulating film to avoid it, other adverse effects due to the thinning, for example, pinholes easily occur, and the reliability of the insulating film decreases. ..
In addition, the cross capacitance in other wirings becomes large, and the characteristics deteriorate, which makes it difficult to use in practice. Further, if an attempt is made to realize a large capacity by increasing the relative dielectric constant of the insulating film, this will change the properties of the insulating film itself, and the reliability such as moisture resistance will decrease. As described above, it is very difficult to form a large capacitance with this structure, whichever method is used.

As another conventional technique, there is a semiconductor device structure using a Schottky junction capacitance between an N-type semiconductor and a metal as shown in FIG. 6, though it is less general than the above structure. Here, FIG. 6A is a sectional view of the semiconductor device, and FIG. 6B is a plan view of the semiconductor device. In the figure, 11 is an N-type conductive layer (hereinafter referred to as N ⁺⁾ formed by selective ion implantation in a compound semiconductor such as GaAs.
Layer), 12 is an electrode that forms an ohmic contact with the N ⁺ layer (hereinafter referred to as an ohmic electrode), and 13 is an electrode that forms a Schottky junction with the N ⁺ layer (hereinafter referred to as a Schottky electrode or gate electrode). .. In this structure, as described above, since the Schottky junction formed by the N ⁺ layer 11 and the gate electrode 13 has a large junction capacitance,
A major feature of this is that a large capacitance can be easily formed in a small area by utilizing this. However,
With this structure, the breakdown voltage is relatively low due to the leakage current of the Schottky junction, but as described above in the prior art, a large capacitance that does not require a high breakdown voltage can be sufficiently realized.

FIG. 7 is a diagram showing the bias dependence of the Schottky junction capacitance. In this figure, the horizontal axis is the voltage [V] applied to the gate electrode with respect to the ohmic electrode, and the vertical axis is the junction capacitance [pF] at that time. At this time, the N ⁺ layer is 2 × 10 ¹³ cm ^-2 Si at 160 KeV.
Formed by implanting ions, the area of the gate electrode is 6400
μm ² .

[0007]

However, in the structure of the conventional semiconductor device having a capacitance as described above, the N ⁺ layer 11 itself must be considered as a part of the electrode as shown in FIG. As shown in (3), there is a problem that the amount of series resistance R becomes high, and it was difficult to use it purely as a capacitor. Note that FIG.
8A is a sectional view of a semiconductor device having the capacitance, and FIG. 8B is an equivalent circuit diagram thereof.

In order to eliminate the above-mentioned problem of high series resistance, the present invention improves the structure of the gate electrode and the ohmic electrode to provide a semiconductor device having a large capacitance and a low series resistance. Is intended to provide.

[0009]

In order to achieve the above object, the present invention forms an ohmic contact type electrode and a Schottky contact type electrode on an N type conductive layer formed in a compound semiconductor by selective ion implantation. In a semiconductor device having a capacitance having the above structure, a comb-tooth-shaped Schottky contact type electrode is provided on the N-type conductive layer, and a comb-tooth-shaped ohmic contact-type electrode is provided on the N-type conductive layer. Contact type electrodes and ohmic contact type electrodes are alternately arranged in mesh with each other, and the width of the Schottky contact type electrodes is wider than the width of the ohmic contact type electrodes, and the Schottky contact type electrodes are the ohmic contacts. The contact type electrode is always used with a negative bias lower than the Schottky reverse breakdown voltage.

[0010]

According to the present invention, as described above, N ⁺ formed by selective ion implantation into a compound semiconductor such as GaAs.
By utilizing the junction capacitance generated by Schottky junction of the gate electrode to the layer, when forming a large capacitance, the gate electrode and the ohmic electrode are formed in a comb-teeth shape, by arranging in mesh with each other, By dividing the high resistance N ⁺ layer in parallel to reduce the resistance, a large capacity and a low series resistance can be obtained.

[0011]

Embodiments of the present invention will be described in detail below with reference to the drawings. 1 is a block diagram of a semiconductor device having a capacitance showing an embodiment of the present invention.
1A is a plan view of the semiconductor device, and FIG. 1B is FIG.
1A is a sectional view taken along the line AA, and FIG. 1C is B in FIG. 1A.
It is a -B line sectional view.

As described above, the series resistance becomes high in the structure of the semiconductor device having this capacitance. However, as shown in the figure, by changing the structure of each electrode into a comb-tooth shape, the resistance component is changed. Can be significantly reduced. In the figure, 21 is an N ⁺ layer formed by selective ion implantation in a compound semiconductor such as GaAs, and 22 is the N ⁺ layer.
Comb-tooth-shaped ohmic electrode (ohmic contact electrode) forming an ohmic junction with the ⁺ layer 21, 23 is the N ⁺ layer 2
1 is a comb-teeth-shaped gate electrode (Schottky contact type electrode) in which a Schottky junction is formed.

Therefore, the comb-teeth-shaped ohmic electrode 22 and the comb-teeth-shaped gate electrode 23 mesh with each other and are arranged in an interdigitator shape. In addition, the comb-shaped ohmic electrode 2
In order to increase the capacitance by 2, the width D _G of the comb-tooth-shaped gate electrode 23 is configured to be wider than the width D _O of the comb-tooth-shaped ohmic electrode 22.

In this embodiment, the comb-shaped gate electrode 23 is formed.
2 pairs of comb-teeth structures are formed by the comb-teeth-shaped ohmic electrode 22. However, in effect, the N ⁺ layer 21 is divided into four in parallel, and the resistance component is reduced to 1/16. Has been reduced. For example, assuming that the sheet resistance of the N ⁺ layer 21 is 165Ω, in order to reduce the resistance to a level at which this capacitance can be practically used, at least 8 divisions (at this time, the resistance component becomes 1/64). Since splitting is needed,
It is necessary to form four or more pairs of comb-shaped structures.

When this capacitance is put into practical use, the Schottky reverse breakdown voltage is low as described above,
The condition is that the gate electrode is always used with a negative bias lower than the Schottky reverse breakdown voltage with respect to the ohmic electrode. FIG. 2 is a plan view of a semiconductor device having a capacitance showing another embodiment of the present invention.

In this figure, 31 is an N ⁺ layer, 32 is an ohmic electrode, and 33 is a gate electrode. In this embodiment, an ohmic electrode 32 having a shape in which comb-shaped electrode portions 32b extend from the central conductive portion 32a to the left and right is formed on the N ⁺ layer 31, and the gate electrode 33 surrounds the ohmic electrode 32. Are formed.

Because of this structure, ohmic
The electrode 32 and the gate electrode 33 have a comb-shaped structure of 7 pairs.
Is equivalent to Therefore, N of the ohmic electrode 32⁺
It means that the layer 31 is divided into 13 parts,
It has been reduced to 169. Where N⁺Implantation conditions for layer 31
Is 160 KeV 2 × 10¹³cm^-2Then, the gate electrode 33
Is biased to -0.5V with respect to the ohmic electrode 32.
The capacitance is 31.2pF and the series resistance is about 2Ω.
Met. The area is 23000 μm ²Is.

The most effective use method of the semiconductor device having the capacitance of the present invention thus constructed is the bypass capacitor Cs in the self-bias circuit as shown in FIG. This bypass capacitor Cs
Is connected in parallel with the resistor Rs, and a large voltage is not applied to both ends of the resistor Rs. Therefore, it is not necessary to have a withstand voltage and only a large capacitance is required, which is suitable for using the capacitance of the present invention. .. In FIG. 3, C _IN and C _OUT are capacitors, R _g is a resistor, FET is a field effect transistor, and V _dd is a DC voltage.

Further, the semiconductor device having the capacitance of the present invention can be applied to the decoupling capacitance C _g on the FET gate side as shown in FIG. In addition,
In FIG. 4, C _IN and C _OUT are capacitors, R _g is a resistor, L is a capacitor, FET is a field effect transistor, and V _gg is a DC voltage (DC voltage applied between the gate and ground).

Here, comparing the conventional parallel plate type capacitance shown in FIG. 5 with the capacitance of the present invention, for example, the parallel plate type capacitance of FIG. 5 (insulating film thickness 1500 Å, relative dielectric constant: Therefore, to form 31.2 pF as shown in FIG. 1, an area of 75000 μm ^{2 is} required. That is, by using the capacitance of the present invention, the area can be reduced by about 1/3.

The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the present invention, which are not excluded from the scope of the present invention.

[0022]

As described above in detail, according to the present invention, the junction capacitance generated by the Schottky junction of the gate electrode to the N ⁺ layer formed by the selective ion implantation in the compound semiconductor such as GaAs. When a large capacitance is formed by using, the gate electrode and the ohmic electrode are formed in a comb-teeth shape and arranged in mesh with each other, whereby the high resistance N ⁺ layer is divided in parallel to reduce the resistance. It is possible to obtain a large capacitance and a low series resistance.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor device having a capacitance according to an embodiment of the present invention.

FIG. 2 is a plan view of a semiconductor device having a capacitance according to another embodiment of the present invention.

FIG. 3 is a circuit diagram showing an application example of a semiconductor device having a capacitance of the present invention.

FIG. 4 is a circuit diagram showing another application example of the semiconductor device having a capacitance of the present invention.

FIG. 5 is a configuration diagram of a conventional parallel plate type capacitance.

FIG. 6 is a configuration diagram of a conventional semiconductor device using a Schottky junction capacitance of an N-type semiconductor and a metal.

FIG. 7 is a diagram showing the bias dependence of the junction capacitance of a conventional Schottky.

8 is a diagram showing an equivalent circuit of the semiconductor device of FIG.

[Explanation of symbols]

21, 31 N ⁺ layer (N-type dielectric layer formed on compound semiconductor) 22, 32 Comb-tooth-shaped ohmic electrode (Ohmic contact-type electrode) 23, 33 Comb-tooth-shaped gate electrode (Schottky contact-type electrode)

Claims (1)

[Claims] 1. A semiconductor device having a capacitance having a structure in which an ohmic contact type electrode and a Schottky contact type electrode are formed on an N type conductive layer formed by selective ion implantation in a compound semiconductor, wherein (a) the N type A comb tooth-shaped Schottky contact type electrode is provided on the conductive layer, and (b) a comb tooth-shaped ohmic contact type electrode is provided on the N-type conductive layer, and (c) the Schottky contact type electrode and the ohmic contact are provided. Type electrodes and alternately arranged in a meshed shape, and the width of the Schottky contact type electrode is wider than the width of the ohmic contact type electrode, the Schottky contact type electrode with respect to the ohmic contact type electrode A semiconductor device having a capacitance characterized by being always used with a negative bias lower than the Schottky reverse breakdown voltage.