JPH05235174A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE:To provide the title manufacturing method capable of forming a wiring layer with high precision even on a rugged surface. CONSTITUTION:The title manufacturing method of semiconductor device is composed of the four steps enumarated as follows, i.e., a first step forming the first conductor layer 3 comprising an exposed light absorptive material on a rugged substrate l; a second step forming a resist pattern 5 by pattern exposing step after forming a photoresist film on the first conductor layer 3; a third step etching the first conductor layer 3 so as to locate the pattern edge on the recess of the rugged substrate l using the resist pattern 5 as a mask for removing the resist pattern 5; and a fourth step selectively growing the second conductor layer 6 on the first conductor layer 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to pattern formation on a substrate surface having irregularities.

[0002]

2. Description of the Related Art In recent years, with the high integration of semiconductor devices, miniaturization of circuits has been progressing, and miniaturization and multi-layering of wiring have been rapidly promoted.

Under such circumstances, it is inevitable that a wiring or other pattern is formed on an uneven surface. When wiring is provided on the uneven surface of a step in the photo-etching process, the resist pattern of the step concave portion may become abnormally thin due to the influence of the step convex portion, and the wiring may fall inside the contact hole. This phenomenon becomes particularly noticeable as the level difference increases.

For example, as shown in FIG. 2A, contact is made with both the surface of the silicon substrate 11 and the electrode 14 made of a polycrystalline silicon film formed on the upper surface of the silicon substrate 11 with the interlayer insulating film 12 interposed therebetween. A contact hole is formed in the interlayer insulating film 12, a Ti layer and a TiN layer as the barrier metal layer 13 and an Al—Cu—Si layer as the wiring layer 16 are sequentially deposited by sputtering, and then a resist pattern 15 is formed. The resist pattern of the step concave portion becomes thinner than the design size due to the influence of the reflected light (reverse beard) of the step convex portion. Then, when the wiring layer 16 and the barrier metal layer 13 are etched using the resist pattern 15 as a mask in this state, as shown in FIG. 2B, the wiring pattern in the stepped recess becomes thin and falls inside the contact hole, resulting in misalignment of patterning. In consideration of the above, the probability of occurrence of such a defect is extremely high, and the probability of causing a defect of the transistor is high.

[0005]

As described above, according to the conventional method, the pattern accuracy is lowered and the reliability is lowered, for example, the wiring layer formed in the stepped recess is thinned by the influence of reflection from the raised part. was there.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method capable of forming a wiring layer having high pattern accuracy even on a surface having irregularities.

[0007]

In the present invention, therefore, a first conductor layer made of a material that absorbs exposure light is formed on a substrate having irregularities, and the first conductor layer is formed on the first conductor layer. After forming a photoresist film, a resist pattern is formed by pattern exposure, and the first conductor layer is etched using the resist pattern as a mask so that the pattern edges come to the concave portions of the substrate having the concave and convex portions. Is removed, and the second conductor layer is selectively grown on the first conductor layer.

[0008]

According to the above structure, since the first conductor layer is made of a material having a light absorbing property to the exposure light, it is possible to prevent the reflection from the convex portion in the exposure process for forming the resist pattern. It can be prevented and the resist is not thinned. In addition, since the first conductor layer is patterned to form a highly accurate pattern and then the second conductor layer is selectively grown on the first conductor layer, it is possible to sufficiently form the contact hole in the contact hole. The wiring can be embedded, and not only the reliability of the wiring is improved, but also the contact resistance becomes uniform.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings.

1 (a) to 1 (c) are sectional views showing manufacturing steps of a semiconductor device according to an embodiment of the present invention.

First, (100) n having a specific resistance of 4 to 6 Ω / cm.
After forming a desired element region on the surface of the pattern silicon substrate 1,
A silicon oxide film 2a having a film thickness of 300 nm is formed by the CVD method. Then, an electrode layer 3 made of an n + polycrystalline silicon layer having a film thickness of 400 nm is formed, and a film thickness of 500 is further formed on the electrode layer 3.
A BPSG film 2b of nm is formed.

Next, a contact hole H is formed by reactive ion etching using the resist pattern formed in the photolithography process as a mask.

Then, a Ti layer 3a having a thickness of 20 nm and a thickness of 4 are formed.
A 2-layer structure film 3 with a 0 nm TiN layer 3b is deposited by a sputtering method, subjected to a heat treatment at 600 ° C. for 60 minutes in a nitrogen atmosphere for silicidation, and then coated with a resist to form a wiring by a photo-etching process The resist pattern 5 is left on (FIG. 1 (a)). At this time, the TiN layer 3b is dark brown and has a high light absorptivity, so that the resist pattern of the step concave portion does not receive reflection from the step convex portion and is not locally thinned to form a highly accurate mask pattern. be able to.

The two-layer structure film 3 is etched by RIE using the resist pattern 5 as a mask to form a pattern of the two-layer structure film 3 as shown in FIG. 1 (b). Here, the Ti layer has low resistance and can reduce contact resistance, and the TiN layer functions as a barrier metal layer. Further, since the two-layer structure film is thin, the pattern is well cut and good patterning is possible.

After that, a tungsten film 6 having a film thickness of 800 nm is selectively grown as a wiring layer only on the pattern of the two-layer structure film 3 by the selective CVD method using WF ₆ as a reactive gas.

Thus, the tag-stain film can be grown uniformly inside the contact hole H, and the wiring layer pattern has a pattern edge on the inclined portion near the opening of the contact hole H. Moreover, a highly accurate pattern can be obtained satisfactorily.

Although the TiN layer is used as a light-absorbing layer here, it is an essentially necessary layer as a barrier metal layer, and a highly accurate wiring pattern can be formed with a slight change in the steps. , Is a very effective method.

Although TiN is used as the light absorbing layer in the above-mentioned embodiment, TiCu, Ti may be used instead of TiN.
NCu, Ti carbide, Cu carbide, CuN or the like can be used.

The wiring layer is not limited to tungsten and may be any layer that can be formed by selective growth, such as a molybdenum silicide or aluminum layer or a three-layer film of aluminum-copper-silicon.

[0020]

As described above, according to the present invention, even when the pattern edge comes to the uneven surface, especially the steep slope near the opening of the contact hole, the film thickness is reduced. A uniform and highly accurate wiring can be embedded, and the reliability of the wiring is improved.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2a Silicon oxide film 2b BPSG film 3a Ti layer 3b TiN layer 4 Gate electrode 5 Resist pattern 6 Tungsten layer 11 Silicon substrate 12 Interlayer insulating film 13 Barrier metal layer (Ti-TiN) 14 Electrode 15 Resist pattern 16 Aluminum layer

Claims (1)

[Claims] 1. A first conductor layer forming step of forming a first conductor layer made of a light-absorbing material on exposure light on a substrate having unevenness, and a photoconductor on the first conductor layer. A photoresist coating step of forming a resist film, a resist pattern forming step of forming a resist pattern by pattern exposure, and the first conductor so that the pattern edge comes to the concave portion of the substrate having the unevenness using the resist pattern as a mask An etching step of etching the layer,
A selective growth step of removing the resist pattern and selectively growing a second conductor layer on the first conductor layer.