JPH05233355A - Maintenance diagnostic device - Google Patents

Abstract

PURPOSE:To read information out without stopping the operation of a device to be diagnosed by confirming that a write control circuit is not in operation and controlling a read of diagnostic information from a diagnostic information storage circuit when there is an instruction from a diagnosis controller. CONSTITUTION:The diagnostic information storage circuit 6 is stored with data of registers 1 and 4, a memory 2, and a register file 3, and the write control circuit 7 performs write control over the diagnostic information storage circuit 6. A read control circuit 8 generates addresses of entries in the diagnostic information storage circuit 6 corresponding to the register 1 or 4, memory 2, or register file 3 indicated from the diagnostic controller to read the information out, and sends it out to the diagnostic controller. When the write control circuit 7 is in writing operation, the read control circuit 8 inhibits reading operation and allows the reading operation after the writing operation ends to prevent read data from being injustice owing to a conflict between the writing and reading.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a maintenance / diagnosis apparatus used for diagnosing an information processing apparatus, and more particularly to a maintenance / diagnosis apparatus used for diagnosing processing when an information processing apparatus to be diagnosed is operating. is there.

[0002]

2. Description of the Related Art Conventionally, as a method for realizing this type of diagnosis, a firmware (FW) operating on a device to be diagnosed has been used.
To the diagnostic device by instructing the diagnostic device to read information by communication, and the firmware operating on the diagnostic device notifies the diagnostic device of the information read by communication, or the diagnostic device sends a micro instruction to the diagnostic device. A method has been adopted in which execution is stopped and reading is performed by hardware (HW) during the stop.

[0003]

In the above-mentioned conventional method, when the device under test tries to read out information while it is operating, the process being executed on the device under test is interrupted and the processing performance deteriorates. There were challenges.

[0004]

The maintenance diagnostic apparatus of the present invention is an information processing apparatus having a register and a memory and a register file for reading and writing data via a bus under the control of microinstructions. And a diagnostic information storage circuit having an entry corresponding to the register file, and the diagnostic information when detecting that the microinstruction instructs the register, the memory, or the register file to write from the bus. A write control circuit that supplies an address of an entry corresponding to the register or the memory or the register file to the storage circuit and that generates a signal for instructing the writing of data on the bus, and an instruction from the diagnostic control device. If there is the above write control circuit Sure that al the write operation is not performed are those having a read control circuit for performing diagnostic information readout control from the diagnostic data storage circuit. Further, a maintenance diagnosis device according to another invention of the present invention,
In the above, it has an address comparison circuit which detects a match between a read address designated by the read control circuit and a write address designated by the write control circuit, and a function of suppressing the read operation when the address comparison circuit detects a match. It has a read control circuit.

A maintenance diagnostic apparatus according to still another aspect of the present invention is the above-described apparatus, wherein a data buffer for storing data on the bus for one clock cycle between the bus and the diagnostic information storage circuit, and a micro-buffer. When the instruction is a write instruction from the bus to the register or the memory or the register file, the address buffer for storing the address of the corresponding entry of the diagnostic information storage circuit for one clock, and the microinstruction from the bus to the register or the register When it is a write instruction to the memory or the register file, it has a write control circuit having a function of writing the data in the data buffer to the entry of the diagnostic storage circuit indicated by the address buffer one clock after detecting this instruction. It is a thing. Also,
According to another aspect of the present invention, there is provided a maintenance / diagnosis apparatus according to the second aspect, wherein a data buffer for storing data on the bus for one clock cycle between the bus and the diagnostic information storage circuit, and a micro instruction for one clock. And an address corresponding to the register or the memory or the register file to the diagnostic information storage circuit when the microinstruction on the instruction buffer instructs writing to the register or the memory or the register file. And a write control circuit for generating a signal instructing to write the data stored in the data buffer.

[0006]

According to the present invention, in the diagnosis of the information processing device, the information of the device to be diagnosed is read out without stopping the operation of the device to be diagnosed.

[0007]

1 is a block diagram showing an embodiment of the present invention, showing an embodiment of the first invention. In FIG. 1, 1 and 2 and 3 are a register, a memory and a register file for reading and writing data via a bus 5 under the control of microinstructions. Reference numeral 6 is a diagnostic information storage circuit having entries corresponding to the register 1, the memory 2 and the register file 3, and 7 is a microinstruction for instructing the register 1 or the memory 2 or the register file 3 to perform a write operation from the bus 5. When this is detected, the write control circuit 8 supplies the address of the entry corresponding to the register 1 or the memory 2 or the register file 3 to the diagnostic information storage circuit 6 and generates a signal for instructing the writing of data on the bus 5.
Is the write control circuit 7 when there is an instruction from the maintenance diagnostic device.
This is a read control circuit for confirming that the write operation from is not performed and controlling the read of the diagnostic information from the diagnostic information storage circuit 6.

Next, the operation of the embodiment shown in FIG. 1 will be described. First, the registers 1 and 4, the memory 2 and the register file 3 are read and written via the bus 5 according to the instruction of the micro instruction. The diagnostic information storage circuit 6 stores the data on the registers 1 and 4, the memory 2 and the register file 3. Here, the diagnostic information storage circuit 6 is composed of a memory in which a read path and a write path exist independently.

Next, the write control circuit 7 is a write control circuit for the diagnostic information storage circuit 6, and when a write operation to the registers 1 and 4 or the memory 2 or register file 3 is detected by analyzing the microinstruction, the corresponding entry is detected. An address is generated and a diagnostic information storage circuit 6
A write instruction signal for writing is generated. The read control circuit 8 is a read control circuit from the diagnostic information storage circuit 6 and corresponds to the register 1, 4 or the memory 2 or the register file 3 designated by the diagnostic control device.
The address of the upper entry is generated, the information is read, and the information is sent to the diagnostic control device. When the write control circuit 7 is performing the write operation, the read control circuit 8 suppresses the read operation and this write control circuit 7
By performing the read operation after the write operation by the above is completed, it is possible to prevent the read data from being illegal due to the conflict between the write and the read.

FIG. 2 is a block diagram showing another embodiment of the present invention, showing an embodiment of the second invention. This Figure 2
In FIG. 1, the same reference numerals as those in FIG. 1 indicate corresponding parts, and 9 is an address comparison circuit for detecting the coincidence between the read address designated by the read control circuit 8 and the write address designated by the write control circuit 7. The read control circuit 8 has a function of suppressing the read operation when the address comparison circuit 9 detects a match.

Next, the operation of the embodiment shown in FIG. 2 will be described. First, the operation of the same portion as that of FIG. 1 is the same, and thus the description thereof is omitted here. Next, the address comparison circuit 9 is an address comparison circuit for comparing addresses generated by the write control circuit 7 and the read control circuit 8 with respect to the diagnostic information storage circuit 6, and the read control circuit 8 outputs a match detection signal for detecting a match between the addresses. The read control circuit 8 suppresses the read operation, thereby suppressing the data fraud caused by the conflict between the write and the read.

FIG. 3 is a block diagram showing still another embodiment of the present invention, showing an embodiment of the third invention. In FIG. 3, the same reference numerals as those in FIG. 2 indicate corresponding parts, 10 is a data buffer for storing data on the bus between the bus 5 and the diagnostic information storage circuit 6 for one clock cycle, and 11 is a microinstruction. From bus 5 to registers 1 and 4
In the case of a write instruction to the memory 2 or the register file 3, the address buffer stores the address of the corresponding entry of the diagnostic information storage circuit 6 for one clock. Then, when the microinstruction is a write instruction from the bus 5 to the registers 1, 4 or the memory 2 or the register file 3, the write control circuit 7 outputs the diagnostic information storage circuit 6 indicated by the address buffer 11 one clock after detecting this instruction. Data buffer 10 for entry
It has a function to write the above data.

Next, the operation of the embodiment shown in FIG. 3 will be described. First, the operation of the same portion as that of FIG. 2 is the same, and thus the description thereof is omitted here. Address buffer 1
1 holds the address of the diagnostic information storage circuit 6 corresponding to the case where the microinstruction instructs writing to the registers 1, 4 or the memory 2 or the register file 3. The data buffer 10 temporarily stores the data on the bus 5. Then, when the write control circuit 7 for the diagnostic information storage circuit 6 analyzes the micro instruction and detects the write operation for the registers 1, 4 or the memory 2 or the register file 3, the diagnostic information storage shown in the address buffer 11 is performed one clock later. The data in the data buffer 10 is written in the entry on the circuit 6. As described above, since the data on the bus 5 is written to the diagnostic information storage circuit 6 via the data buffer 10, the delay time condition is relaxed. Next, the read control circuit 8 sends a read address and a read instruction signal to the diagnostic information storage circuit 6 in accordance with an instruction from the diagnostic control device to control the reading of diagnostic information. When the address comparison circuit 9 that compares the write address and the read address detects a match, the read operation is suppressed and the conflict between the read and the write is avoided.

FIG. 4 is a block diagram showing another embodiment of the present invention, which shows an embodiment of the fourth invention. This Figure 4
In FIG. 2, the same reference numerals as those in FIG.
Is a data buffer for storing the data on the bus 5 between the bus 5 and the diagnostic information storage circuit 6 for one clock cycle,
An instruction buffer 12 stores microinstructions for one clock. Then, when the microinstruction on the instruction buffer 12 instructs the writing to the registers 1 or 4 or the memory 2 or the register file 3, the writing control circuit 7 instructs the diagnostic information storage circuit 6 to register 1 or 2.
4 or memory 2 or register file 3 to supply an address corresponding thereto and generate a signal for instructing writing of data stored in the data buffer 10.

Next, the operation of the embodiment shown in FIG. 4 will be described. First, the operation of the same portion as that of FIG. 2 is the same, and thus the description thereof is omitted here. Data buffer 10
Temporarily stores the data on the bus 5. The write control circuit 7 is a write control circuit for the diagnostic information storage circuit 6,
When a micro-instruction on the instruction buffer 12 is analyzed and a write operation to the registers 1, 4 or the memory 2 or the register file 3 is detected, the data buffer 1 is added to the entry on the diagnostic information storage circuit 6 indicated by the instruction buffer 12.
Write the data on 0. Next, the read control circuit 8
Controls the reading of diagnostic information by sending a read address and a read instruction signal to the diagnostic information storage circuit 6 according to an instruction from the diagnostic control device. When the address comparison circuit 9 that compares the write address and the read address detects a match, the read operation is suppressed and the conflict between the read and the write is avoided.

[0016]

As described above, according to the present invention, in the diagnosis of the information processing apparatus, the information of the apparatus to be diagnosed is read out without stopping the operation of the apparatus to be diagnosed. It is possible to read the data of the register, the memory, the register file and the like connected via the bus from the diagnostic control device without interrupting the process.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a block diagram showing another embodiment of the present invention.

[Explanation of symbols]

 1 register 2 memory 3 register file 4 register 5 bus 6 diagnostic information storage circuit 7 write control circuit 8 read control circuit 9 address comparison circuit 10 data buffer 11 address buffer 12 instruction buffer

Claims (4)

[Claims] 1. An information processing apparatus having a register, a memory and a register file for reading and writing data via a bus under the control of a micro instruction, and diagnostic information having an entry corresponding to the register, the memory and the register file. A memory circuit, and when the microinstruction detects that the register, the memory, or the register file is instructing a write operation from the bus, the diagnostic information memory circuit is instructed to the register, the memory, or the memory. A write control circuit that supplies an address of an entry corresponding to a register file and that generates a signal for instructing writing of data on the bus, and a write operation from the write control circuit is performed when instructed by a diagnostic control device. That you have not been forgiven A maintenance diagnostic device, comprising: a read control circuit for confirming and performing diagnostic information read control from the diagnostic information storage circuit. 2. The maintenance diagnosis device according to claim 1,
It has an address comparison circuit for detecting a match between a read address designated by the read control circuit and a write address designated by the write control circuit, and a read control circuit having a function of suppressing a read operation when the address comparison circuit detects a match. A maintenance diagnostic device characterized in that 3. The maintenance diagnosis device according to claim 2,
A data buffer for storing data on the bus for one clock cycle between the bus and the diagnostic information storage circuit, and when the microinstruction is a write instruction from the bus to a register or a memory or a register file, the diagnostic information storage circuit And an address buffer for storing the address of the corresponding entry for 1 clock, if the microinstruction is a write instruction from the bus to the register, the memory, or the register file, the address buffer 1 clock after the detection of this instruction The maintenance diagnostic apparatus has a write control circuit having a function of writing data in the data buffer to the entry of the diagnostic information storage circuit indicated by. 4. The maintenance diagnosis device according to claim 2,
A data buffer that stores data on the bus for one clock cycle between the bus and the diagnostic information storage circuit, an instruction buffer that stores microinstruction for one clock, and a microinstruction on this instruction buffer is the register or When writing to the memory or the register file is instructed, an address corresponding to the register or the memory or the register file is supplied to the diagnostic information storage circuit to write the data stored in the data buffer. A maintenance diagnosis apparatus having a write control circuit for generating a signal for instructing the maintenance.