JPH05226602A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device including a sufficient amount of impurity in an electrode of a fin-type capacitor without changing the film thickness by heat-treating the sample with an impurity containing interlayer film being brought into contact with a semiconductor film and then by diffusing in solid phase an impurity contained in the impurity containing interlayer film. CONSTITUTION:With semiconductor films 11, 13 and 16, which will become an accumulated electrode 18 of a capacitor, being brought into contact with impurity containing interlayer insulating films 10, 12, 14 and 17, the sample is heat-treated and thereby an impurity contained in the impurity containing interlayer insulating films 10, 12, 14 and 17 are diffused in solid phase into the semiconductor films 11, 13 and 16. Therefore, when a resistance of the semiconductor layers 11, 13 and 16, which will become the accumulated electrode 18, is made lower, an impurity does not pass through the semiconductor films 11, 13 and 16 and thereby enough amount of impurity can be doped. Because of this, enough amount of impurity can be doped only with one time heat treatment and therefore the surface of the semiconductor films is not oxidized during diffusion of an impurity and eventually, the accumulated electrode of the desired thickness can be formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a stack capacitor.

[0002]

2. Description of the Related Art A stack capacitor type DRAM cell has been proposed in which the storage electrode of the capacitor has a fin structure so that the storage capacity of the capacitor does not decrease even if the area occupied by one bit cell becomes small.

Since the fin type cell can utilize the lower surface region of the storage electrode as a capacitor, a large storage capacitance can be obtained. Further, the number of fins can be increased by increasing the number of layers, and a sufficient storage capacity can be obtained even if the cell area becomes small.

Next, an example of a method of manufacturing a fin type cell will be described with reference to FIG. First, as shown in Fig. 5 (a),
The semiconductor substrate 51 surface made of silicon, after forming the thick SiO ₂ film 52 of element isolation by selective oxidation method, SiO ₂
A gate insulating film 53 and a gate electrode 54 are formed in a region surrounded by the film 52, and then impurities are introduced into the semiconductor substrate 51 on both sides thereof to form, for example, an n-type source / drain (S /
D) Diffusion layers 55 and 56 are formed to form the transfer transistor TR.

The gate electrode 54 is connected to the word line WL of the memory cell formed of the same film. Then, as shown in the figure, an interlayer insulating film 57 is grown on the entire surface and is patterned to form a first S / D diffusion layer 55.
A window 58 is opened on the top and the S / D is passed through this window 58.
The bit line BL is connected to the diffusion layer 55.

Further, a SiN film 59 and a SiO ₂ film 60 are formed on the entire surface, and a polycrystalline silicon film 61 and a SiO ₂ film 6 are formed thereon.
After at least one layer of 2 is alternately stacked, for example, an n-type impurity is introduced into the polycrystalline silicon film 61 by vapor phase diffusion or ion implantation.

Next, as shown in FIG. 5 (b), the uppermost SiO ₂
A layer below the film 62 is patterned to form a window 63 on the second S / D diffusion layer 56, and a second multi-layer is formed in the window 63 and along the uppermost SiO ₂ film 62. Crystalline silicon film 64
After forming, the n-type impurity is added to the polycrystalline silicon film 64 by vapor phase diffusion or ion implantation.

Next, as shown in FIG. 5C, the polycrystalline silicon films 64 and 61 and the SiO ₂ film 62 sandwiched between them are patterned by photolithography using a resist mask (not shown). , These membranes with a second S /
It is left on the D diffusion layer 56 and its peripheral region.

Subsequently, the SiO ₂ film 62 above the SiN film 59 is selectively removed by wet etching with hydrofluoric acid or the like to form a storage electrode 65 having a fin structure as shown in FIG. 5D. To be done. Further, when the capacitor dielectric film 66 and the counter electrode 67 are sequentially formed, the capacitor is completed by these.

After that, a fin type capacitor cell is completed by forming an interlayer insulating film, a wiring layer and the like which are not shown.

[0011]

By the way, as the integration degree is improved, the polycrystalline silicon film 6 to be the storage electrode 65 is formed.
Although the layers 1 and 64 have been thinned, if the impurities are introduced by an ion implantation method, the impurities are more likely to pass through the film as the layers are thinned.
There is an inconvenience that a sufficient amount of n-type impurities cannot be introduced into the inside and resistance cannot be reduced.

On the other hand, according to the vapor phase diffusion method, the polycrystalline silicon film 6 is formed by oxygen contained in the vapor phase diffusion.
Since the surfaces of the electrodes 1 and 64 are oxidized, there is a problem that the substantial film thickness of the storage electrode 65 is reduced or the film thickness of the dielectric film 66 on the surface is increased to reduce the storage capacitance.

Further, when the number of fins of the storage electrode 65 is increased, the number of steps for vapor phase diffusion of impurities or ion implantation is increased for each fin, which tends to increase the number of manufacturing steps.

The present invention has been made in view of the above problems, and a semiconductor device in which the electrode of the fin-type capacitor contains a sufficient amount of impurities without changing the film thickness and the labor of introducing the impurities can be reduced. It aims at providing the manufacturing method of.

[0015]

[Means for Solving the Problems]
(g), as illustrated in FIG. 3, a step of forming an electrode-forming semiconductor film on the substrate in contact with the impurity-containing interlayer film,
A step of solid-phase diffusing impurities contained in the impurity-containing interlayer film into the electrode-forming semiconductor film by heat treatment to reduce the resistance of the electrode-forming semiconductor film; A step of removing all of the impurity-containing interlayer film and using the remaining electrode-forming semiconductor film as a first electrode, and a step of removing the impurity-containing interlayer film along the surface of the electrode-forming semiconductor film exposed by the removal of the impurity-containing interlayer film. And a step of forming a dielectric film for a capacitor with the step of forming a second conductive film in contact with an exposed surface of the dielectric film for a capacitor. ..

Alternatively, as illustrated in FIGS. 1 to 3, insulating films 3, 7 and 9 are formed on the conductive layer 6 of the opposite conductivity type formed in the upper layer portion of the one conductivity type semiconductor layer 1. The insulating film 3,
7 or 9 directly or through the first impurity-containing interlayer film 10, the first electrode-forming semiconductor films 11 and 13 and the second impurity-containing interlayer films 12 and 14 in order of one layer each or alternately. A step of forming a layer and a step of patterning the second impurity-containing interlayer films 12, 14 to the insulating films 3, 7, 9 to form an opening 15 exposing the conductive layer 6 of the opposite conductivity type. And a step of stacking the second electrode-forming semiconductor film 16 on the upper surfaces of the second impurity-containing interlayer films 12 and 14 and the opening 15, and by heating all the impurity-containing interlayer films 10 and 10. , 1
Impurities in 2, 14 are solid-phase diffused into the first and second electrode forming semiconductor films 11, 13, 16 to form the first and second electrode forming semiconductor films 11, 13, 16. A step of reducing the resistance,
At least the one electrode forming semiconductor film 11 is patterned and left in the cell region including the opening 15,
A step of using the remaining fin-shaped first and second semiconductor films for electrode formation 11, 13, 16 as the first electrode 18, and containing all the impurities above the insulating films 3, 7, 9 Interlayer film
Step of removing 10, 12 and 14, and the impurity-containing interlayer film 1
A step of forming a dielectric film for a capacitor 19 along the surfaces of the first and second semiconductor films for electrode formation 11, 13, 16 exposed by removing 0, 12, 14; and the dielectric for a capacitor. And a step of forming a second electrode 20 in contact with the surface of the film 19 to achieve the semiconductor device manufacturing method.

Alternatively, the impurity-containing interlayer films 10, 12, 14
Are phosphorous glass, arsenic glass, and antimony glass.

[0018]

[Operation] According to the present invention, the semiconductor film 11, 13, 16 which becomes the storage electrode (first electrode) 18 of the capacitor is heated by heat treatment while the impurity-containing interlayer films 10, 12, 13 are in contact with each other. , The impurities in the impurity-containing interlayer film 10, 12, 13 to the semiconductor film 11, 13,
Solid phase diffusion to 16. Therefore, when reducing the resistance of the semiconductor layers 11, 13 and 16 which will be the storage electrodes 18, impurities are removed from the semiconductor film 1.
It does not pass through 1,13,16 and introduces a sufficient amount of impurities. Further, the surface of the semiconductor films 11, 13, 16 is not oxidized during the impurity diffusion, and the storage electrode 18 having a desired film thickness is formed.

Further, since the introduction of impurities is performed only once, the labor for introducing impurities can be reduced. The semiconductor films 11, 13, 16 that will be the storage electrodes 18 of the capacitors may be fin type, cylindrical type, box type, or the like. Also,
Examples of the impurity-containing interlayer films 10, 12, 13 include phosphorus glass, arsenic glass, antimony glass and the like.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. (A) Description of the first embodiment of the present invention FIGS. 1 to 3 are sectional views showing the steps of the first embodiment of the present invention,
FIG. 4 is a plan view showing the arrangement of each element of the first embodiment, and FIGS. 1 to 3 are sectional views taken along the line AA of FIG.

In FIGS. 1A and 4, reference numeral 1 is a p-type semiconductor substrate made of silicon, on the surface of which a SiO ₂ film 2 for element isolation is formed by a selective oxidation method.
Active region (transistor formation region) X surrounded by O ₂ film 2
A select transistor T is formed in the.

As shown in FIG. 1 (a), this selection transistor has a gate electrode 4 formed on a semiconductor substrate 1 with an insulating film 3 having a film thickness of 200 Å or less and the semiconductor substrate 1 on both sides thereof. The source / drain (S / D) layers 5 and 6 are formed by introducing n-type impurities such as phosphorus and arsenic. The gate electrode 4 is the word line WL of the memory cell.
It is formed integrally with.

In such a state, as shown in FIG. 1B, first, as shown in FIG. 1B, an interlayer insulating film 7 made of SiO ₂ , PSG or the like is formed on the entire surface, and then the interlayer insulating film 7 and the insulating film 3 are formed. Is patterned by photolithography to form an opening 8 on the first S / D layer 5.

Then, as shown in FIG. 1 (c), the word line
Bit line BL passing through the opening 8 in a direction orthogonal to WL
Are formed on the interlayer insulating film 7. After this, as shown in FIG. 1D, a film thickness of 5 is formed on the interlayer insulating film 7 and the bit line BL.
A silicon nitride film (SiN film) 9 of 00Å is laminated by a CVD method, and then a first PSG (phosphorus glass) film 10, a first polycrystalline silicon film 11, a second PSG film 12, and a second polycrystalline silicon film 12. CVD of the crystalline silicon film 13 and the third PSG film 14
Each is formed to a thickness of about 500Å by the method. The content of phosphorus in each PSG film 10, 12, 14 is 3 to.
It is about 8 wt%.

Next, a photoresist is applied, and this is exposed and developed to form a resist mask M having a window on the second S / D layer 6, and the PSG film 14 exposed from the window.
Is etched by a reactive ion etching method (RIE method) or the like, and subsequently, the polycrystalline silicon film 13 thereunder is etched.
To remove each layer underneath from the second S
The opening 15 for exposing a part of the / D layer 6 is formed (FIG. 2E). In this case, chlorine-based gas or fluorine-based gas is used as the etching gas.

After removing the resist mask M,
A third polycrystalline silicon film 16 and a fourth PSG film 17 are formed in the entire area including the inside of the opening 15 by 500 Å, respectively.
(FIG. 2 (f)), the phosphorus contained in the PSG films 10, 12, 14, 17 is solid-phase diffused into the polycrystalline silicon films 11, 13, 16 after heating (FIG. 2 (f)). As a result, the resistance of the polycrystalline silicon films 11, 13, 16 is reduced.

Thereafter, at least six layers of PSG from the top are formed by RIE or the like using a resist mask (not shown).
Films 12, 14, 17 and polycrystalline silicon films 11, 13,
16 is sequentially patterned to leave these films only on the second S / D layer 6 and its peripheral region, that is, the storage electrode forming region Y shown in FIG. 4 (FIG. 2 (g)). Immediately after this, the solid phase diffusion described above may be performed.

After removing the resist mask, S
All PSG films 10, 12, 14, above the iN film 9,
When 17 is removed by hydrofluoric acid, the upper and lower side surfaces of the first to third polycrystalline silicon films 11, 13 and 16 respectively spaced apart from the SiN film 9 are exposed, and the third polycrystalline silicon film is also exposed. The first and second polycrystalline silicon films 1 are formed by the portion of the film 17 formed vertically in the opening 15.
1 and 13 are supported, and these form the storage electrode 18 of the stack capacitor (FIG. 4 (h)).

Thereafter, as shown in FIG. 3 (i), a silicon nitride film is uniformly formed along the surface of the storage electrode 18 by the CVD method, and the surface is slightly thermally oxidized to form this film as a capacitor. Of the dielectric film 19. Furthermore, the storage electrode 18
Impurity-containing polycrystalline silicon is formed by the CVD method between the surface of the capacitor and the surface thereof, and this is patterned to form the counter electrode 20 of the capacitor.

As a result, the capacitor is completed. An interlayer insulating film, a wiring layer, etc. are further formed on the capacitor, and the DRAM is formed.
The cell will be completed. As described above, the storage electrode 1
Forming the PSG films 10, 12, 14, 17 on the upper surface or the lower surface of the polycrystalline silicon films 11, 13, 16 constituting
Since phosphorus, which is an n-type impurity contained in the PSG films 10, 12, 14 and 17, was solid-phase diffused into the polycrystalline silicon films 11, 13 and 16, the film thickness of the polycrystalline silicon films 11, 13 and 16 was reduced. Even if it becomes thinner, impurities will be surely introduced into it. Moreover, since the polycrystalline silicon films 11, 13 and 16 are not placed in an oxidizing atmosphere when introducing impurities, their surfaces are not oxidized and their effective film thickness is not reduced.

As the interlayer film grown on either the upper or lower surface of the polycrystalline silicon film to be the storage electrode, arsenic glass, antimony glass, or other impurity-containing material may be used in addition to PSG.

The film forming the storage electrode of the capacitor may be made of another semiconductor of polycrystalline silicon as long as it is a material that remains when the impurity-containing glass is removed. Furthermore, in the above-described embodiment, the PSG film 17 is formed on the uppermost polycrystalline silicon film 16, but it may be omitted if the introduction of impurities is sufficient by the PGS film 14 and the like under the PSG film 17.

(B) Description of Other Embodiments of the Present Invention In the above-mentioned embodiments, the storage electrode having three fins has been described, but this may be one, two or four or more. It is applicable in the same manner, and an impurity-containing interlayer film may be formed on at least one surface side of the semiconductor film to be the storage electrode, and the impurities may be solid-phase diffused.

Further, the fins of the lowermost layer of the storage electrode having a plurality of fins may be in a state of being lifted from the SiN film as described above, or may be in contact with the SiN film and the dielectric film on the upper surface side, facing the SiN film. The electrodes may be formed.

Further, although the fin type stack capacitor has been described in the above-mentioned embodiments, it is also possible to form the storage electrode by making the semiconductor layer conductive in cylindrical type, box type, tunnel type and other stack capacitors. The same applies.

[0036]

As described above, according to the present invention, heat treatment is performed while the impurity-containing interlayer film is in contact with the semiconductor film to be the storage electrode (first electrode) of the capacitor.
Since the impurities in the impurity-containing interlayer film are solid-phase-diffused into the semiconductor film, the impurities do not pass through the semiconductor film when the resistance of the semiconductor layer to be the storage electrode is reduced, and a sufficient amount of impurities are Can be introduced.

Moreover, the surface of the semiconductor film is not oxidized during the impurity diffusion, and the storage electrode having a desired film thickness can be formed. Further, since the introduction of impurities is performed only once, it is possible to reduce the time and effort required for introducing the impurities.

[Brief description of drawings]

FIG. 1 is a sectional view (1) showing a process of an embodiment of the present invention.

FIG. 2 is a sectional view (No. 2) showing a step of the embodiment of the present invention.

FIG. 3 is a sectional view (3) showing a process of an example of the present invention.

FIG. 4 is a plan view showing an example of an apparatus formed according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view showing an example of a conventional manufacturing process.

[Explanation of symbols]

1 semiconductor substrate 2 SiO ₂ film 3 gate insulating film 4 gate electrode 5, 6 S / D layer 7 interlayer insulating film 8 opening 9 SiN film 10, 12, 14, 17 PSG film (impurity-containing interlayer film) 11, 13, 16 Silicon Film (Semiconductor Film) 15 Opening 18 Storage Electrode 19 Dielectric Film 20 Counter Electrode T Transfer Transistor BL Bit Line WL Word Line

Claims (3)

[Claims] 1. A step of bringing an impurity-containing interlayer film into contact with an electrode-forming semiconductor film to form it on a substrate, and a heat treatment to fix impurities contained in the impurity-containing interlayer film to the electrode-forming semiconductor film. A step of phase-diffusing to reduce the resistance of the electrode-forming semiconductor film, and removing all of the impurity-containing interlayer film in contact with the electrode-forming semiconductor film to leave the remaining electrode-forming semiconductor film as a first layer. And a step of forming a capacitor dielectric film along the surface of the electrode-forming semiconductor film exposed by removing the impurity-containing interlayer film, and on the exposed surface of the capacitor dielectric film. And a step of forming a second conductive film by bringing them into contact with each other. 2. An insulating film (3, 3) is formed on a conductive layer (6) of opposite conductivity type formed on an upper layer portion of the one conductivity type semiconductor layer (1).
7, 9) are formed, and a first electrode forming semiconductor film (11, 13) is formed on the insulating film (3, 7, 9) directly or via the first impurity-containing interlayer film (10). Forming a second impurity-containing interlayer film (12, 14) one layer at a time or alternately forming a plurality of layers, and from the second impurity-containing interlayer film (12, 14) to the insulating film (3, 7, 9). ) To form an opening (15) exposing the conductive layer (6) of the opposite conductivity type, the upper surface of the second impurity-containing interlayer film (12, 14) and the opening (15). 15) in which a second electrode forming semiconductor film (16) is laminated, and by heating, all the impurity-containing interlayer films (1
Impurities in the first, second, and second electrode forming semiconductor films (11, 13, 16) are solid-phase diffused to the first and second electrode forming semiconductor films (11, 13, 16). , 13, 16) to reduce the resistance, and at least up to the one electrode forming semiconductor film (11) is patterned to remain in the cell region including the opening (15), and the remaining fin-shaped A step of using the first and second electrode forming semiconductor films (11, 13, 16) as a first electrode (18), and all the impurities above the insulating film (3, 7, 9) A step of removing the containing interlayer film (10, 12, 14), and the first and second electrode forming semiconductor films (11, 13) exposed by removing the impurity containing interlayer film (10, 12, 14). ,
16) a step of forming a capacitor dielectric film (19) along the surface of the capacitor, and a step of forming a second electrode (20) in contact with the surface of the capacitor dielectric film (19). A method for manufacturing a semiconductor device, comprising: 3. The impurity-containing interlayer film (10, 12, 14)
3. The method for manufacturing a semiconductor device according to claim 1, wherein is a phosphorous glass, an arsenic glass, or an antimony glass.