JPH05226184A - Noise filter - Google Patents

Noise filter

Info

Publication number
JPH05226184A
JPH05226184A JP6127492A JP6127492A JPH05226184A JP H05226184 A JPH05226184 A JP H05226184A JP 6127492 A JP6127492 A JP 6127492A JP 6127492 A JP6127492 A JP 6127492A JP H05226184 A JPH05226184 A JP H05226184A
Authority
JP
Japan
Prior art keywords
electrodes
resistor
electrode
porcelain
semiconductor porcelain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6127492A
Other languages
Japanese (ja)
Other versions
JP3099503B2 (en
Inventor
Kazuyoshi Nakamura
和敬 中村
Akiyoshi Nakayama
晃慶 中山
Yasunobu Yoneda
康信 米田
Yukio Sakabe
行雄 坂部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP04061274A priority Critical patent/JP3099503B2/en
Publication of JPH05226184A publication Critical patent/JPH05226184A/en
Application granted granted Critical
Publication of JP3099503B2 publication Critical patent/JP3099503B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To effectively prevent damage, erroneous operation of a semiconductor device, to reduce the number of components and a mounting cost, to avoid deterioration of life characteristics and to avoid a variation in a resistance value when glass is diffused. CONSTITUTION:End face electrodes 4 are formed on left and right end faces 3a, 3b of a semiconductor porcelain 3 having voltage nonlinear characteristics, and side face electrodes 5 are formed on the other both side faces 3c, 3d. A first inner electrode 6 is buried in the porcelain 3, and only its one edge 6a is connected to the one electrode 4. A second inner electrode 7 superposed with the electrode 6 through a ceramic layer 2 is buried in the porcelain 3, and its both edges 7a, 7b are connected to the electrodes 5. Further, a resistor 8 superposed with the electrode 6 through a ceramic layer 2 is buried in the porcelain 3, and lead electrodes 9 to be connected to the electrode 4 are formed on left and right outer edges 2a, 2b of the layer 2. Left and right edges 8a, 8b of the resistor 8 are connected to the electrodes 9 to constitute a noise filter 1. In addition, a glass film is formed on a surface part except the end face and side face electrodes.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、バリスタ特性,コンデ
ンサ特性,及び抵抗特性を兼ね備えた3端子型のノイズ
フィルタに関し、特に電圧抑制御能力を向上して半導体
デバイスの破壊,誤動作を確実に防止でき、かつ部品点
数,実装コストを低減できるとともに、寿命特性の悪化
を回避できるようにした構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a three-terminal type noise filter having both varistor characteristics, capacitor characteristics, and resistance characteristics, and in particular, voltage suppression control capability is improved to reliably prevent destruction and malfunction of semiconductor devices. The present invention relates to a structure capable of reducing the number of parts and mounting cost, and avoiding deterioration of life characteristics.

【0002】[0002]

【従来の技術】コンピュータ機器に採用されるIC,L
SIをはじめとする半導体デバイスにおいては、静電気
サージ等のトランジェントノイズの侵入によって破壊,
誤動作するのを防止することが重要な課題となってい
る。このようなトランジェントノイズの侵入から防御す
る方法として、従来、セットや基板のグランドの設定や
基板内の電子部品素子の配列を工夫したり,あるいはデ
ィスク型バリスタやLCフィルタを回路に付加すること
によりノイズを吸収するのが一般的である。なかでも上
記バリスタは、回路に加えることが比較的簡単であり、
しかも低電圧,低容量であることから他の方法に比べて
ノイズ吸収素子として適している。またノイズ吸収素子
としてバリスタを採用する場合、これのバリスタ電圧は
できるだけ回路電圧に近づける必要があることから、低
電圧化が要求される。
2. Description of the Related Art ICs and Ls used in computer equipment
In semiconductor devices such as SI, destruction due to intrusion of transient noise such as electrostatic surge,
Preventing malfunctions has become an important issue. As a method to prevent such intrusion of transient noise, conventionally, by setting the ground of the set or the board, arranging the electronic component elements in the board, or adding a disk type varistor or an LC filter to the circuit. It is common to absorb noise. Above all, the above varistor is relatively easy to add to the circuit,
Moreover, since it has a low voltage and a low capacity, it is more suitable as a noise absorbing element than other methods. When a varistor is used as the noise absorbing element, the varistor voltage of the varistor needs to be as close to the circuit voltage as possible, so that a low voltage is required.

【0003】また、近年、コンピュータ機器の小型化,
薄型化が進むなかで、上記バリスタにおいても小型化,
SMT(表面実装)化への対応が要請されている。しか
し、上記ディスク型バリスタではその構造からして小型
化,SMT化に対応できない。このようなディスク型バ
リスタに代わるものとして、従来、積層型バリスタが提
案されている(例えば、特公昭58-23921号公報参照) 。
In recent years, miniaturization of computer equipment,
As thinning advances, the varistor also becomes smaller,
It is required to support SMT (surface mounting). However, the above-mentioned disc type varistor cannot support downsizing and SMT due to its structure. As an alternative to the disc type varistor, a laminated type varistor has been conventionally proposed (see, for example, Japanese Patent Publication No. 58-23921).

【0004】[0004]

【発明が解決しようとする課題】しかしながら、上記従
来の積層型バリスタでは、小型化,SMT化には対応で
きるものの、電圧抑制能力は従来のディスク型バリスタ
とほとんど変わらないことから、ノイズの侵入から半導
体デバイスを保護しきれない場合があり、この点での向
上が要請されている。また、上記半導体デバイスの破壊
電圧はその種類によって異なるが、MOS−IC等では
40〜60V で破壊するものが多い。一方、上記積層型バリ
スタの電圧抑制能力はバリスタ電圧の2〜3倍であり、
このバリスタ電圧が低いほど比率は大きくなることか
ら、静電気等のインパルスでは抑制電圧はさらに高くな
り、その結果上記積層型バリスタ単独では保護できない
場合がある。
However, although the above-mentioned conventional laminated varistor can be made compact and SMT, its voltage suppression capability is almost the same as that of the conventional disk varistor, so that it is not susceptible to noise intrusion. In some cases, semiconductor devices cannot be completely protected, and improvement in this respect is required. In addition, although the breakdown voltage of the semiconductor device varies depending on its type, in a MOS-IC or the like,
Many are destroyed at 40-60V. On the other hand, the voltage suppressing ability of the above laminated varistor is 2 to 3 times the varistor voltage,
Since the lower the varistor voltage, the larger the ratio, the suppression voltage is further increased by impulses such as static electricity, and as a result, the laminated varistor alone may not be protected.

【0005】ここで、上記積層型バリスタに抵抗を付加
することによって、実力値以上の電圧抑制能力を得るこ
とが可能である。この場合、上記積層型バリスタに抵抗
素子を別途外付けすると、この素子が増える分だけコス
トが上昇するとともに、実装スペースが拡大するという
問題が生じる。また、上記積層型バリスタの表面に抵抗
膜を被覆形成することも考えられるが、このようにする
と外部からの機械的負荷により抵抗膜が損傷し易く、そ
の結果電気的特性が悪化し、寿命特性が低下するという
問題が生じる。
Here, by adding a resistance to the laminated varistor, it is possible to obtain a voltage suppression capability higher than the actual value. In this case, if a resistance element is externally attached to the laminated varistor, the cost increases and the mounting space increases due to the increase in the number of elements. It is also conceivable to form a resistance film on the surface of the laminated varistor. However, in this case, the resistance film is easily damaged by an external mechanical load, resulting in deterioration of electrical characteristics and life characteristics. Occurs.

【0006】本発明は、上記従来の状況に鑑みてなされ
たもので、電圧抑制能力を向上してノイズによる半導体
デバイスの破壊,誤動作を確実に防止でき、さらにはコ
ストの上昇や実装スペースの拡大を回避できるととも
に、寿命特性の悪化を回避できるノイズフィルタを提供
することを目的としている。
The present invention has been made in view of the above-mentioned conventional circumstances, and it is possible to improve the voltage suppressing ability to reliably prevent the semiconductor device from being damaged or malfunctioning due to noise, and further increase the cost and the mounting space. It is an object of the present invention to provide a noise filter capable of avoiding the above and avoiding deterioration of life characteristics.

【0007】[0007]

【課題を解決するための手段】そこで本発明は、電圧非
直線特性を有する半導体磁器の互いに対向する第1,第
2側面に第1,第2側面電極を形成するとともに、互い
に対向する第3,第4側面に第3,第4側面電極を形成
し、上記半導体磁器の内部に第1内部電極を埋設し、該
第1内部電極の一端縁を上記第1,第2側面電極の一方
に接続し、上記半導体磁器の内部にセラミック層を挟ん
で上記第1内部電極と重なり合う第2内部電極を埋設す
るとともに、該第2内部電極の両端縁を上記第3,第4
側面電極に接続し、さらに上記半導体磁器の内部にセラ
ミック層を挟んで上記第1内部電極と重なり合う抵抗体
を埋設し、該抵抗体の両端縁を導出電極を介して上記第
1,第2側面電極に接続したことを特徴とするノイズフ
ィルタである。
SUMMARY OF THE INVENTION Therefore, according to the present invention, the first and second side surface electrodes are formed on the first and second side surfaces of the semiconductor porcelain having the voltage non-linear characteristic, which face each other, and the third and third electrodes face each other. , Forming third and fourth side surface electrodes on the fourth side surface, burying the first internal electrode inside the semiconductor porcelain, and applying one end edge of the first internal electrode to one of the first and second side surface electrodes. A second internal electrode, which is connected to and overlaps with the first internal electrode with a ceramic layer sandwiched therebetween, is embedded inside the semiconductor porcelain, and both end edges of the second internal electrode are connected to the third and fourth internal electrodes.
A resistor which is connected to the side surface electrode and which overlaps the first internal electrode with a ceramic layer sandwiched therein is embedded in the semiconductor porcelain, and both end edges of the resistor are connected to the first and second side surfaces through lead electrodes. It is a noise filter characterized by being connected to electrodes.

【0008】ここで、上記半導体磁器の各電極を除く表
面部分にガラス膜を被覆形成するのが望ましい。これに
より耐湿性,及び耐酸化性を向上できるとともに、もれ
電流を低減でき、寿命特性を向上できるからである。
Here, it is desirable to form a glass film on the surface portion of the semiconductor ceramic except the electrodes. This is because moisture resistance and oxidation resistance can be improved, leakage current can be reduced, and life characteristics can be improved.

【0009】また、上記抵抗体を構成する材料として
は、Ruを主成分とするのが適当であり、特にRuO2
にPb2 Ru2 7 又はBi2 Ru2 7 のいずれかを
混合するのが望ましい。これにより抵抗値の制御が容易
にでき、またこれと合わせて抵抗体の長さ,面積,及び
積層数を適宜変えることによって所望の抵抗値に設定で
きるからである。また上記Pb2 Ru2 7 ,Bi2
2 7 の添加量は60wt%までにするのが望ましい。こ
れを越えると抵抗値にばらつきが生じるからである。さ
らに、上記半導体磁器を構成するセラミック材料として
は、焼成時の温度を考慮するとZnOを主成分としたも
のを採用するのが適当である。
Further, as a material forming the resistor, it is appropriate to use Ru as a main component, and particularly RuO 2
It is desirable to mix with either Pb 2 Ru 2 O 7 or Bi 2 Ru 2 O 7 . This is because the resistance value can be easily controlled, and in addition, the resistance value can be set to a desired resistance value by appropriately changing the length, the area, and the number of laminated layers of the resistor. Also, the above Pb 2 Ru 2 O 7 , Bi 2 R
The amount of u 2 O 7 added is preferably up to 60 wt%. This is because if it exceeds this value, the resistance value varies. Further, as the ceramic material forming the above-mentioned semiconductor porcelain, it is suitable to use a material containing ZnO as a main component in consideration of the temperature during firing.

【0010】[0010]

【作用】本発明に係るノイズフィルタによれば、半導体
磁器の第1,第2側面電極間に導出電極を介在させて抵
抗体を接続したので、第1,第2内部電極間で電圧非直
線特性を得ながら、上記抵抗体で該バリスタの実力値以
上の電圧抑制能力が得られることとなり、トランジェン
トノイズの侵入による半導体デバイスの破壊や誤動作を
確実に防止できる。また、上記抵抗体を半導体磁器の内
部に埋設したので、抵抗部品を別途外付けする場合のコ
ストの上昇,及び実装スペースの拡大を回避でき、さら
には半導体磁器の表面に抵抗膜を被覆形成する場合の、
外部からの機械的負荷による損傷を回避でき、寿命特性
を向上できる。さらに、本発明では、上記抵抗体を半導
体磁器内に封入し、該抵抗体を導出電極を介して端面の
第1,第2側面電極に接続したので、半導体磁器にガラ
ス膜を形成する場合に、該ガラスが抵抗体に拡散するの
を防止できる。その結果、抵抗値の変動を回避でき、ひ
いては設計どおりの抵抗値を得ることができる。
According to the noise filter of the present invention, since the resistor is connected between the first and second side electrodes of the semiconductor porcelain with the lead-out electrode interposed therebetween, the voltage nonlinearity between the first and second inner electrodes is increased. While obtaining the characteristics, the resistor can obtain the voltage suppressing ability which is equal to or more than the actual value of the varistor, so that the destruction or malfunction of the semiconductor device due to the intrusion of transient noise can be surely prevented. Further, since the resistor is embedded inside the semiconductor porcelain, it is possible to avoid an increase in cost and an increase in mounting space when a resistance component is externally attached, and further, to form a resistance film on the surface of the semiconductor porcelain. of the case,
Damage due to external mechanical load can be avoided and life characteristics can be improved. Furthermore, in the present invention, the resistor is enclosed in the semiconductor porcelain, and the resistor is connected to the first and second side surface electrodes on the end face via the lead-out electrode. Therefore, when the glass film is formed on the semiconductor porcelain. It is possible to prevent the glass from diffusing into the resistor. As a result, it is possible to avoid variations in resistance value, and it is possible to obtain the resistance value as designed.

【0011】[0011]

【実施例】以下、本発明の実施例を図について説明す
る。図1ないし図4は本発明の一実施例によるノイズフ
ィルタを説明するための図である。図において、1は本
実施例の電圧非直線特性,コンデンサ特性,及び抵抗特
性を兼ね備えた3端子型のノイズフィルタである。この
ノイズフィルタ1の半導体磁器3は、ZnOを主成分と
する複数のセラミック層2を積層し、この積層体を一体
焼結してなる直方体状のものである。この半導体磁器3
の左, 右端面(第1,第2側面)3a,3bにはAgか
らなる外部回路接続用の端面電極(第1,第2側面電
極)4,4が形成されており、上記半導体磁器3の前,
後側面(第3,第4側面)3c,3dの中央部には同じ
くAgからなる外部回路接続用の側面電極(第3,第4
側面電極)5,5が形成されている。
Embodiments of the present invention will be described below with reference to the drawings. 1 to 4 are views for explaining a noise filter according to an embodiment of the present invention. In the figure, reference numeral 1 is a three-terminal type noise filter having the voltage non-linear characteristic, the capacitor characteristic, and the resistance characteristic of this embodiment. The semiconductor porcelain 3 of the noise filter 1 has a rectangular parallelepiped shape obtained by laminating a plurality of ceramic layers 2 containing ZnO as a main component and integrally sintering the laminated body. This semiconductor porcelain 3
On the left and right end faces (first and second side faces) 3a and 3b, end face electrodes (first and second side face electrodes) 4 and 4 made of Ag for external circuit connection are formed. Before,
At the central portions of the rear side surfaces (third and fourth side surfaces) 3c and 3d, side surface electrodes (third and fourth surface electrodes) also made of Ag for connecting an external circuit are formed.
Lateral electrodes 5 and 5 are formed.

【0012】また、上記半導体磁器3の内部にはAg−
Pd合金からなる第1内部電極6が埋設されている。こ
の第1内部電極6の一端縁6aは半導体磁器3の左側端
面3aに露出して端面電極4に接続されており、他端縁
6bは半導体磁器3の右側端面3bの内方に位置して半
導体磁器3内に封入されている。
Inside the semiconductor porcelain 3, Ag-
The first internal electrode 6 made of Pd alloy is embedded. One end edge 6a of the first internal electrode 6 is exposed at the left end surface 3a of the semiconductor porcelain 3 and connected to the end surface electrode 4, and the other end edge 6b is located inside the right end surface 3b of the semiconductor porcelain 3. It is enclosed in the semiconductor porcelain 3.

【0013】さらに、上記半導体磁器3の内部には上記
セラミック層2を挟んで上記第1内部電極6と平行に重
なり合う第2内部電極7が埋設されている。この第2内
部電極7の両端縁7a,7bは半導体磁器3の前,後側
面3c,3dに露出して側面電極5,5に接続されてお
り、これにより上記第1,第2内部電極6,7で挟まれ
たセラミック部分が電圧非直線特性を発現するセラミッ
ク層2となっている。さらに、図示していないが、上記
半導体磁器3の左,右端面電極4,前,後側面電極5を
除く外表面にはガラス膜が被覆形成されている。
Further, inside the semiconductor porcelain 3, there is embedded a second internal electrode 7 which overlaps the first internal electrode 6 in parallel with the ceramic layer 2 interposed therebetween. Both end edges 7a, 7b of the second internal electrode 7 are exposed at the front and rear side surfaces 3c, 3d of the semiconductor porcelain 3 and connected to the side surface electrodes 5, 5, whereby the first and second internal electrodes 6 are formed. The ceramic portion sandwiched between the electrodes 7 and 7 is the ceramic layer 2 that exhibits a voltage non-linear characteristic. Further, although not shown, a glass film is formed on the outer surface of the semiconductor porcelain 3 excluding the left and right end surface electrodes 4 and the front and rear side surface electrodes 5.

【0014】そして、上記半導体磁器3の内部には、R
uO2 にPb2 Ru2 7 及びBi2 Ru2 7 を所定
量混合してなる抵抗体8が埋設されている。この抵抗体
8は1つのセラミック層2を挟んで上記第2内部電極7
と平行に重なり合うよう配置されている。またこの抵抗
体8の全ての端縁は端面3a,3b側面3c,3dの内
方に位置し、該半導磁気3内に封入されている。そして
この抵抗体8はこれの厚さ,幅を選定することにより所
定の抵抗値に設定されている。
Inside the semiconductor porcelain 3, R
A resistor 8 formed by mixing Pb 2 Ru 2 O 7 and Bi 2 Ru 2 O 7 in a predetermined amount in uO 2 is embedded. The resistor 8 has the second internal electrode 7 with one ceramic layer 2 interposed therebetween.
It is arranged so as to overlap in parallel with. All the edges of the resistor 8 are located inside the end faces 3a, 3b and the side faces 3c, 3d, and are enclosed in the semi-conductive magnet 3. The resistor 8 is set to a predetermined resistance value by selecting its thickness and width.

【0015】また、上記抵抗体8が形成されたセラミッ
ク層2の左, 右外縁部2a,2bには導出電極9が形成
されている。この導出電極9の一端は上記端面電極4に
接続されており、他端は上記抵抗体8の左, 右端縁8
a,8bが接続されている。これにより上記抵抗体8は
上記導出電極9を介して上記左,右端面電極4に接続さ
れている。
Further, lead electrodes 9 are formed on the left and right outer edge portions 2a and 2b of the ceramic layer 2 on which the resistor 8 is formed. One end of the lead-out electrode 9 is connected to the end face electrode 4, and the other end is the left and right end edges 8 of the resistor 8.
a and 8b are connected. As a result, the resistor 8 is connected to the left and right end face electrodes 4 via the lead electrode 9.

【0016】次に本実施例のノイズフィルタ1の一製造
方法について説明する。まず、純度99%以上のZnOを
主成分とし、これにBi2 3 ,CoCO3 ,MnO2
及びSb2 2 をそれぞれ98mol %,0.5mol %,0.5mol
%,0.5mol %,及び0.5 mol %の割合で秤量し、これに
純水を加えてボールミルで24時間混合してスラリーを形
成する。次にこのスラリーを濾過乾燥して造粒した後、
800 ℃の温度で2時間仮焼成する。
Next, a method of manufacturing the noise filter 1 of this embodiment will be described. First, ZnO having a purity of 99% or more is used as a main component, and Bi 2 O 3 , CoCO 3 , and MnO 2 are added to the main component.
And Sb 2 O 2 are 98mol%, 0.5mol%, 0.5mol
%, 0.5 mol%, and 0.5 mol% are weighed, pure water is added thereto, and they are mixed in a ball mill for 24 hours to form a slurry. Next, after filtering and drying this slurry and granulating,
Pre-baking is performed at a temperature of 800 ° C for 2 hours.

【0017】次に、上記仮焼成物をパルベライザーによ
り粗粉砕した後、これに純水を加えてボールミルで微粉
砕する。次いで、この微粉末を濾過乾燥させた後、有機
バインダーとともに溶媒中に分散させてスラリーを形成
する。この後、このスラリーを、ドクターブレード法に
より厚さ50μm のセラミックグリーンシートを形成し、
このグリーンシートを所定寸法の大きさに打ち抜いて複
数枚のセラミック層2を形成する。
Next, the calcined product is roughly pulverized by a pulverizer, pure water is added thereto, and then finely pulverized by a ball mill. Next, this fine powder is filtered and dried, and then dispersed in a solvent together with an organic binder to form a slurry. After this, this slurry was formed into a ceramic green sheet with a thickness of 50 μm by the doctor blade method,
This green sheet is punched into a predetermined size to form a plurality of ceramic layers 2.

【0018】次に、Ag−Pd(7:3)合金からなる
導電ペーストを上記セラミック層2の上面にスクリーン
印刷して第1内部電極6を形成する。この第1内部電極
6はこれの一端縁6aのみがセラミック層2の外縁に位
置し、他端縁6b及び残りの端縁はセラミック層2の内
方に位置するように形成する。また、別のセラミック層
2の上面に同じく導電ペーストを印刷して第2内部電極
7を形成する。この内部電極7はこれの両端縁7a,7
bがセラミック層2の長手方向両外縁に位置し、残りの
端縁がセラミック層2の内方に位置するように形成す
る。さらに、別のセラミック層2の上面の左, 右外縁2
a,2bに、同じく導電ペーストを印刷して導出電極9
を形成する。
Next, a conductive paste made of an Ag-Pd (7: 3) alloy is screen-printed on the upper surface of the ceramic layer 2 to form the first internal electrode 6. The first inner electrode 6 is formed so that only one end edge 6a thereof is located on the outer edge of the ceramic layer 2, and the other end edge 6b and the remaining end edge are located inside the ceramic layer 2. Further, a conductive paste is printed on the upper surface of another ceramic layer 2 to form the second internal electrode 7. This internal electrode 7 has both edges 7a, 7
b is located on both outer edges of the ceramic layer 2 in the longitudinal direction, and the remaining edges are located inside the ceramic layer 2. Furthermore, the left and right outer edges 2 of the upper surface of another ceramic layer 2
Similarly, a conductive paste is printed on a and 2b to form the lead electrode 9
To form.

【0019】次いで、RuO2 にPb2 Ru2 7 及び
Bi2 Ru2 7 を0〜60wt%混合し、これにワニスを
加えて抵抗ペーストを作成し、この抵抗ペーストを上記
導出電極9が形成されたセラミック層2の上面にスクリ
ーン印刷して抵抗体8を形成する。この抵抗体8は、こ
れの両端縁8a,8bが上記両導出電極9に少し重なる
ように形成する。
Then, RuO 2 is mixed with Pb 2 Ru 2 O 7 and Bi 2 Ru 2 O 7 in an amount of 0 to 60 wt%, and varnish is added to the mixture to prepare a resistance paste. The resistor 8 is formed by screen-printing on the upper surface of the formed ceramic layer 2. The resistor 8 is formed such that both end edges 8a and 8b of the resistor 8 slightly overlap the lead-out electrodes 9.

【0020】そして、図3に示すように、第1内部電極
6と第2内部電極7とがセラミック層2’を挟んで対向
するよう上記各セラミック層2を重ね、上記第1内部電
極6の上面にダミー用セラミック層2を介在させて抵抗
体8が形成されたセラミック層2を重ねるとともに、こ
れの上面,下面にダミー用セラミック層2を複数枚重ね
る。次に、これの積層方向に2t/cm2 の圧力を加えて圧
着し、積層体を形成する。
Then, as shown in FIG. 3, the respective ceramic layers 2 are stacked so that the first internal electrode 6 and the second internal electrode 7 face each other with the ceramic layer 2 ′ interposed therebetween. The ceramic layer 2 on which the resistor 8 is formed is stacked on the upper surface with the dummy ceramic layer 2 interposed therebetween, and a plurality of dummy ceramic layers 2 are stacked on the upper surface and the lower surface thereof. Then, a pressure of 2 t / cm 2 is applied in the stacking direction to press-bond the stack to form a stack.

【0021】次に、上記積層体を所定寸法にカットし、
これを900 ℃の温度で2時間焼成して半導体磁器3を得
る。次いで、上記半導体磁器3を磁器ポット内に収容す
るとともに、該ポット内にホウケイ酸亜鉛ガラスを添加
し、上記磁器ポットを回転させながら600 〜900 ℃の温
度で熱処理を施す。これにより上記半導体磁器3の外表
面部分にガラス膜を形成する。そして最後に、この半導
体磁器3の左, 右端面3a,3b及び前,後側面3c,
3dの中央部にAgペーストを塗布した後、800 ℃で10
分間焼き付けて端面電極4及び側面電極5を形成する。
Next, the above laminated body is cut into a predetermined size,
This is fired at a temperature of 900 ° C. for 2 hours to obtain a semiconductor ceramic 3. Next, the semiconductor porcelain 3 is housed in a porcelain pot, zinc borosilicate glass is added to the pot, and heat treatment is performed at a temperature of 600 to 900 ° C. while rotating the porcelain pot. Thereby, a glass film is formed on the outer surface portion of the semiconductor porcelain 3. And finally, the left and right end faces 3a and 3b of the semiconductor porcelain 3 and the front and rear side faces 3c,
After applying Ag paste to the center of 3d,
It is baked for a minute to form the end face electrode 4 and the side face electrode 5.

【0022】本実施例のノイズフィルタ1は、図4の等
価回路図に示すように、一方の端面電極4と側面電極5
との間に電源を接続し、他方の端面電極4と側面電極5
との間に半導体デバイスAを接続する。これにより半導
体デバイスAに異常電圧が加わるのを防止するととも
に、バリスタ部Zの電圧抑制能力を越える過電圧エネル
ギーを抵抗体8でもって吸収することとなる。
The noise filter 1 of this embodiment has one end face electrode 4 and one side face electrode 5 as shown in the equivalent circuit diagram of FIG.
A power source is connected between the other end face electrode 4 and the side face electrode 5
The semiconductor device A is connected between and. As a result, an abnormal voltage is prevented from being applied to the semiconductor device A, and the overvoltage energy exceeding the voltage suppression capability of the varistor portion Z is absorbed by the resistor 8.

【0023】このように本実施例によれば、半導体磁器
の端面電極4間に導出電極9を介して抵抗体8を付加す
るとともに、該抵抗体8を半導体磁器3内に埋設したの
で、半導体デバイスAの破壊電圧より大きいノイズが侵
入しても抵抗体8で抑制することができ、その結果IC
やLSI等の半導体デバイスの破壊や誤動作を確実に回
避できる。また、上記抵抗体8を半導体磁器3に内蔵し
た構造であるから、抵抗部品を別途外付けする場合に比
べて部品コストを低減できるとともに、実装スペースを
縮小でき、ひいてはコンピュータ機器の小型化に対応で
きる。さらに、半導体磁器の表面に抵抗膜を被覆形成す
る場合に比べて外力による損傷を回避でき、寿命特性を
向上できる。
As described above, according to this embodiment, since the resistor 8 is added between the end face electrodes 4 of the semiconductor porcelain via the lead-out electrode 9, and the resistor 8 is embedded in the semiconductor porcelain 3, the semiconductor Even if noise larger than the breakdown voltage of the device A enters, it can be suppressed by the resistor 8, and as a result, the IC
It is possible to surely avoid breakage and malfunction of semiconductor devices such as LSIs and LSIs. Further, since the resistor 8 is built in the semiconductor porcelain 3, the component cost can be reduced and the mounting space can be reduced as compared with the case where the resistor component is externally attached, which corresponds to downsizing of computer equipment. it can. Further, compared with the case where a resistance film is formed on the surface of the semiconductor porcelain, damage due to an external force can be avoided and the life characteristics can be improved.

【0024】さらに、本実施例では、上記半導体磁器3
内に封入した抵抗体8を導出電極9を介して端面電極4
に接続したので、半導体磁器3にガラス膜を形成する際
に、該ガラスが抵抗体8に拡散するのを防止でき、抵抗
値の変動を回避できる。
Further, in this embodiment, the semiconductor porcelain 3 is used.
The resistor 8 enclosed in the inside is connected to the end face electrode 4 via the lead-out electrode 9.
Since it is connected to, when the glass film is formed on the semiconductor porcelain 3, the glass can be prevented from diffusing into the resistor 8 and the fluctuation of the resistance value can be avoided.

【0025】[0025]

【表1】 [Table 1]

【0026】表1は、本実施例のノイズフィルタ1の効
果を確認するために行った試験結果を説明するためのも
のである。この試験は、上述した製造方法により、ガラ
ス膜を被覆していないサンプルNo. 1と、ガラス膜を被
覆したサンプルNo. 2を作成し、この両サンプルの抵抗
値(Ω),バリスタ電圧(V1mA ),非直線係数
(α),及び静電容量値(pF)を測定するとともに、
それぞれのばらつきを調べた。また、ばらつきは3CV
=σ×3/平均×100 %で求めた(σは標準偏差を示
す)。
Table 1 is for explaining the result of the test conducted to confirm the effect of the noise filter 1 of this embodiment. In this test, a sample No. 1 not covered with a glass film and a sample No. 2 covered with a glass film were prepared by the above-mentioned manufacturing method, and the resistance value (Ω) and varistor voltage (V) of both samples were prepared. 1mA ), non-linear coefficient (α), and capacitance value (pF),
Each variation was examined. Also, the variation is 3 CV
= Σ × 3 / average × 100% (σ indicates standard deviation).

【0027】表1からも明らかなように、本実施例によ
れば、両サンプル No.1,2ともバリスタ電圧,非直線
係数,静電容量のいずれも満足できる値が得られてい
る。また、抵抗値は232 、235 Ωが得られており、しか
もばらつきは4.3 、4.7 %と小さい。この結果、半導体
磁器内に抵抗体を埋設して一体焼結することによって、
バリスタ特性及び誘電率の変化がなく、しかも抵抗のば
らつきが小さく、かつ結合安定性の良いノイズフィルタ
が得られることがわかる。また、半導体磁器にガラス膜
を被覆形成したサンプルNo. 2の場合、湿度,及び酸化
に対する耐環境性が向上し、寿命特性の向上がみられ
た。ちなみに、上記各サンプルの抵抗体にノイズシミュ
レーションを用いて2KV・200nSEC の方形波を印加した
ところ、いずれも抵抗体の変化は2%未満であった。
As is clear from Table 1, according to the present embodiment, both Sample Nos. 1 and 2 have satisfactory values for varistor voltage, nonlinear coefficient, and capacitance. In addition, resistance values of 232 and 235 Ω were obtained, and the variation was as small as 4.3 and 4.7%. As a result, by embedding the resistor in the semiconductor porcelain and sintering it integrally,
It can be seen that it is possible to obtain a noise filter which does not change in varistor characteristics and permittivity, has small resistance variation, and has good coupling stability. Further, in the case of Sample No. 2 in which the semiconductor porcelain was coated with the glass film, the environment resistance against humidity and oxidation was improved, and the life characteristics were improved. By the way, when a square wave of 2 KV · 200 nSEC was applied to the resistors of the above samples using noise simulation, the change in the resistors was less than 2% in all cases.

【0028】図5は、上記サンプルを採用して、図4に
示すような回路を構成し、これに高電圧パルスを印加し
たときのパルス波形を示す。同図からも明らかなよう
に、本実施例サンプルでは40V 程度となっており、従来
バリスタの略1/5 に低減できている。この点からも抵抗
体を内蔵したものは電圧抑制能力が高く半導体デバイス
の保護に有効であることがわかる。
FIG. 5 shows a pulse waveform when a circuit as shown in FIG. 4 is constructed by using the above sample and a high voltage pulse is applied thereto. As is clear from the figure, the sample of this example has a voltage of about 40 V, which is about 1/5 of that of the conventional varistor. From this point as well, it can be seen that the one having the built-in resistor has a high voltage suppressing ability and is effective in protecting the semiconductor device.

【0029】図6は、上記サンプルの周波数特性を示す
図であり、この図からも明らかなように、優れた周波数
特性が得られており、内部電極による浮遊容量の発生が
少ないことがわかる。
FIG. 6 is a diagram showing the frequency characteristics of the above sample. As is clear from this figure, excellent frequency characteristics are obtained, and it can be seen that the stray capacitance generated by the internal electrodes is small.

【0030】[0030]

【発明の効果】以上のように本発明に係るノイズフィル
タによれば、半導体磁器の内部に第1内部電極を埋設す
るとともに、セラミック層を挟んで重なり合う第2内部
電極を埋設し、上記半導体磁器の内部に抵抗体を埋設
し、該抵抗体の両端縁をセラミック層の外縁に形成され
た導出電極を介して端面電極(第1,第2側面電極)に
接続したので、電圧抑制能力を向上して半導体デバイス
の破壊,誤動作を確実に防止でき、また部品点数,実装
コストを低減できるとともに、寿命特性の悪化を回避で
きる効果があるとともに、ガラスを拡散させる際の抵抗
値の変動を回避でき、設計どおりの抵抗値が得られる効
果がある。
As described above, according to the noise filter of the present invention, the first internal electrode is embedded inside the semiconductor porcelain, and the second internal electrode that overlaps with the ceramic layer is embedded. Since a resistor is embedded inside the resistor and both end edges of the resistor are connected to the end face electrodes (first and second side face electrodes) through the lead-out electrodes formed on the outer edge of the ceramic layer, the voltage suppressing ability is improved. As a result, it is possible to reliably prevent breakage and malfunction of the semiconductor device, reduce the number of parts and mounting cost, and avoid the deterioration of the life characteristics. Also, it is possible to avoid the fluctuation of the resistance value when diffusing the glass. There is an effect that the resistance value as designed can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】請求項1の発明の一実施例によるノイズフィル
タを説明するための断面図である。
FIG. 1 is a sectional view for explaining a noise filter according to an embodiment of the present invention.

【図2】上記実施例のノイズフィルタを示す斜視図であ
る。
FIG. 2 is a perspective view showing a noise filter of the above embodiment.

【図3】上記実施例のノイズフィルタの製造方法を示す
分解斜視図である。
FIG. 3 is an exploded perspective view showing the method of manufacturing the noise filter of the above embodiment.

【図4】上記実施例のノイズフィルタの等価回路図であ
る。
FIG. 4 is an equivalent circuit diagram of the noise filter of the above embodiment.

【図5】上記実施例のノイズフィルタの効果を示す特性
図である。
FIG. 5 is a characteristic diagram showing the effect of the noise filter of the above-described embodiment.

【図6】上記実施例のノイズフィルタの効果を示す特性
図である。
FIG. 6 is a characteristic diagram showing the effect of the noise filter of the above-described embodiment.

【符号の説明】[Explanation of symbols]

1 ノイズフィルタ 2 セラミック層 3 半導体磁器 3a,3b 左, 右端面(第1,第2側面) 3c,3d 前,後側面(第2,第3側面) 4 端面電極(第1,第2側面電極) 5 側面電極(第3,第4側面電極) 6 第1内部電極 6a 一端縁 7 第2内部電極 7a,7b 両端縁 8 抵抗体 8a,8b 両端縁 9 導出電極 1 noise filter 2 ceramic layer 3 semiconductor porcelain 3a, 3b left and right end faces (first and second side faces) 3c and 3d front and rear side faces (second and third side faces) 4 end face electrodes (first and second side face electrodes) ) 5 side surface electrodes (third and fourth side surface electrodes) 6 first inner electrode 6a one end edge 7 second inner electrodes 7a, 7b both end edges 8 resistors 8a, 8b both end edges 9 lead electrode

───────────────────────────────────────────────────── フロントページの続き (72)発明者 坂部 行雄 京都府長岡京市天神2丁目26番10号 株式 会社村田製作所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yukio Sakabe 2 26-10 Tenjin Tenjin, Nagaokakyo-shi, Kyoto Murata Manufacturing Co., Ltd.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 電圧非直線特性を有する半導体磁器の互
いに対向する第1,第2側面に第1,第2側面電極を形
成するとともに、互いに対向する第3,第4側面に第
3,第4側面電極を形成し、上記半導体磁器の内部に第
1内部電極を埋設し、該第1内部電極の一端縁を上記第
1,第2側面電極の一方に接続し、上記半導体磁器の内
部にセラミック層を挟んで上記第1内部電極と重なり合
う第2内部電極を埋設するとともに、該第2内部電極の
両端縁を上記第3,第4側面電極に接続し、さらに上記
半導体磁器の内部にセラミック層を挟んで上記第1内部
電極と重なり合う抵抗体を埋設し、該抵抗体の両端縁を
導出電極を介して上記第1,第2側面電極に接続したこ
とを特徴とするノイズフィルタ。
1. A semiconductor porcelain having a voltage non-linear characteristic has first and second side electrodes formed on first and second side surfaces facing each other, and third and fourth side surfaces facing each other. 4 side surface electrodes are formed, a first internal electrode is embedded inside the semiconductor porcelain, one end edge of the first internal electrode is connected to one of the first and second side surface electrodes, and inside the semiconductor porcelain. A second internal electrode that overlaps the first internal electrode is embedded with a ceramic layer sandwiched in between, and both end edges of the second internal electrode are connected to the third and fourth side surface electrodes, and the ceramic is provided inside the semiconductor porcelain. A noise filter in which a resistor that overlaps the first internal electrode is embedded with a layer sandwiched in between, and both ends of the resistor are connected to the first and second side electrodes through lead electrodes.
【請求項2】 請求項1において、上記半導体磁器の第
1〜第4側面電極を除く表面部分をガラス膜で覆ったこ
とを特徴とするノイズフィルタ。
2. The noise filter according to claim 1, wherein a surface portion of the semiconductor porcelain except for the first to fourth side electrodes is covered with a glass film.
JP04061274A 1992-02-14 1992-02-14 Noise filter Expired - Lifetime JP3099503B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP04061274A JP3099503B2 (en) 1992-02-14 1992-02-14 Noise filter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP04061274A JP3099503B2 (en) 1992-02-14 1992-02-14 Noise filter

Publications (2)

Publication Number Publication Date
JPH05226184A true JPH05226184A (en) 1993-09-03
JP3099503B2 JP3099503B2 (en) 2000-10-16

Family

ID=13166472

Family Applications (1)

Application Number Title Priority Date Filing Date
JP04061274A Expired - Lifetime JP3099503B2 (en) 1992-02-14 1992-02-14 Noise filter

Country Status (1)

Country Link
JP (1) JP3099503B2 (en)

Also Published As

Publication number Publication date
JP3099503B2 (en) 2000-10-16

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