JPH0522544A - Image processor - Google Patents

Abstract

PURPOSE:To enable printing with excellent multilevel expression by any type of printing output device by deciding the output pulse width and the output position for printing according to the recording dot printing characteristics of the printing output device. CONSTITUTION:A buffer 61 stores noted picture element data and before and after consecutive three pixel data, the decision data according to the recording dot printing characteristics are written in a decision device 64 by means of a CPU. The device 64 designates an address by pixel data from a buffer 61, outputting the required decision data. A selector 66 outputs data where the output pulse width and the output position are formed as printing data for binarized noted picture element data according to the decision data from the device 64. Thus, the printing with excellent multilevel expression can be performed even by various kinds of printing output devices.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing device used in, for example, a laser printer.

[0002]

2. Description of the Related Art For example, a facsimile apparatus is designed to receive image data of a document read by an image sensor or the like by a transmission partner, decode the image data, and print it out.

There are many print output means for facsimiles, and their output characteristics are all different. In normal facsimile communication, the print output device on the receiving side cannot be specified at the time of transmission. Therefore, conventionally, the data sent from the sending side was directly printed out.

[0004]

However, when a laser printer utilizing an electrophotographic system is used as a print output device in such a case where the received data is printed out as it is, an output image, particularly a pseudo intermediate image is output. There is a problem that the toned image is remarkably black and the gradation expression is largely lost. That is, in the case of a laser printer, dots actually printed with respect to theoretical pixels are circular pixels having an area larger than that of theoretical pixels, which causes blackening.

Therefore, according to the present invention, when an image is printed out by using a print output device using an electrophotographic system such as a laser printer, an output pulse for printing according to the recording dot print characteristics of the print output device. An object of the present invention is to provide an image processing apparatus capable of performing image processing capable of printing with excellent gradation expression for any print output apparatus by determining the width and the output position. Another object of the present invention is to provide an image processing apparatus capable of determining an appropriate output pulse width and output position according to print density.

[0006]

The invention according to claim 1 is
Storage means for storing the binarized pixel data of interest and a plurality of binarized pixel data adjacent to the binarized pixel data of interest;
A determination unit that is addressed by a plurality of binarized pixel data including the binarized target pixel data extracted from the storage unit, selects and outputs the determination data, and a binarized target pixel according to the print dot printing characteristics. Judgment data writing means for writing a plurality of judgment data for judging an output pulse width and an output position of a target pixel from a plurality of binarized pixel data including data, and a reference for determining the output pulse width and the output position A timing generation circuit for generating a timing signal for generating the following, and data for which an output pulse width and an output position are determined according to the timing signal from the timing generation circuit and the determination data from the determination means are binarized. It is provided with an output means for outputting as use data.

According to a second aspect of the invention, storage means for storing the binarized pixel data of interest and a plurality of binarized pixel data adjacent to the binarized pixel data of interest, and a density selection switch for selecting the print density. And a judgment means for selecting and outputting judgment data addressed by a plurality of binarized pixel data including the binarized pixel data of interest extracted from the storage means, and recording dot printing by the density selection operation of the density selection switch. Judgment data writing means for writing to the judgment means a plurality of pieces of judgment data for determining the output pulse width and output position of the pixel of interest from the plurality of binarized pixel data including the binarized pixel data of interest in accordance with the characteristics and density. And a timing generation circuit for generating a timing signal serving as a reference for determining an output pulse width and an output position, and a timing signal from the timing generation circuit. It is provided with a output means for outputting the data output pulse width and the output position is determined in accordance with the determination data from the constant means as printing data of the binarized attention pixel data.

[0008]

According to the first aspect of the present invention, the output pulse width and the output of the target pixel are output from the plurality of binarized pixel data including the binarized target pixel data in advance according to the recording dot printing characteristics to the determination unit. Write a plurality of judgment data for determining the position. In this state, when the storage unit stores the binarized pixel data of interest and a plurality of binarized pixel data adjacent to the binarized pixel data of interest, the storage unit stores a plurality of binarized pixel data of interest. The binarized pixel data is extracted, the address of the determination means is specified by the extracted data, and the determination data is selectively output. Then, the output pulse width and the output position are determined according to the timing signal from the timing generation circuit and the determination data from the determination means.
Then, the output pulse width and the output position are determined, and the data is output as the printing data of the binarized target pixel data.

In the present invention corresponding to claim 2, the target pixel is selected from a plurality of binarized pixel data including the binarized target pixel data according to the recording dot printing characteristics and the density by the density selection operation of the density selection switch. A plurality of determination data for determining the output pulse width and the output position are written in the determination means.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the overall structure.
Is a CPU (central processing unit) that constitutes the main body of the control unit, 2 is an image RAM (random access memory) that expands and stores the image data for printing and recording in a dot pattern, and 3 is a host computer that is externally connected An interface 4 for transmitting and receiving data to and from the controller 4, an I / O port for controlling input / output of signals to and from the operation unit 5, and a gate array 6 for outputting printing data to a laser printer 7 as a printing device. CPU 1 and image RAM
2, the interface 3, the I / O port 4, and the gate array 6 are connected via a bus line 8.

When the image data is input from the host computer to the interface 3, the CPU 1 temporarily stores the image data in the image RAM 2, then develops it into a dot pattern, and stores it again in the image RAM 2.

As shown in FIG. 2, the operation section 5 has a print start / stop switch 5 for instructing start and stop of printing.
a, a reset switch 5b, a density selection switch 5c for selecting printing density from three levels of "dark", "normal", and "light",
Lamps 5d, 5e, 5f are provided to display the density selection state of the density selection switch 5c.

As shown in FIG. 3, the gate array 6 includes a buffer 61 as a storage means, a RAM address changeover switch 62, a RAM data changeover switch 63, a determination device 64 as a determination means, a timing generation circuit 65, and
It is composed of a selector 66 as an output means.

The buffer 61, as shown in FIG.
It is composed of a series circuit of three D-type flip-flops 61a, 61b, 61c, and has pixel data P (-
1), P (0) and P (1) are stored, and pixel data is externally fetched and shifted in synchronization with the clock VCLK from the timing generation circuit 65. The pixel data P (-1), P (0) and P (1) stored in the flip-flops 61a, 61b and 61c are output respectively. The pixel data P (0) is the binarized target pixel data, the pixel data P (-1) is the previous binarized pixel data, and the pixel data P (1) is the next binarized pixel data. Is.

The judging device 64, as shown in FIG.
8 address x 4 bit RA of 3 address buses RA0, RA1, RA2 and 4 data buses RD0, RD1, RD2, RD3
It is composed of M. This RAM64 enable signal
/ RE is always at the low level, and the RAM 64 is in the operation mode. A CPU write signal is input to the write terminal / RW of the RAM 64.

The RAM address changeover switch 62 is
As shown in FIG. 6, six gate circuits 62a to 62f and 1 are provided.
The inversion circuit 62g is provided, and the pixel data P (-1), P (0) and P (1) from the buffer 61 are supplied to the gate circuit 62a.
To 62c, and CPU address buses A0,
A1 and A2 are input to the gate circuits 62d to 62f, respectively. Then, the CPU data access mode signal from the CPU 1 is input to the gates of the gate circuits 62a to 62c and also input to the gates of the gate circuits 62d to 62f via the inverting circuit 62g.

The switch 62 sends the outputs of the gate circuits 62a to 62c to the address buses RA0, RA1 and RA2 of the judging device 64 when the mode signal is at a low level, and the gate circuits 62d to 62 when it is at a high level.
The output of f is applied to the address buses RA0 and RA1 of the judging device 64.
, RA2. Therefore, the CP
When U1 accesses the RAM of the determination device 64, the CPU data access mode signal is set to the high level.

The RAM data changeover switch 63 comprises eight gate circuits 63a to 63h and one inversion circuit 63i as shown in FIG. Data is transferred to the data H0, H1, H2, H3 via the gate circuits 63a-63d.
And the data D0, D from the CPU 1
The data buses RD0, RD1, RD2, RD of the judging device 64 are connected to 1, D2, D3 via the gate circuits 63e-63h.
It is designed to send to 3. Then, the CPU data access mode signal from the CPU 1 is input to the gates of the gate circuits 63a to 63d, and the inverting circuit 63 is used.
It is input to the gates of the gate circuits 63e to 63h via i.

When the mode signal is low level, the switch 63 receives data H0 from the data buses RD0, RD1, RD2 and RD3 via the gate circuits 63a to 63d.
, H1, H2, H3, and when it is at a high level, the data D0, D1, D2, D3 from the CPU 1 is sent.
Is sent to the data buses RD0, RD1, RD2 and RD3 of the judging device 64 through the gate circuits 63e to 63h.

The timing generating circuit 65 includes one D-type flip-flop 65a and four 2 flip-flops 65a as shown in FIG.
The AND-type AND gate circuits 65b to 65e are provided, and the system clock SCLK is input to the clock input terminal of the flip-flop 65a and to one input terminal of each of the AND gate circuits 65b to 65e. Note that one of the input terminals of the AND gate circuits 65c and 65e is an inverting input terminal.

The / Q output terminal of the flip-flop 65a is connected to the D input terminal, and the output of the Q output terminal is clocked.
The AND gate circuit 65 outputs the signal as VCLK.
It is input to the other input terminal of b to 65e. The other input terminals of the AND gate circuits 65d and 65e are inverting input terminals. The timing signals T0, T1, T2 from the AND gate circuits 65b to 65e,
Outputs T3.

That is, the relationship between the system clock SCLK input in the timing generation circuit 65, the output clock VCLK and the timing signals T0 to T3 is shown in FIG.

The selector 66, as shown in FIG.
It is composed of four 2-input AND gate circuits 66a to 66d and one 4-input OR gate circuit 66e, and one of the input terminals of each AND gate circuit 66a to 66d has a timing signal T0 ... T3
, And the data H0 to H3 from the RAM data changeover switch 63 are input to the other input terminals. And each of the AND gate circuits 66a-6
The output of 6d is output to the laser printer 7 via the OR gate circuit 66e as printing data of the binarized pixel data of interest.

In the embodiment having such a configuration, when the concentration selection switch 5c is operated by the operation unit 5, the CPU 1
Eight RAM data (HEX) shown in Table 1 are recorded in the RAM of the judging device 64 of the gate array 6 according to each selected density, and the output pulse width and output position of the pixel of interest are determined according to the recording dot printing characteristics and density. Write as judgment data for
(Judgment data writing means)

At this time, the CPU data access mode signal is set to the high level for writing. For example, when the density of a normal pixel is selected, "0,0,6,3,0,0, C,
RAM data (HEX) of "F" is the CPU address bus A0,
Based on the data of A1 and A2, it is written in a predetermined address of the RAM of the judging device 64.

[0027]

[Table 1]

When image data is received from the host computer in this state, the data is developed into a dot pattern and stored in the image RAM 2. Then, the pixel data developed in the dot pattern from the image RAM 2 is sequentially sent to the gate array 6.

The gate array 6 sequentially stores the input pixel data in the buffer 61. Then, the buffer 61 outputs the binarized pixel data of interest P (0) and the binarized pixel data P (-1) and P (1) before and after it, and supplies them to the RAM address changeover switch 62. Now, since the CPU data access mode signal supplied from the CPU 1 to the RAM address changeover switch 62 is at the low level, the RAM address changeover switch 62 outputs the pixel data P (-1), P (0), P
(1) is sent to the address buses RA0, RA1, RA2 of the determination device 64.

Thus, the pixel data P (-1), P (0), P
Desired determination data is read from the determination device 64 using (1) as an addressing signal. For example, pixel data P (-1),
If P (0) and P (1) are "1, 1, 0", the determination data "3 = 1100 (HEX)" is read from the determination device 64 according to Table 1.

The read judgment data is supplied to the selector 66 as the data H0 to H3 via the gate circuits 63a to 63d of the RAM data changeover switch 63.
That is, in the above example, H0 = 1, H1 = 1, H2 = 0, H
3 = 0. On the other hand, the selector 66 receives the timing signals T0 to T3 from the timing generation circuit 65. Then, in the selector 66, the AND gates 66a, 6
Only 6b turns on the gate and timing signals T0, T1
Only the selector 66 will pass.

In this way, the first half of the four divided pulse widths, that is, the pulse whose pulse width is ½ of the whole and biased toward the first half, is output to the laser printer 7 as the printing data for the binarized pixel of interest. Will be done. This is because the pixel before the binarization target pixel is "1" and the pixel after it is "0", so that the dot diameter is reduced and the pixel is moved to the black pixel before and the white pixel after Area is secured and the print image is prevented from being crushed.

When the pixel data P (-1), P (0), P (1) are "0, 1, 1", the determination data "C = 0011 (HEX)" is output from the determination device 64 according to Table 1. Read out. At this time, the selector 66 has AND gates 66c and 66d.
Only the gate is turned on, and only the timing signals T2 and T3 pass through the selector 66.

In this way, the second half of the pulse width divided into four, that is, the pulse whose pulse width is 1/2 of the whole and biased to the latter half is output to the laser printer 7 as the printing data of the binarized pixel of interest. Will be done. This is because the pixel after the binarized pixel of interest is "1" and the previous pixel is "0", and the diameter of the dot is reduced and the pixel of the previous white pixel Area is secured and the print image is prevented from being crushed.

In this way, printing of normal density is performed. Therefore, if the determination data for printing with a normal density is set according to the recording dot printing characteristics of the laser printer 7 and written in the determining device 64, the recording dot printing characteristics of the laser printer 7 will be met. The normal darkness printing is performed, and good printing can be performed. Therefore, even if the laser printer 7 to be used is different, printing can be performed accordingly, and therefore, whichever laser printer is used, printing with excellent gradation expression can be performed.

When relatively dark printing is performed, a dark image is selected by the density selection switch 5c. At this time, according to Table 1, the RAM data (HEX) of "0,0, F, F, 0,0, F, F" is written in the RAM of the determination device 64.

At this time, the pixel data P (-1), P (0),
If P (1) is "1, 1, 0", the determination data "F = 1111 (HEX)" is read from the determination device 64. At this time, in the selector 66, all the AND gates 66a to 66d are turned on, and the timing signals T0 to T3 pass through the selector 66.

In this way, a pulse having the same pulse width as the pulse width in the non-divided state is output to the laser printer 7 as the printing data of the binarized target pixel. Therefore, the printing at this time is printing with high density.

When relatively light printing is performed, a light image is selected by the density selection switch 5c. At this time, according to Table 1, the RAM data (HEX) of "0, 0, 6, 1, 0, 0, 8, 6" is written in the RAM of the determination device 64.

At this time, the pixel data P (-1), P (0),
If P (1) is "1, 1, 0", the determination data "1 = 1000 (HEX)" is read from the determination device 64. At this time, in the selector 66, only the AND gate 66a is turned on, and only the timing signal T0 passes through the selector 66.

In this way, the first half of the four divided pulse widths, that is, the pulse whose pulse width is ¼ of the whole and which is biased toward the first half, is output to the laser printer 7 as the data for printing the binarized target pixel. Will be done. Therefore, the printing at this time is printing with light density.

As described above, the print density can be selected, and printing can be performed with various densities based on the determination data set according to the print density. Also in this case, if the determination data corresponding to various densities are set according to the recording dot printing characteristics of the laser printer 7, various densities can be printed according to the laser printer 7 used.

Although a laser printer is used as the printing device in the above embodiment, the present invention is not limited to this. The point is that it can be applied to a printing output device using an electrophotographic method. It is a thing. Further, in the above-described embodiment, the example in which the printing density is set to three steps has been described, but it goes without saying that it is not necessarily limited to this.

[0044]

As described above in detail, according to the present invention, when an image is printed out by using a print output device using an electrophotographic system such as a laser printer, the recording dot printing characteristics of the print output device. By determining the output pulse width and output position for printing in accordance with the above, it is possible to perform image processing capable of printing with excellent gradation expression for any print output device. Can be provided. Further, it is possible to provide an image processing apparatus capable of determining an appropriate output pulse width and output position according to print density.

[Brief description of drawings]

FIG. 1 is an overall block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of an operation unit in the embodiment.

FIG. 3 is a block diagram showing a configuration of a gate array in the embodiment.

FIG. 4 is a circuit diagram showing a configuration of a buffer in FIG.

5 is a circuit diagram showing a configuration of a determination device in FIG.

6 is a circuit diagram showing a configuration of a RAM address changeover switch in FIG.

7 is a circuit diagram showing a configuration of a RAM data changeover switch shown in FIG.

FIG. 8 is a circuit diagram showing a configuration of a selector shown in FIG.

9 is a circuit diagram showing a configuration of a timing generation circuit in FIG.

10 is a diagram showing the signal timing of each part of the timing generation circuit in FIG.

[Explanation of symbols]

1 ... CPU (judgment data writing means), 6 ... Gate array, 61 ... Buffer (storage means), 64 ... Judgment device (judgment means), 65 ... Timing generation circuit, 66 ... Selector (output means).

Claims (2)

[Claims] 1. Storage means for storing binarized pixel data of interest and a plurality of binarized pixel data adjacent to the binarized pixel data of interest, and binarized pixel data of interest extracted from this storage means Determination means which is addressed by a plurality of binary pixel data including and selects and outputs the determination data;
Determination data for writing to the determination means a plurality of determination data for determining an output pulse width and an output position of a pixel of interest from a plurality of binarized pixel data including binarized pixel data of interest according to recording dot printing characteristics. Writing means, a timing generation circuit for generating a timing signal serving as a reference for determining an output pulse width and an output position, and an output pulse width and an output position according to the timing signal from the timing generation circuit and the determination data from the determination means. An image processing apparatus, comprising: an output unit that outputs the determined data as print data for binarized pixel data of interest. 2. A storage unit for storing the binarized pixel data of interest and a plurality of binarized pixel data adjacent to the binarized pixel data of interest, a density selection switch for selecting a print density, and the storage unit. Judgment means for selecting and outputting judgment data that is addressed by a plurality of binarized pixel data including the extracted binarized pixel data of interest, and recording dot printing characteristics and densities by the density selection operation of the density selection switch. Accordingly, a determination data writing unit that writes a plurality of determination data for determining the output pulse width and the output position of the target pixel from the plurality of binarized pixel data including the binarized target pixel data, and the output A timing generation circuit for generating a timing signal serving as a reference for determining a pulse width and an output position, a timing signal from the timing generation circuit, and the determination hand. An image processing apparatus, comprising: an output unit that outputs data in which an output pulse width and an output position are determined according to determination data from a stage as print data for binarized target pixel data.