JPH02155673A - Image processor - Google Patents

Abstract

PURPOSE:To enable pixel signals to be processed at low cost by providing a storage means with such a construction that pixel signals for a plurality of lines can be stored at each bit therein, and reading the plurality of pixel signal corresponding to the plurality of lines from each bit. CONSTITUTION:An image signal VDO1 inputted sequentially is inputted into a bit 0 in a memory 65 through a 3-state latch 64, and an address counter 66 is incremented by the leading edge of an image clock signal VCLK2 to enter a reading mode. A discriminating circuit 20 decides whether a pixel in question is a pixel to be provided with a dot and also a size into which the dot is to be reproduced, based on data corresponding to the pixel in question and the surrounding pixel. A PWM circuit 23 outputs a pulse width modulation signal to a laser driver 25, based on signals 21, 22 inputted from the discriminating circuit 20. When the signal 21 designates formation of a dot and the signal 22 designates a dot smaller than a normal size, the circuit 23 outputs a pulse signal with a pulse width smaller than a predetermined width.

Description

[Detailed description of the invention] [Industrial application fields] The present invention relates to an image processing device that processes pixel signals.

[Prior Art] In recent years, laser beam printers have been widely used as output devices for computers. Especially low density (e.g. 30
Laser beam printers (0 dpi) are rapidly becoming popular due to their low cost and compact size.

For example, in a laser beam printer that prints at a printing density of 300 dpi, as shown in FIG. The printer engine unit 5 receives code data sent from the external host computer 54, generates page information consisting of dot data based on this code data, and
1, and a printer controller 52 that sequentially transmits dot data to the printers 1 and 1. The host computer 54 is loaded with a program by a floppy disk 55 having application software, starts the application software, and operates as, for example, a word processor.

Many types of application software have been created and used, and users create and store a large amount of data using these application software. This data includes text, pictures, etc.

Conventionally, methods such as increasing the resolution of the printer engine 51 have been used to form these characters and pictures as higher-quality images, but each time the resolution changes, the method of generating data such as characters must be considered. It was not practical because it had to be done.

Therefore, in recent years, methods have been devised to obtain high image quality by distinguishing between the pixel of interest and its surrounding pixels and correcting the image. An example of the conventional circuit configuration and processing will be explained based on the drawings. FIG. 7 is a diagram for explaining the configuration of a conventional image processing circuit, and FIG. i8 is its timing chart.

The circuit shown in FIG. 7 is a circuit inserted between the printer controller 52 and the printer engine section 51 as shown in FIG. There is. (Of course, it may also be a part of the printer controller 52.) First, the printer controller 52 transfers the image signal (VDo) 1 to the printer engine in synchronization with the lock (VCLK) 2. Within the printer engine, the received image data is sent to the printer engine. It is stored in eight line buffers 1 to 8 for each scan.

It is the selector 1 (3) that performs this sorting for each scanning line, and switches sequentially from line buffer 1 (4) to line buffer 8 (11), and then switches again to line buffer 1 (4). Of the eight buffers from line buffer 1 to line buffer 8, the buffers other than the line buffer selected by selector 1 repeatedly output the data in the buffers. Each line buffer repeatedly outputs the same content for each scanning line, and continues this output operation until the next data input. The data output from these seven buffers are input to terminals a to g of the discrimination circuit 20, as shown in FIG. That is, by switching with the selector 2 (12), the scanning line including the pixel of interest and three lines each above and below it are input to the discrimination circuit 20. The 0 discriminating circuit 20 whose details are shown in FIG. 9 includes shift registers 26a to 26g and a logic circuit 28. The shift register 26d is a shift register that includes the pixel of interest, and the hatched cell in the center corresponds to the pixel of interest. The pixel of interest and pixel information around the pixel of interest are input to the logic circuit 28 . Furthermore, since the shift registers 26a to 26g shift in synchronization with an image clock (not shown), the contents input to the logic circuit 28 also change in synchronization with the image clock. Details of the logic circuit 28 will be explained next.

FIG. 10 illustrates an example of the conditions for determining the correction process, and assumes that the diagonally shaded circle is the pixel of interest, the black circle is the pixel that will form an image, and the white circle is the pixel that will not form an image.

Taking Figure 10(d) as an example, the pixel to the left of the sex pixel, the pixel to the left of that pixel, the pixel one below the pixel of interest, and the pixel to the right of it are all white (that is, The pixel one above the pixel of interest, the pixel one pixel to the right of the pixel of interest, and the pixel one pixel to the right of the pixel of interest are all black (that is, they form an image). If the conditions are met and the pixel of interest is white, that pixel is determined to be a pixel that forms a smaller image.

However, surrounding pixels (not shown) are not included in the judgment conditions. The above judgments are made for all the logics (a) to (p), and if even one of them matches the logic, the pixel of interest is determined to be a pixel forming a smaller image. When this is expressed as a logical expression, it becomes as shown in FIG. A in the center
Whether or not to form a small image is determined by equation (1), where an overlined image corresponds to white, and an unoverlined image corresponds to black. The logic circuit shown in FIG. 9 is constructed from this logic formula. For example, when the pattern shown in FIG. 10(d) is converted into a circuit, it becomes as shown in FIG. 12. Shift register 30 including the pixel of interest and lines n-1 and n+ above and below it
Logic gates 32 to 34 determine the portion corresponding to the pattern (d) from the shift register 29.degree. 31 containing 1. Judgment by this logic circuit is made for all patterns shown in FIGS. 10(a) to 10(p).

According to the above logical formula, a smaller pixel is formed by applying PWM (pulse width modulation) at a location determined to be a pixel forming a smaller image.

Note that the discrimination circuit 20 sends a signal 21 indicating whether or not to form a dot to the PWM circuit 23 and a signal 22 indicating whether or not the dot is small. Based on the drive signal 24 to the laser driver
Send out.

FIG. 13 shows an image subjected to this processing.

Form small dots 35 and 36 in the shaded area. These small dots are drawn toward the image side during development, and as a result, reduce jaggedness that occurs in diagonal lines.

FIG. 14 shows the appearance of small dots when this process is applied to Albet's raJ.

■ indicates the original one dot, and ★ indicates the position where a small dot is generated. According to this method, the shaded areas can be made smooth with small dots.

[Problems to be Solved by the Invention] However, in the conventional example described above, although the diagonal lines can be made smooth, as shown in FIG. 7, the disadvantage is that multiple line buffers are required and the circuit becomes very expensive. .

In particular, when attempting to view surrounding pixels in a large area, additional line buffers must be added, which poses a cost problem.

The present invention has been made in view of the above points, and it is an object of the present invention to provide an image processing device that can process pixel signals at low cost.

[Means for Solving the Problems] In order to achieve the above object, an image processing apparatus of the present invention has the following configuration.

That is, an image processing device that outputs a plurality of pixel signals corresponding to a plurality of lines includes an input means for sequentially inputting pixel signals, and a storage means for storing each bit of the pixel signal input from the input means line by line. Equipped with.

[Operation] In the above configuration, the storage means is configured to be able to store pixel signals for a plurality of lines in each of the bits, and operates to read out a plurality of pixel signals corresponding to a plurality of lines from each bit.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[First Embodiment] FIG. 1-1 shows the configuration of an image processing apparatus in this embodiment. Incidentally, those having the same mechanism as in Fig. 7 are given the same symbols. Figures 1-2 and 1-
FIG. 3 is a timing chart explaining the operation of FIG. 1-1.

First, the sequentially input pixel signals VDOI are input to the 0 bit of the memory 65 via the 3-state latch 64. During this operation, the address counter 66 is counted up by the image clock VCLK2, so the address 0 of the memory 65 is
The current pixel signal VDO1 is sequentially stored in the O bit.

When the pixel signal VDOI is stored at the 0 bit position for one line, the address counter 66 is reset by the horizontal synchronizing signal HSYNC, and the next line is similarly stored at the 0 bit position.

However, the one line of data previously stored in the O bit is sent to the discrimination circuit 20 via the 3-state latch 64 and at the same time stored in one bit of the memory 65. As a result, seven lines of pixel information 67 to 73 can be simultaneously and continuously sent to terminals a to g of the discrimination circuit 20 without using a line buffer for eight lines as shown in FIG.

A timing chart showing this operation is shown in FIGS. 1-3.

In this embodiment, it is necessary to perform four operations during the formation of one pixel: counting up the address counter 66, reading the memory 65, latching the 3-state latch 64, and writing the memory 65. FIG. 1-2 shows the timing.

At the rising edge of the image clock VCLK2, the address counter 66 is counted up and enters read mode.

The remote mode ends when VCLK2 falls. The LAT 62 shown in FIG.
This is a timing signal for latching data read from 5. Also, this latched value is returned to the memory by the timing signal 0E63, and the timing signal W60
Write to memory with .

The pixel data input to the discrimination circuit 20 through the above operations becomes a reproduced image by the method described above. As described above, the determination circuit 20 determines whether the pixel of interest is a pixel on which a dot should be made and the size when reproducing it as a dot, based on the data corresponding to the pixel of interest and its surrounding pixels.

The PWM circuit 23 receives the signal 21 input from the discrimination circuit 20.
．． 22, a pulse width modulated signal is sent to the laser driver 25. For example, when the signal 21 instructs the formation of a dot and the signal 22 instructs the formation of a normal size dot, a pulse signal of a predetermined width is sent out. Further, when the signal 21 instructs the formation of a dot and the signal 22 instructs the formation of a dot smaller than the normal size, a pulse signal having a width shorter than the predetermined width is sent out.

[Second Embodiment] In the first embodiment described above, data from the memory 65 is input to the discrimination circuit 20, but when data from the memory (8 bits in this embodiment) and VDOl are input to the discrimination circuit 20. The circuits after the implementation determination circuit 20 latch the omitted 0 pixel signal VDO1 with the latch 64 and then input it to the terminal a of the determination circuit 20, and also input the data from the 7th bit of the memory into another 7 bit.
By adopting a configuration in which 6 is inputted to the terminal i of the discriminating circuit 20, the maximum number of bits of the memory to be used +
1 line information can be input to the discrimination circuit 20. By adopting this configuration, it is possible to input peripheral pixel information over a wider range. In addition, each signal LAT
62.

0E63. The timing of W2O, HSYNC61 VCLK is the same as in FIG. 1-2.

[Third Embodiment] In the embodiment described above, an image is formed in synchronization with the clock VCLK2. Therefore, if the means for generating VDO1 and VCLK2 is different from the printer engine, for example, the controller 52 (see FIG. 15) generates VDO1.

When generating VCLK2, Who and LAT62,0
Since it is necessary to generate E63 in synchronization with VCLK2, it is necessary to transfer signals such as W2O from the controller 52. In this case, generating the signal within the controller 52 and the printer engine would complicate the circuit.

Therefore, the configuration can be further simplified by using VCLK2 as a clock for pixel signal transfer and separating it from the image forming lock 5CLK83 on the engine 51 side.

An embodiment in that case is shown in FIG. Components having the same functions as those in FIG. 1 are given the same symbols, and the discrimination circuit 20
The subsequent circuits have been omitted.

79 is a toggle memory, and horizontal synchronization signal H3YNC6
1, the memory switching unit 82 switches between line memory 1 (80) and line memory 2 (81) in line units.

Now, if the pixel signal VDOI is written to the line memory 2 in synchronization with the clock VCLK2, the line memory 1 is in the readout state, and the data (pixel signal VDOI) is written in synchronization with the clock 5CLK83 generated inside the printer engine. )77 is being read. Furthermore, W2O, CA
Signals such as T62 and 0E63 are generated based on the clock 5CLK83. Conversely, pixel signal VDO1 is clock VC
If it is written to line memory 1 in synchronization with LK2, line memory 2 is in a read state and clock 5
Data 77 is read out in synchronization with CLK83.

Note that the write and read states of line memory 1.2 are HSY.
Switched in synchronization with NC61.

Other operations are similar to those in the first embodiment, so detailed explanations will be omitted.

[Fourth Example] Next, an example in which the image data is multivalued data is shown in Section 4-1.
As shown in the figure.

Components having the same functions as those in FIG. 1-1 are given the same symbols, and circuits after the discrimination circuit 20 are omitted. The basic operation is the same as that shown in FIG. 1-1, or the 2-bit image data VDOa (86) and VDOb (87) are input to the O bit and 1 bit of the memory 65 via the 3-state latch 64. . It is input as data 3 of 0 bit and 1 bit. Further, 84.85 is a latch. By handling data in units of 2 bits in this manner, multi-value data (89-98) for a total of 5 lines, including 2 lines each for the upper and lower lines, can be sent to the discrimination circuit 20. This result determination circuit 20
can perform a more accurate discrimination operation than when binary data is input. A timing chart showing the operation of the circuit of FIG. 4-1 is shown in FIG. 4-2.

Further, although the present embodiment has been described using 2-bit multi-value data as an example, the number of multi-value bits is not limited.

[Fifth Embodiment] In the second embodiment, it was stated that the number of lines that can be handled in one memory is (number of bits + 1) trees. If a larger number of lines is used, a configuration that handles a plurality of memories as shown in FIG. 5 may be used.

The image processing device shown in FIG. 5 uses two memories and processes data (a=q) of 17 lines (67 to 75) @ discrimination circuit 2.
It is possible to send it to 0. memory 65 and memory 65
' is operated based on the same control method as in the previous embodiment.

In FIG. 5, components having the same functions as those in FIG. 2 are given the same symbols, and the discrimination circuit 20 and the like are omitted.

By connecting a plurality of memories using this method, a buffer with the required number of lines can be configured.

[Sixth Example] Next, Section 6-1 shows an example in which interpolated data is added to data obtained from a controller with a resolution of 300 dpi and applied to a conversion circuit that converts the data into data for a printer engine with a resolution of 600 dpi. Components shown in the figure that have the same functions as those in Figure 3 are given the same symbols, and the discrimination circuit 2
The circuit after 0' is omitted.

VDOI and VCLK2 are pixel data and image clock for 300 dpi, and are input to the toggle buffer 79 described in the third embodiment. Data is read from this toggle buffer 79 at the station frequency of the 600 dpi image clock 5CLK and is taken into the 600 dpi luminous clock 5CL memory, so the data is doubled in the main scanning direction. The switch SWI (103) switches between data from the toggle buffer 79 and data from the memory 65, and its timing is shown in FIG. The frequency converter 121 outputs the external horizontal synchronizing signal HSYNC to the external device once every time the horizontal synchronizing signal H3YNC is input twice.
This is an external horizontal synchronization signal generator that outputs '. 104 to 1 by switching the switch SWI in main scanning units.
The data on 11 is lifetime scanning data repeated twice. By inputting this data to the discrimination circuit 20' shown in No. 6-3, an interpolation line 115 is created by converting 300 dpi to 600 dpi.

Switch SW2 switches to side a and side b.

When SW2 is on the a side, the interpolation line is the output 113 from the logic circuit 116. The logic circuit 116 generates an interpolation line from the upper and lower lines, and a well-known method can be used.

As described above, according to this embodiment, by managing image information in line units and storing the line unit information in each bit of memory, it is possible to replace multiple line memories with one memory. , which has improved economic efficiency.

In the above embodiment, a memory with a capacity of 1 main scanning line x 7 bits was used, but another memory capacity of m words x n bits (m
, n is a natural number).

Furthermore, although this embodiment has been described using a configuration in which a plurality of pixel data are input to the discrimination circuit, a configuration may be adopted in which a plurality of pixel data are input to a processing circuit other than the discrimination circuit.

[Effects of the Invention] As explained above, according to the present invention, it is possible to reduce the cost of the device and downsize the circuit board.

[Brief explanation of the drawing]

1-1 is a diagram showing the image processing device in the first embodiment, FIGS. 1-2 and 1-3 are timing charts showing the operation of the circuit in FIG. 1-1, and FIG. FIG. 3 is a diagram showing an image processing device in the second embodiment, FIG. 3 is a diagram showing the image processing device in the third embodiment, FIG. 4-1 is a diagram showing the image processing device in the fourth embodiment, Figure 4-2 is the fourth
1 is a timing chart showing the operation of the circuit, FIG. 5 is a diagram showing the image processing apparatus in the fifth embodiment, and FIG.
Figure 1 is a diagram showing the image processing device in the sixth embodiment, Figure 6-2 is a timing chart diagram showing the operation of the circuit in Figure 6-1, and Figure 6-3 is the discrimination diagram in Figure 6-1. 7 is a diagram showing a conventional image processing device; FIG. 8 is a timing chart showing the operation of the circuit in FIG. 7; FIG. 9 is a detailed diagram of the discrimination circuit 20; FIG. 10 is a detailed diagram of the circuit 20'. 11 is a diagram for explaining the discrimination operation, FIG. 12 is a diagram showing a specific example of the logic circuit 28, FIGS. 13 and 14 are diagrams showing an example of image output, and FIG. 15 is a diagram showing the external equipment, printer controller,
FIG. 3 is a diagram showing a connection relationship of printer engines. In the figure, 3.12 is a selector, 4 to 11 are line buffers,
20 is a discrimination circuit, 23 is a PWM circuit, 25 is a laser driver, 64 is a three-state latch, 65 is a memory, and 66 is an address counter.

Claims (2)

[Claims] (1) In an image processing device that outputs a plurality of pixel signals corresponding to a plurality of lines, an input means for sequentially inputting pixel signals, and a memory for storing the pixel signals input from the input means in each bit line by line. means, wherein the storage means is configured to be able to store pixel signals for a plurality of lines in each of the bits, and read out a plurality of pixel signals corresponding to the plurality of lines from each bit. Image processing device. (2) Furthermore, the holding means is configured to hold the pixel signal read from the storage means, and the holding means is configured to write the pixel signal read from the first bit of the storage means into the second bit. An image processing apparatus according to claim (1), characterized in that: