JP2003099391A - Dma-forwarding method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DMA-forwarding method, preventing forwarding errors in a response data for DMA demand consisting of a plurality of channels, in a composited image forming process apparatus. SOLUTION: In the DMA-forwarding method constituted from DMAC which is the source of demand for plurality of data, an arbiter 1084 adjusting the data demands of DMAC and a data control part carry out data access demand to a data providing source such as an outside memory according to the adjusted result and administrating the exchange of forwarding data in between the DMAC and the data supplying source, the DMAC is provided with an outputting means, which outputs specified inside information with the demand signal when an access demand is made. In this case, the data control part is provided with a storage means 1083 temporarily saving the access demand by the DMAC, which is permitted by the adjustment and the inside information paired with it. Furthermore, a checking means 1086 is provided for checking the inside information saved to the storing means 1083 with the present inside information, which is outputted from the output means at the time of reception of the response data for the access demand, and when they do not match, the response data is deemed as being ineffective.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA transfer system, and more particularly to a digital copying machine, a scanner, a printer,
The present invention relates to a DMA transfer method capable of appropriately managing a DMA request including a plurality of channels in an image processing apparatus such as a FAX.

[0002]

2. Description of the Related Art In recent years, with the spread of digital copying machines, processing and editing using image memories have been actively performed on the copying machines. The processing and editing functions of the digital copying machine include, for example, image rotation by address operation when reading from the image memory, image repeat by forming a plurality of data of the same pattern on the image memory, and writing at the image memory. There is an aggregate copy of a plurality of originals on one transfer sheet by an address operation. In order to realize such a function, a digital copying machine is usually provided with an image memory capable of developing image data for at least one original.

By the way, in the composite type image forming apparatus as described in JP-A-8-149241, a scanner,
By connecting each functional device such as a printer and a controller with an image memory for storing images with a general-purpose bus,
There has been proposed a system aiming at making a system with a high degree of expandability by making an interface common and suppressing unnecessary circuits and control software for connecting different devices.

[0004]

However, in general, when a read access is made to an external memory connected via a general-purpose bus, a bus bridge, etc., the response time is the memory to the directly connected RAM or the like. It will be larger than in the case of access. For example, the request source for memory access is DMAC (Direct Memory Access Controller)
Therefore, if the requested DMA is forcibly terminated for some reason before the response data is received, the response data corresponding thereto becomes invalid data. This is not a problem in this case, but the response time is large enough that the next DMA before the invalid data arrives.
When activating, the situation occurs in which the DMA data from the previous activation is erroneously received.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems of the prior art and has as its object to solve the following matters. The first purpose is to temporarily store the internal state of the DMAC at the time of memory request, and compare and collate with the internal state of the current DMAC at the time of receiving response data, so that invalid data at the previous DMA start is not accidentally transferred. Reliable D
It is to provide an MA transfer method.

A second object of the present invention is to provide a DMA transfer system in which a circuit for data processing of a plurality of DMACs is carried out at one place so that the cost can be reduced by a simple structure.

A third object is to provide a DMA transfer system which can achieve both the first object and the second object.

[0008]

The present invention employs the following means in order to solve the above problems.

A first means is a plurality of data request sources, a DMAC, an arbiter that arbitrates data requests of the DMAC, a data access request to a data supply source such as an external memory from the arbitration result, and In the DMA transfer method, which comprises a DMAC and a data control unit that manages the transfer of transfer data between a DMAC and a data supply source, the DMAC internally outputs predetermined internal information together with a request signal when an access request is made. The data control unit has an information output unit, the data control unit has an internal information temporary storage unit that temporarily stores internal information paired with the access request of the DMAC permitted by the arbitration, and when receiving response data to the access request, A predetermined process is performed on the response data based on the stored internal information.

According to a second means, in the first means, the internal information is composed of n-bit activation order information counted every activation of a series of data transfer by the DMAC, and the data control is performed. When receiving the response data, the section collates the internal information stored in the internal information temporary storage means with the current internal information output from the internal information output means. It is characterized by having invalid data collating means.

A third means is the first means, wherein the internal information is data processing information to be applied to the response data by the DMAC, and the data control unit receives the response data when the response data is received. It is characterized by further comprising data processing means for processing the response data based on the internal information stored in the internal information temporary storage means.

[0012] According to a fourth means, in the first means, the internal information is n-bit activation sequence information counted each time the DMAC activates a series of data transfer in page units, and the DMAC responds to the response. The data control unit is composed of data processing information to be applied to data, and when the response data is received, the data control unit stores internal information stored in the internal information temporary storage unit and current internal information output from the internal information output unit. If you don't match
It is characterized by further comprising data collating means for invalidating the response data and data processing means for processing the response data based on the internal information stored in the internal information temporary storage means.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an outline of an electrical configuration of a composite image forming apparatus including various image processing devices.

In the figure, reference numeral 10 denotes a system controller for controlling the entire image forming apparatus. The system controller 10 has an operation / display board OPB for displaying to the operator, controlling the function setting input from the operator, and issuing a copy instruction. Connected.

Further, the system controller 10 analyzes a command for instructing an image and print from the outside such as a personal computer in addition to control related to normal copy processing,
As image data, a bitmap control is performed in a printable state and the printer 400 is driven to perform print control for printing out the image data. Further, the system controller 10 sends images and commands to a LAN or parallel I / O.
LAN control and parallel I / F for receiving and operating through F are provided.

When there is a facsimile transmission instruction, the facsimile board FXB drives the scanner 200 via the controller 10 to read the image of the original, and the image data is transferred to the communication control and facsimile board FX.
It is sent to the facsimile communication line via B. When a facsimile call is received from the communication line and image data is received, the printer 4 is sent via the system controller 10.
00 to print out the image data by the printer 400.

The scanner 200 and the printer 400 have a PCI (Peripheral Comp) which is a general-purpose bus.
It is possible to communicate with each other via the present interconnect bus 12. Scanner 20
The image data read by 0 is signal deterioration due to the image processing (IPU) in the image data due to quantization of the read image data into an optical system and a digital signal (signal deterioration of the scanner system, scanner It is possible to correct the distortion of read image data due to the characteristics, and send the corrected image data to the printer 400 or write it in the image memory 11 connected to the system controller 10.

The scanner 200 includes a job for storing the read image data in the image memory 11 for reuse and a job for outputting the read image data to the printer 400 without storing it in the image memory 11. As an example of storing the original in the memory 11, when copying one sheet of a plurality of sheets, the scanner 200 is operated only once, the read image data is stored in the memory 11, and the stored data is read out a plurality of times. is there. Also,
As an example of not using the image memory 11, one original is
In the case of copying only one sheet, the read image data may be output to the printer 400 as it is, and it is not necessary to write it in the image memory 11. If the read image data is to be stored for a relatively long period of time, the read image data is written in an image memory, floppy disk, compact disk, hard disk or DVD (not shown) which is already installed or added. In addition, print data (text data, which is text data, or pixel data, which is image data) provided from the host computer PCa is handled in the same manner.

Further, the case where the image memory 11 is not used will be described.
At U, image quality processing for converting the luminance data by the CCD into area gradation is performed. The signal subjected to the image quality processing and changed into the area gradation is sent to the printer 400, and given to the writing control in the printer 400 via the image memory therein. The writing control in the printer 400 performs post-processing regarding dot arrangement and pulse control for reproducing dots to the image forming unit in the printer 400,
A reproduced image is formed on the transfer paper.

When the image memory 11 is used, the system controller is used in the case where the image memory 11 is stored in the image memory 11 and read from the image memory 11 for additional processing, for example, rotation of the image direction and image composition. Within 10, the access control of the image data and the image memory 11, the expansion of the print data of the host computer PCa (character code / character bit conversion), and the compression / expansion of the image data for effective memory utilization are performed. The data sent to the image memory 11 is stored in the memory after data compression in the image memory 11, and the stored data is read as needed. The read data is expanded in the image memory 11, restored to the original image data, and transferred to the printer 40 via the PCI bus 12.
Output to 0.

In the flow of image data, the composite function of the digital copying machine is realized by data transfer on the PCI bus 12 under the bus control of the controller 10. The FAX transmission function, which is one of the composite functions, transfers the image data read by the scanner 200 to the facsimile board FXB via the PCI bus 12.

In each job, for example, the copy function, the facsimile transmission / reception function, and the printer output function, a general-purpose bus to the scanner 200, printer 400, image memory 11 and facsimile board FXB, that is, PCI.
The system controller 10 controls the allocation of the usage right of the bus 12 via its bus control function.

FIG. 2 is a diagram showing an internal configuration of the system controller 10 shown in FIG.

The internal local bus 10 will be described below.
All access to the image memory 11 of the bus master on 7 is performed via the bus control unit 108, the general-purpose high-speed bus 109, and the bus bridge 111.

Next, the configuration of each part of the system controller 10 will be described.

The PCI I / F unit 103 is a PCI bus 1
2 and an internal local bus 107, which receives an address and data designated by a PCI bus master such as the scanner 200 or the printer 400 to receive the image memory 11
I / O to.

A DMAC (Direct Memory Access Controller) 105 for image transfer is activated by the CPU 110, and at the time of compression, it reads out image data from the image memory 11 in a predetermined area and compresses / expands the data.
The data is output to 1 and the compression / expansion unit 10 is used for expansion.
The image data received from 1 is written to the image memory 11 in a predesignated area.

The code transfer DMAC (Direct Memory Access Controller) 104 is activated by the CPU 110, receives the compressed code data output from the compression / expansion unit 101 during compression, and receives the image memory 11 in a predetermined area. Write to. Further, at the time of decompression, the code data is read from the image memory 11 in the area designated in advance and output to the compression / decompression unit 101. At the time of compression, the amount of code data received from the compression / expansion unit 101 is counted, and at the end of compression, the CPU 110 can know the count value via an internal register.

The compression / expansion unit 101
The image data received from the image transfer DMAC 105 is compressed and output to the code transfer DMAC 104 as code data, and when decompressed, the code data received from the code transfer DMAC 104 is decompressed and output to the image transfer DMAC 105 as image data. . At the time of compression, a compression end signal is also output to notify the code transfer DMAC. In this embodiment, the MH encoding method is used.

A DMAC (Direct Memory Access Controller) 106 for HDD transfer is a DM for HDD transfer.
AC is used to transfer data between the image memory 11 and the HDD 102.

The CPU 110 draws in the image memory 11 based on the printer language when all system-related settings are made, the DMAC is activated, and printer data is received from the host computer. At the time of drawing, an image of one page is usually divided into a plurality of bands and drawn.

In the bus bridge 111, the CPU 110 serves as a master to access the image memory 11, the internal PCI bus 112 and the general purpose high speed bus 109, and the internal local bus 107 side serves as a master to access the image memory 11 via the general purpose high speed bus 109. It acts as a bridge of the path to do. An address decoder and a memory control circuit are provided inside.

The communication system I / F unit 114 is a PC shown in FIG.
PCa, operation board OPB, facsimile board FX
Data transmitted / received to / from the CPU 1 via the internal PCI bus 112 via an internal register.
Communicated with 10.

The ROM 113 is a non-volatile memory that mainly stores the programs of the CPU 110.

The bus control unit 108 uses the internal local bus 1
07 and the interface circuit of the general-purpose high-speed bus 109. The detailed internal configuration will be described below.

FIG. 3 is a diagram showing an internal configuration of the bus control unit 108 shown in FIG.

The bus control unit 108 is composed of a clock-synchronized logic circuit, and is roughly divided into a circuit related to master control of a general-purpose high-speed bus and a circuit related to target control. Will be described in detail, and circuits related to target control will be briefly described.

The internal information temporary storage unit 1083 is a storage unit for storing and saving the internal information 1089 selected and output by the internal information selector (1) 1081 at the timing of the access request from the arbiter 1084. The general-purpose high-speed bus 109 has a one-to-one correspondence between request command transfer and data transfer.
When performed independently, the arbitration information is also stored in pairs as a queue structure capable of sequentially storing a plurality of internal information.

The internal information selector (1) 1081 transfers the internal information from the request source to the arbitration information 1 from the arbiter 1084.
The internal information selector (2) 1082 is configured in the same manner as the internal information selector (1) 1081 in the present embodiment. However, when the internal information temporary storage unit 1083 has a queue structure, It is selected by the arbitration information stored in the internal information temporary storage unit 1083.

The arbiter 1084 is connected to the bus shown on the left side of the internal local bus 107 shown in FIG.
When one of the blocks 103 to 106 becomes the master and the request signal 1090 is output to the arbiter 1084, the arbiter 1084 permits one of the request signals 1090 according to the state of the master control unit 1085, and the access request signal 1
095 is output to the master control unit 1085. At this time, although not shown, a permission signal is output to the authorized request source. Arbitration information 1091 for indicating the permitted request source is output.

The master control unit 1085 has the arbiter 108.
General-purpose high-speed bus 10 in response to access request 1095 from
9, the master controller 1085 receives the command information selected according to the arbitration information 1091, the request address, and the write data if it is a write, which is reflected in the general-purpose high-speed bus 109 (not shown). To be done. When read access is made to the general-purpose high-speed bus 109, if the read data can be prepared, the read data 10 is sent together with the valid source signal 1096 indicating the presence of the read data.
97 is output.

The target control unit 1088 performs a target operation when the bus master of the general-purpose high-speed bus 109 is the CPU 110, decodes from address information accessed by the target operation, and accesses an internal register such as a DMAC. Register access bus 10
Connected to 94.

The data collating unit 1086 is the master control unit 1
Based on the request source signal from 085, it has a function of dividing the arbitration information into four valid signals and outputting them. Normally, the inside of the request source at the time of the access request stored and stored in the internal information temporary storage unit 1083 is used. Compare the information with the current inside information,
If they match, one of the valid signals 1092 to be output is made active. The internal information includes 3-bit DMA activation information, which is the content counted every time DMA activation is performed in page units on the DMAC side. If they do not match in the data collation, none of the valid signals are activated, which makes it possible to avoid the erroneous transfer of invalid read data at the previous DMA activation.

The data processing unit 1087 is the master control unit 1
Read data 1097 from 085 is converted to internal information 1089.
Processing is performed according to the data processing information included together with the DMA activation information of No. 1, and is output to the read data bus 1093 on the internal local bus 107 side. Specific processing contents are black-and-white inversion of image data, array conversion of bit arrangement, and the like. As a result, it becomes possible to perform a circuit for data processing of a plurality of DMACs at one place.

[0046]

According to the invention described in claim 1, the internal state of the DMAC at the time of the access request is temporarily stored, and when the response data is received, a predetermined process is performed on the response data based on the previously stored internal information. Therefore, it is possible to provide a DMA transfer method capable of performing appropriate transfer processing for an access request.

According to the second aspect of the present invention, the internal state of the DMAC at the time of memory request is temporarily stored, and by comparing and collating with the current internal state of the DMAC at the time of receiving response data, the DMA request at the time of the previous DMA activation. It is possible to provide a highly reliable DMA transfer method that avoids erroneous transfer of invalid data for.

According to the invention described in claim 3, a plurality of DMs
Since the circuit for data processing of AC can be performed at one place, DMA with a simple structure and low cost
It becomes possible to provide a transfer method.

According to the invention described in claim 4, it is possible to provide a DMA transfer system which can exert the effects of the inventions described in claims 2 and 3 together.

[Brief description of drawings]

FIG. 1 is a system configuration diagram illustrating an outline of an electrical configuration of a composite image forming apparatus including various image processing apparatuses.

FIG. 2 is a diagram showing an internal configuration of a system controller 10 shown in FIG.

3 is a diagram showing an internal configuration of a bus control unit shown in FIG.

[Explanation of symbols]

10 system controller 101 compression / decompression section 102 HDD 103 PCI I / F section 104 DMAC for code transfer 105 Image transfer DMAC 106 HDD transfer DMAC 107 Internal local bus 108 Bus control unit 1081 Internal Information Selector (1) 1082 Internal information selector (2) 1083 Internal information temporary storage unit 1084 Arbiter 1085 Master control unit 1086 Data collation unit 1087 Data processing unit 1088 Target control unit 1089 Inside information 1090 request signal 1091 Mediation information 1092 Valid signal 1093 read data bus 1094 Internal register access bus 1095 Access request 1096 Effective source signal 1097 Read data 109 General-purpose high-speed bus 110 CPU 111 Bus Bridge 112 Internal PCI bus 113 ROM 114 Communication system I / F 11 Image memory 12 PCI bus 200 scanner 400 printer PCa Host computer FXB facsimile board OPB operation board

Claims (4)

[Claims] 1. A DMAC, which is a plurality of data request sources,
An arbiter that arbitrates the data request of the DMAC and a data access request to a data supply source such as an external memory from the arbitration result, and a transfer data exchange DM
In a DMA transfer system composed of an AC and a data control unit that manages between a data supply source, the DMAC has internal information output means for outputting predetermined internal information together with a request signal when an access request is made. , The data control unit is the DMAC permitted by the arbitration.
Of the access request, the internal information temporary storage means for temporarily storing internal information paired with the access request is provided, and when the response data to the access request is received, predetermined processing is performed on the response data based on the stored internal information. A DMA transfer method characterized in that 2. The internal information is composed of n-bit activation order information that is counted every activation of a series of data transfers by the DMAC in page units, and the data control unit receives the response data when the response data is received. It has a data collating means for collating the internal information stored in the internal information temporary storage means with the current internal information output from the internal information output means, and if they do not match, invalidate the response data. The DMA transfer system according to claim 1, characterized in that. 3. The internal information is composed of data processing information to be applied to the response data by the DMAC,
The data control unit includes a data processing unit that processes the response data based on internal information stored in the internal information temporary storage unit when the response data is received. DM
A transfer method. 4. The internal information is composed of n-bit activation order information counted every time the DMAC starts a series of data transfers in page units, and data processing information to be applied to the response data by the DMAC. When the response data is received, the data control unit compares the internal information stored in the internal information temporary storage unit with the current internal information output from the internal information output unit, and if they do not match, The data collating means for invalidating the response data, and the data processing means for processing the response data based on the internal information stored in the internal information temporary storage means. DMA transfer method.