JPH0522152A - Msb/lsb conversion circuit - Google Patents

Abstract

PURPOSE:To reduce a hardware and to enable high-speed conversion concerning the MSB/LSB conversion circuit to exchange the MSB and LSB of data having (n) bits. CONSTITUTION:This MSB/LSB conversion circuit to convert and output the MSB and LSB of data in respect to the data of the (n) bits is equipped with a register 1 to store the data of the (n) bits and a drive circuit 2 to drive the parallel output of the register 1 and to output it to a parallel signal line 5. The register 1 and the drive circuit 2 or the drive circuit 2 and the parallel signal line 5 are related so as to exchange the positions of the MSB and the LSB in the data of the (n) bits.

Description

Detailed Description of the Invention

[0001] (table of contents) Industrial applications Conventional technology (Fig. 3) Problems to be Solved by the Invention Means for Solving the Problems (FIG. 1) Action Example (a) Description of one embodiment (FIG. 1) (b) Description of another embodiment (FIG. 2) The invention's effect

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to an MSB-LSB conversion circuit that interchanges SB and LSB.

With the recent development of computers, various CPUs and peripheral circuits have been combined to form devices. In the case of such a combination, the circuit of one manufacturer and the circuit of another manufacturer may be used in combination.

In this case, the data of the MSB (Most Significa
There is a completely opposite position of nt Bit) and LSB (Least Significant Bit).

For example, in the Motorola CPU, the 7th bit is the MSB and the 0th bit is the LSB.
In the peripheral circuit of Intel Corporation, the 7th bit is the LSB and the 0th bit is the MSB. In order to exchange data by combining such circuits, an MSB-LSB conversion circuit that converts the positions of MSB and LSB of data is required.

[0006]

2. Description of the Related Art FIG. 3 is an explanatory diagram of a conventional technique. Figure 3
As shown in (A), for example, for 8-bit data, if the 7th bit is MSB and the 0th bit is LSB, it is necessary to replace 7-0 bits with 0-7 bits for conversion. .

Therefore, conventionally, as shown in FIG. 3B, a pair of shift registers 10 and 11 are provided, and
After the 8-bit data of (A) is set in the shift register 10, the shift register 10 is shifted to the right and the shift register 11 is shifted to the left, and the data at the left end of the shift register 10 is shifted to the left end of the shift register 11. By inputting, the shift register 11 forms data with the bit positions interchanged, and the shift register 11 is read.

As another conventional technique, as shown in FIG. 3 (C), an MS for original data is stored in the memory 12.
A table storing conversion data in which B and LSB are exchanged is provided, conversion data corresponding to original data is read from the table, and conversion data in which MSB and LSB are exchanged is obtained.

[0009]

However, the prior art has the following problems. In the former conventional technique, if the data has n bits, a shift operation is required n times, so that high-speed conversion cannot be performed.

In the latter prior art, a memory capacity corresponding to the number of bits of data is required, and if the data is 16 bits, a huge memory capacity is required and the hardware increases.
The price will also increase. Therefore, it is an object of the present invention to provide an MSB-LSB conversion circuit which requires less hardware and enables high-speed conversion.

[0011]

FIG. 1 is a principle diagram of the present invention and a circuit diagram of an embodiment. According to claim 1 of the present invention, in an MSB-LSB conversion circuit which converts MSB and LSB of n-bit data and outputs the same, a register 1 for storing the n-bit data and the register 1 And a drive circuit 2 for driving the parallel output of the drive circuit 2 and outputting the parallel output to the parallel signal line 5, and the connection relationship between the register 1 and the drive circuit 2 or the connection relationship between the drive circuit 2 and the parallel signal line 5. Is configured such that the MSB position and the LSB position in the n-bit data are replaced with each other. According to a second aspect of the present invention, in the first aspect, the parallel signal line 5 is a bus of the CPU 4, and the register 1 is connected to the bus.

[0012]

According to the first aspect of the present invention, the register 1 for storing n-bit data and the drive circuit 2 for driving the parallel output of the register 1 to output to the parallel signal line 5 are provided. Since the connection relationship between the drive circuit 2 or the connection relationship between the drive circuit 2 and the parallel signal line 5 is configured such that the MSB position and the LSB position in the n-bit data are interchanged, it is possible to write the data to the register 1. , Can be converted in 2 steps of reading the drive circuit 2,
High-speed conversion is possible, and it can be realized with less hardware.

In claim 2 of the present invention, the parallel signal line 5 is
Since the register 1 is the bus of the CPU 4 and is connected to the bus, the conversion data can be obtained at high speed at the time when the CPU 4 needs it.

[0014]

EXAMPLES (a) Description of an Example An example of the present invention will be described with reference to FIG. In FIG. 1, the CPU 4 is connected to other peripheral circuits by an 8-bit bus 5 (D7 to D0).

The MSB-LSB conversion circuit 3 has one LS.
8-bit flip-flop 1 composed of I
And an 8-bit drive circuit 2. The 8-bit flip-flop 1 is the D of the bus 5 in order from the top.
It is connected to 0 to D7 and stores the data of D0 to D7 of the bus 5 by the write signal WRITE from the CPU 4.

The 8-bit drive circuit 2 transfers the data of the flip-flop 1 to the read signal READ from the CPU 4.
Drive and output to bus 5,
The data D0 is D7 of the bus 5 and the data D1 is D of the bus 5.
6, data D2 to D5 of bus 5, data D3 to D4 of bus 5, data D4 to D3 of bus 5, data D5
Is connected to D2 of the bus 5, data D6 is connected to D1 of the bus 5, and data D7 is connected to D0 of the bus 5.

Therefore, when the CPU 4 sends the data to be converted to the bus 5 and issues the write signal WRITE,
When the data on the bus 5 is stored in the flip-flop 1 and then the read signal READ is generated, the drive circuit 2 outputs the converted data to the bus 5, and the data can be fetched.

In this way, with less hardware,
High-speed conversion becomes possible, and particularly conversion operation under the control of the CPU 4 becomes possible. The flip-flop 1 and the drive circuit 2 are general-purpose LSIs and can be realized simply by setting the connection with the bus 5, and can be realized easily at low cost.

(B) Description of another embodiment FIG. 2 is a circuit diagram of another embodiment of the present invention. In the figure, the same components as those shown in FIG. 1 are designated by the same symbols.
In this example, instead of changing the connection between the drive circuit 2 and the bus 5, the connection between the flip-flop 1 and the drive circuit 2 is changed.

That is, in the connection relationship between the flip-flop 1 and the drive circuit 2, the data D of the flip-flop is
0 is D7 of the drive circuit 2, data D1 is D6 of the drive circuit 2, data D2 is D5 of the drive circuit 2,
The data D3 is connected to D4 of the drive circuit 2, the data D4 is connected to D3 of the drive circuit 2, the data D5 is connected to D2 of the drive circuit 2, the data D6 is connected to D1 of the drive circuit 2, and the data D7 is connected to D0 of the drive circuit 2. It was done.

Even in this case, the same effect as that of the embodiment of FIG. 1 can be obtained, but a general-purpose LSI cannot be used. In addition to the above-described embodiment, the present invention can be modified as follows. In the above embodiment, the data is 8 bits, but other numbers of bits such as 16 bits may be used, and the larger the number of bits, the greater the effect.

Although the example of using it as the peripheral circuit of the CPU 4 has been described, it may be used for other purposes. Although the present invention has been described with reference to the embodiments, various modifications are possible within the scope of the gist of the present invention, and these modifications are not excluded from the scope of the present invention.

[0023]

As described above, according to the present invention,
It has the following effects. The connection relationship between the register 1 and the drive circuit 2 or the connection relationship between the drive circuit 2 and the parallel signal line 5 is determined by the MSB position and the LSB in the n-bit data.
Since the positions are changed, the data can be converted in two steps of writing the data to the register 1 and reading the drive circuit 2, which enables high-speed conversion and can be realized with less hardware. Moreover, the timing of the conversion operation can be controlled by controlling the register 1 and the drive circuit 2, and the conversion data can be obtained at a desired timing.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention and a circuit diagram of an embodiment.

FIG. 2 is a circuit diagram of another embodiment of the present invention.

FIG. 3 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

1 register 2 drive circuit 3 MSB-LSB conversion circuit 4 CPU 5 buses

Claims (2)

[Claims] 1. For n-bit data, M of the data
In an MSB-LSB conversion circuit which converts SB and LSB and outputs the same, a register (1) for storing the n-bit data and a parallel output of the register (1) are driven to drive a parallel signal line (5). And a drive circuit (2) for outputting to the register, the connection relationship between the register (1) and the drive circuit (2) or the connection relationship between the drive circuit (2) and the parallel signal line (5), An MSB-LSB conversion circuit, characterized in that the MSB position and the LSB position in the n-bit data are replaced. 2. The parallel signal line (5) is a CPU (4)
The MSB-LSB conversion circuit according to claim 1, wherein the register (1) is connected to the bus.