JPH05218797A - Variable attenuator - Google Patents

Variable attenuator

Info

Publication number
JPH05218797A
JPH05218797A JP1687392A JP1687392A JPH05218797A JP H05218797 A JPH05218797 A JP H05218797A JP 1687392 A JP1687392 A JP 1687392A JP 1687392 A JP1687392 A JP 1687392A JP H05218797 A JPH05218797 A JP H05218797A
Authority
JP
Japan
Prior art keywords
signal
drain
voltage
effect transistor
variable attenuator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1687392A
Other languages
Japanese (ja)
Inventor
Shigeru Amano
天野茂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1687392A priority Critical patent/JPH05218797A/en
Publication of JPH05218797A publication Critical patent/JPH05218797A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To suppress deterioration in the distortion characteristic by providing an inductive bias line through which a signal controlling a drain voltage of a field effect transistor(TR) passes to the attenuator. CONSTITUTION:The attenuator is provided with a FET 3 inserted to a path between signal lines having a signal input terminal 1 receiving a high frequency signal and a signal output terminal 2 and a gate resistor 4 being a resistor with a high resistance through which a signal used to control a gate voltage of the FET 3 passes and with an inductive drain bias line 7 through which a signal used to control the drain voltage of the FET 3 passes. Then the high frequency signal is fed between a drain and a source of the FET 3. The distortion characteristic is not deteriorated by applying a DC voltage between the drain and the source to apply a high frequency voltage only at a straight line part of a drain voltage versus drain current curve.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電界効果トランジスタ
を用いた低歪可変減衰器に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low distortion variable attenuator using field effect transistors.

【0002】[0002]

【従来の技術】通常、電気・電子回路を用いて構成され
る通信システムでは、回線構成上のレベルダイヤ調整ま
た温度特性によるシステム内の信号レベルの変動の安定
化等を目的として、システム内に可変減衰器を備える。
可変抵抗素子としては一般的にはPINダイオードがよ
く知られている。これはPINダイオードに流れる電流
を変化させると高周波抵抗が変化する特性を利用したも
のであり、PINダイオードを用いた可変減衰器は歪特
性の劣化する入力レベルが高いので、有効な可変減衰器
である。
2. Description of the Related Art Generally, in a communication system constructed by using electric / electronic circuits, a system is provided in the system for the purpose of adjusting the level diagram in the line configuration and stabilizing the fluctuation of the signal level in the system due to temperature characteristics. A variable attenuator is provided.
A PIN diode is generally well known as the variable resistance element. This utilizes the characteristic that the high frequency resistance changes when the current flowing through the PIN diode is changed, and the variable attenuator using the PIN diode has a high input level at which the distortion characteristics deteriorate, so it is an effective variable attenuator. is there.

【0003】最近では半導体基板上に多くの回路素子を
集積化して高周波回路を構成するモノリシック集積回路
の開発が盛んであり、マイクロ波帯以上で動作する集積
回路を超高周波動作に敵したガリウムひ素等の半導体基
板上に構成する場合も多くある。これと同時にガリウム
ひ素等の半導体基板上に可変減衰器を構成する必要性も
生じてきているが、ガリウムひ素基板上にP形半導体を
作る技術は今だ未熟で、良い特性を持ったP形半導体は
得られておらず、よってPINダイオードの実現は難し
いのが実情である。そこで、可変抵抗素子として電界効
果トランジスタを用い、信号線に並列に接続する可変減
衰器が実現されている。これは電界効果トランジスタの
チャンネル抵抗をゲート電圧を制御することによって変
化させている。
Recently, development of a monolithic integrated circuit in which a large number of circuit elements are integrated on a semiconductor substrate to form a high frequency circuit has been actively pursued, and gallium arsenide is suitable for an ultra high frequency operation of an integrated circuit operating in a microwave band or higher. In many cases, it is formed on a semiconductor substrate such as. At the same time, it is necessary to construct a variable attenuator on a semiconductor substrate such as gallium arsenide, but the technology for making a P-type semiconductor on a gallium arsenide substrate is still immature, and a P-type semiconductor with good characteristics is available. Since no semiconductor has been obtained, it is difficult to realize a PIN diode. Therefore, a variable attenuator that uses a field effect transistor as a variable resistance element and is connected in parallel to a signal line has been realized. This changes the channel resistance of the field effect transistor by controlling the gate voltage.

【0004】[0004]

【発明が解決しようとする課題】このような電界効果ト
ランジスタを用いた従来の可変減衰器はドイレイン・ソ
ース間に高周波信号が流れるので、可変減衰器の歪特性
はドレイン・ソース間電圧対ドレイン・ソース電流特性
の直線性に依存するが、その特性は本質的に非直線性を
示し、PINダイオードを用いた可変減衰器の歪特性に
比べて電界効果トランジスタを用いた可変減衰器の歪特
性は著しく劣り、通信システム中で必要とされる水準の
歪特性を満足せず、実用化に至っていない。
In the conventional variable attenuator using such a field effect transistor, since a high frequency signal flows between the drain and source, the distortion characteristic of the variable attenuator has a drain-source voltage vs. drain-source voltage. Although it depends on the linearity of the source current characteristic, the characteristic is essentially non-linear, and the distortion characteristic of the variable attenuator using the field effect transistor is higher than that of the variable attenuator using the PIN diode. It is extremely inferior, does not satisfy the level of distortion characteristics required in the communication system, and has not been put to practical use.

【0005】本発明は、このような欠点を除去するもの
で、歪特性の劣化を抑制する手段をもつ可変減衰器を提
供することを目的とする。
An object of the present invention is to eliminate such drawbacks and to provide a variable attenuator having means for suppressing deterioration of distortion characteristics.

【0006】[0006]

【課題を解決するための手段】本発明は、高周波信号が
入力する端子および出力する端子をもつ信号線と共通電
位との間の経路に挿入された電界効果トランジスタと、
この電界効果トランジスタのゲート電圧を制御する信号
が通過する高抵抗値の抵抗とを備えた可変減衰器におい
て、上記電界効果トランジスタのドレイン電圧を制御す
る信号が通過するインダクティブなバイアス線を備えた
ことを特徴とする。
According to the present invention, a field-effect transistor inserted in a path between a signal line having a terminal for inputting a high-frequency signal and a terminal for outputting a high-frequency signal and a common potential,
A variable attenuator having a high resistance resistor through which a signal for controlling the gate voltage of the field effect transistor passes, and an inductive bias line through which a signal for controlling the drain voltage of the field effect transistor passes. Is characterized by.

【0007】ここで、ガリウムひ素半導体基板上に形成
されても良い。
Here, it may be formed on the gallium arsenide semiconductor substrate.

【0008】[0008]

【作用】信号の入出力端子間に並列接続された電界効果
トランジスタのドレイン電極のバイアス線を介してドレ
イン電圧を制御する。これにより、歪特性の劣化を抑え
る。
The drain voltage is controlled via the bias line of the drain electrode of the field effect transistor connected in parallel between the signal input / output terminals. This suppresses the deterioration of distortion characteristics.

【0009】[0009]

【実施例】以下、本発明の一実施例について図面を参照
して説明する。図1はこの実施例の構成図である。この
実施例は、図1に示すように、信号入力端子1と信号出
力端子2とをもち、直流阻止コンデンサ5および6が挿
入された信号線と、直流阻止コンデンサ5と直流阻止コ
ンデンサ6との間の信号線にそのドレイン電極が接続さ
れ、そのソース電極が共通電位に接続され、そのゲート
にゲート抵抗4を介してゲートバイアス端子12が接続
された電界効果トランジスタ3と、直流阻止コンデンサ
5と直流阻止コンデンサ6との間の信号線とドレインバ
イアス端子8とを接続するドレインバイアス線7とを備
える。すなわち、この実施例は、図1に示すように、高
周波信号が入力する信号入力端子1および出力する信号
出力端子2をもつ信号線と共通電位との間の経路に挿入
された電界効果トランジスタ3と、この電界効果トラン
ジスタ3のゲート電圧を制御する信号が通過する高抵抗
値の抵抗であるゲート抵抗4とを備え、さらに、本発明
の特徴とする手段として、電界効果トランジスタ3のド
レイン電圧を制御する信号が通過するインダクティブな
ドレインバイアス線7を備える。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of this embodiment. In this embodiment, as shown in FIG. 1, a signal line having a signal input terminal 1 and a signal output terminal 2, in which DC blocking capacitors 5 and 6 are inserted, a DC blocking capacitor 5 and a DC blocking capacitor 6 are provided. The drain electrode is connected to the signal line between them, the source electrode is connected to a common potential, and the gate is connected to the gate bias terminal 12 via the gate resistance 4, and the field effect transistor 3 and the DC blocking capacitor 5. The drain bias line 7 connects the signal line between the DC blocking capacitor 6 and the drain bias terminal 8. That is, in this embodiment, as shown in FIG. 1, the field effect transistor 3 inserted in the path between the signal line having the signal input terminal 1 for inputting the high frequency signal and the signal output terminal 2 for outputting and the common potential. And a gate resistor 4 which is a high resistance resistor through which a signal for controlling the gate voltage of the field effect transistor 3 passes. Further, as a feature of the present invention, the drain voltage of the field effect transistor 3 is An inductive drain bias line 7 through which a control signal passes is provided.

【0010】次に、この可変減衰器の動作を説明する。
この可変減衰器の可変抵抗素子として、電界効果トラン
ジスタ3のチャンネル抵抗をゲート電圧を制御すること
によって使用する。高周波信号は電界効果トランジスタ
3のドレイン・ソース間に加わる。図2はノーマリオン
形のNチャンネル電界効果トランジスタのドレイン電圧
対ドレイン電流曲線の例である。ドレイン・ソース間に
直流電圧を加えず高周波信号のみを加える場合に、ドレ
イン電圧が負の領域での非直線性がドレイン電圧が正の
領域での非直線性より小さなドレイン電圧でみられ、可
変減衰器の歪特性を悪化させる。そこでドレイン・ソー
ス間に直流電圧を加えることで、図2のドレイン電圧対
ドレイン電流曲線の直線部分のみで高周波電圧が加わる
ようにすれば歪特性は悪化しない。図3は、この可変減
衰器に一定の高周波信号を入力し、ドレイン電圧を変化
させたときの減衰量に対する高周波信号の所望波の出力
と三次歪成分の差の例を示す。ドレイン電圧を加えるこ
とで所望波と三次歪成分の差が最小となるときの減衰量
を変化させることが可能になり、必要な減衰量に対して
適当なドレイン電圧を加えることで歪特性の悪化を抑え
ることができる。
Next, the operation of this variable attenuator will be described.
As the variable resistance element of this variable attenuator, the channel resistance of the field effect transistor 3 is used by controlling the gate voltage. The high frequency signal is applied between the drain and source of the field effect transistor 3. FIG. 2 is an example of a drain voltage-drain current curve of a normally-on type N-channel field effect transistor. When only a high frequency signal is applied without applying a DC voltage between the drain and source, the non-linearity in the negative drain voltage region is observed at a smaller drain voltage than the non-linearity in the positive drain voltage region. It deteriorates the distortion characteristics of the attenuator. Therefore, if a high-frequency voltage is applied only to the linear portion of the drain voltage-drain current curve of FIG. 2 by applying a DC voltage between the drain and the source, the distortion characteristic will not deteriorate. FIG. 3 shows an example of the difference between the output of the desired wave of the high frequency signal and the third-order distortion component with respect to the attenuation amount when a constant high frequency signal is input to this variable attenuator and the drain voltage is changed. It is possible to change the amount of attenuation when the difference between the desired wave and the third-order distortion component is minimized by adding a drain voltage, and the distortion characteristics are deteriorated by adding an appropriate drain voltage to the required amount of attenuation. Can be suppressed.

【0011】[0011]

【発明の効果】本発明は、以上説明したように、電界効
果トランジスタのドレイン電圧を制御可能としたので、
必要な減衰量に対するドレイン電圧を適当に選ぶことに
よって歪の少ない減衰器を実現できる効果がある。ま
た、ガリウムひ素半導体上でも構成できるので、小形
化、コストダウンを可能にする効果がある。
As described above, according to the present invention, the drain voltage of the field effect transistor can be controlled.
There is an effect that an attenuator with less distortion can be realized by appropriately selecting the drain voltage with respect to the required attenuation amount. Further, since it can be formed on a gallium arsenide semiconductor, it has the effect of enabling miniaturization and cost reduction.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明実施例の構成を示すブロック構成図。FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

【図2】電界効果トランジスタのドレイン電圧対ドレイ
ン電流特性を示す図。
FIG. 2 is a diagram showing drain voltage-drain current characteristics of a field effect transistor.

【図3】信号入力一定時の減衰量に対する所望波と三次
歪成分出力との差を示す図。
FIG. 3 is a diagram showing a difference between a desired wave and an output of a third-order distortion component with respect to an attenuation amount when a signal input is constant.

【符号の説明】[Explanation of symbols]

1 信号入力端子 2 信号出力端子 3 電界効果トランジスタ 4 ゲート抵抗 5、6 直流阻止コンデンサ 7 ドレインバイアス線 8 ドレインバイアス端子 12 ゲートバイアス端子 1 signal input terminal 2 signal output terminal 3 field effect transistor 4 gate resistance 5, 6 DC blocking capacitor 7 drain bias line 8 drain bias terminal 12 gate bias terminal

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 高周波信号が入力する端子および出力す
る端子をもつ信号線と共通電位との間の経路に挿入され
た電界効果トランジスタと、この電界効果トランジスタ
のゲート電圧を制御する信号が通過する高抵抗値の抵抗
とを備えた可変減衰器において、 上記電界効果トランジスタのドレイン電圧を制御する信
号が通過するインダクティブなバイアス線を備えたこと
を特徴とする可変減衰器。
1. A field-effect transistor inserted in a path between a signal line having a terminal for inputting a high-frequency signal and a terminal for outputting a high-frequency signal and a common potential, and a signal for controlling a gate voltage of the field-effect transistor pass therethrough. A variable attenuator having a high resistance value, comprising an inductive bias line through which a signal for controlling a drain voltage of the field effect transistor passes.
【請求項2】 ガリウムひ素半導体基板上に形成される
請求項1記載の可変減衰器。
2. The variable attenuator according to claim 1, which is formed on a gallium arsenide semiconductor substrate.
JP1687392A 1992-01-31 1992-01-31 Variable attenuator Pending JPH05218797A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1687392A JPH05218797A (en) 1992-01-31 1992-01-31 Variable attenuator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1687392A JPH05218797A (en) 1992-01-31 1992-01-31 Variable attenuator

Publications (1)

Publication Number Publication Date
JPH05218797A true JPH05218797A (en) 1993-08-27

Family

ID=11928313

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1687392A Pending JPH05218797A (en) 1992-01-31 1992-01-31 Variable attenuator

Country Status (1)

Country Link
JP (1) JPH05218797A (en)

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