JPH05218391A - Quantum well wire and device with quantum well wire - Google Patents

Abstract

PURPOSE:To form a quantum well wire and a device including the quantum well wire easily without using an advanced fine-pattern manufacturing method or a process at an ultra-low temperature, by utilizing misfitted dislocation that is generated by a mismatch in lattices at a hetero-interface. CONSTITUTION:The substrate 10 is made of monocrystal (100) GaAs, and the surface of the substrate 10 is partly removed so that a rectangular hill with a short side of 0.5 to 5mum and a long side twice as large as the short side. After the surface of the hill is cleaned in an ultra-high vacuum, a molecular beam made of Ga and P is cast to the hill with the substrate at about 500 deg.C. Then, GaP monocrystal 11 of about 50nm in thickness is formed so that a plurality of misfit dislocations 12, which moderates stress caused by a difference in lattice constant at a GaP/GaAs hetero-interface, are spread over the wide area other than the hill. On the hill, since the hetero-interface area is limited, the dislocation density is decreased and only one line of misfit dislocation 12 is generated in the elongated direction of the rectangular hill.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an extremely high speed and low power consumption electronic element and a quantum wire required for forming the same, which can be formed with reproducibility by a particularly simple process and requires extremely low temperature. The present invention relates to an electronic device that can be formed without a problem.

[0002]

2. Description of the Related Art Conventional quantum wires are described, for example, in Japanese Journal of Applied Physics, Vol. 28 (1989), pages 2188-2192 (Japanese J).
ournalof Applied Physics, 28, (1989), 21
88-2192). in this case,
In order to obtain a quantum wire, first, an AlGaAs / GaAs structure is formed and a sheet-shaped two-dimensional electron gas is formed at the interface. Next, this structure is processed into a thin line, and the two-dimensional electron gas is confined in the thin line to obtain a quantum thin line. That is, as shown in FIG. 4, a resist layer (PMMA) is formed on a substrate in which AlGaAs is epitaxially grown on GaAs. A line is drawn using a thin electron beam (2.4 nm in diameter) and developed to form a narrow groove in the resist layer. A
1 is vapor-deposited, and Al on the resist is removed by the lift-off method. Ion beam etching is performed using the remaining Al thin line pattern as a mask to form AlGaAs / Ga.
The As structure is left in the shape of a narrow mesa. The two-dimensional electron gas in the form of a thin wire was formed by the above steps, and the quantum wire was obtained at a temperature of about 1.4K.

[0003]

In the prior art for forming quantum wires, a thin film was formed and, in addition, sophisticated microfabrication technology was used to limit the movement of electrons in the lateral direction of the film. For this reason, not only the reproducibility and mass productivity are poor, but also the effect as a quantum wire cannot be exhibited unless the temperature is extremely low because there is a limit to the fine processing.

[0004]

In the present invention, in order to eliminate the need for fine processing for forming quantum wires, misfit dislocations due to lattice mismatch at the hetero interface are utilized. That is, the number of misfit dislocations is controlled by limiting the width of the hetero interface to a width of about 1 μm to about 10 μm according to the lattice mismatch, and the already misfit dislocations are used as a main electric conduction region, so A quantum wire or an element using the same is obtained without using a fine processing method.

[0005]

When two kinds of strongly covalently bonded semiconductors or insulators having different lattice constants are joined, misfit dislocations are likely to occur at their hetero interfaces. Usually, many dislocation lines having a specific crystal orientation can be formed at the interface, but if the joining region is limited to a narrow range, the number of dislocation lines can be controlled to one or several due to the reduction of dislocation generation sources and the stress relaxation effect. it can. On the other hand, focusing on the electronic state near the misfit dislocation, an unpaired electron pair is formed along the dislocation line, and as shown in FIG. Is formed. The electrons in this level are characterized in that they are allowed to move continuously only in the direction of the dislocation lines, while the movement in the direction perpendicular to the dislocation lines is restricted and only discrete energy values are allowed. If the condition that electrons and holes are not accumulated in the already existing hetero interface is selected by selecting the temperature and the potential, the energy rank 15 along the misfit dislocation can be used as the main electric conduction means. By combining these two actions, a so-called quantum wire is obtained in which the movement of charged particles is restricted in the film thickness direction and the direction perpendicular to the dislocation line, and is allowed only in the direction of the dislocation line.

Since the width of the thin wire obtained by this method is theoretically extremely narrow on the order of the atomic spacing, there is an advantage that it becomes a quantum thin wire even if it is not brought to an extremely low temperature such as below the liquid helium temperature. Furthermore, since the dimensions and electronic states of the thin wires are determined by the crystal structure of the material, there is an advantage that they can be formed with extremely good reproducibility.

[0007]

EXAMPLE 1 FIG. 1 shows one example of the present invention. A (100) plane of single crystal GaAs is used as the substrate 10, and the surface is partially removed by etching to form a rectangular hill having a width of 2 μm and a length of 10 μm.
This substrate is placed in an ultrahigh vacuum to clean the surface, the substrate temperature is kept at 500 ° C., and Ga and P molecular beams are irradiated.
A GaP single crystal 11 having a thickness of 50 nm is formed. As a result, GaP / Ga is spread over a wide area other than the hill.
A large number of misfit dislocations 12 for relaxing the stress due to the difference in lattice constant are generated at the As hetero interface. On the other hand, by limiting the area of the hetero interface on the hill, the dislocation density decreases, and only one misfit dislocation 12 is generated in the longitudinal direction of the rectangle.

By reducing the impurity concentration of the GaP film and the GaAs substrate, the electric conduction due to the energy level 15 formed along the misfit dislocations becomes the main constituent even at the temperature of liquid nitrogen, and the quantum wire can be obtained. Therefore, the present embodiment has an advantage that a quantum wire can be obtained with a reproducibility of about 1 μm with good reproducibility without using a special fine processing technique, and an extremely low temperature is not required.

Here, GaAs is used as an example of the material.
Although GaP and GaP were used, the same effect can be obtained as long as the material is a single crystal and has a Fermi level in the forbidden band and generates misfit dislocations due to a difference in lattice constant. Although a rectangular hill formed on the substrate was used here to control the number of misfit dislocations, other than that, for example, an amorphous high resistance thin film is formed on the substrate and a rectangular hill is formed on this film. Even if a hole is formed and a crystal grows in the hole, the region where the crystal grows on the substrate is limited, so that the same effect is obtained. Although the number of misfit dislocations is set to one here, even if the shorter side of the rectangular hill is made longer and the number of dislocation lines is increased to about 5, a quantum wire with uniform characteristics can be obtained with good reproducibility. Has the same effect as one quantum wire.

<Second Embodiment> FIG. 2 shows a first embodiment of another embodiment of the present invention.
Shows one. Using the quantum wire 20 shown in Example 1, Si ion implantation and activation annealing are performed on both ends of the quantum wire 20.
A high-concentration impurity region 21 for a source and a drain which serves as a current injection / extraction means is formed. An insulating film 25 is formed on this, and only the source and drain regions are removed by etching. Then, the lift-off method is used to process the Au electrode to form the source 22, drain 23 and gate 24 electrodes.

A constant voltage is applied between the source and drain,
When the voltage applied to the gate electrode is changed, (b) in FIG.
The drain current oscillates as shown in FIG. this is,
In the portion directly under the gate electrode, the relative potential between the discrete energy level and the Fermi level due to the misfit dislocation changes with the gate voltage, and a large current increase occurs only when the energy level and the Fermi level match. Because it can be seen.

As a result, an element having a region having a large amplification factor and a plurality of regions having negative resistance can be obtained. Since this element uses a quantum wire, which is a material whose electrical properties change with extremely small energy, it has the advantage of extremely low power consumption and extremely high speed operation. Further, since a plurality of peaks and troughs of current appear, there is an advantage that it can be applied to a multi-valued logic circuit.

<Third Embodiment> A third embodiment of the present invention will be described with reference to FIG. As the substrate 31, a Si single crystal having a (100) -oriented surface is used. Thermally oxidize the substrate to form Si on the surface.
The O ₂ film 32 is formed. Width 2.5 to 3
The Si substrate 31 is exposed by etching into a rectangular shape having a length of 5 μm or more (FIG. 3A). This surface is put in an ultra-high vacuum to clean the surface, and Si and Ge are then added to 4: 1.
To form a film having a thickness of 150 nm (FIG. 3B). As a result, the single crystal 33 of the SiGe solid solution grows on Si, and one dislocation line is generated at the interface with the substrate along the longitudinal direction of the rectangle. On the other hand, a polycrystalline film 34 is formed on the SiO ₂ film. This polycrystalline film is removed by etching, leaving only the rectangular single crystal SiGe film 33 (FIG. 3 (c)).

After that, a SiO ₂ film 32 is formed by CVD, and only the ends of the dislocation lines are removed by etching. A high concentration impurity region 35 is formed in this region by P ion implantation and activation annealing ((d) of FIG. 3). Finally, an Al electrode is formed, and the source 37 and drain 38 electrodes are formed in the high-concentration impurity regions at both ends of the dislocation line.
Further, the gate electrode 3 is formed between the both and in the region above the dislocation line.
6 is obtained ((e) of FIG. 3).

The element thus obtained functions as a quantum wire element at a relatively high temperature without requiring an extremely low temperature as in Example 2, and has good reproducibility without using a special fine processing technique. Not only does it have the advantage that it can be obtained, but there is also the advantage that it can be highly integrated because it can be formed using ordinary Si-LSI fabrication techniques.

In this embodiment, S is used as the material of the group 4 element.
Although i and Si80% -Ge20% alloy were used, the same effect can be obtained by using other compositions and composition ratios by selecting the width of the crystal growth region according to the lattice mismatch.

[0017]

According to the present invention, there is an advantage that a quantum wire which can be formed with good reproducibility without a special microfabrication technique and which does not require cryogenic temperature can be obtained. In addition, a quantum wire device that is easy to form, does not require cryogenic temperature during operation, has extremely low power consumption, and operates at high speed can be obtained. further,
It is possible to obtain an integrated circuit which is easy to form, does not require cryogenic temperature during operation, and has extremely low power consumption and operates at high speed.

[Brief description of drawings]

FIG. 1A is a cross-sectional view, FIG. 1B is a plan view, and FIG. 1C is a band explanatory view in the structure of Example 1 of the present invention.

FIG. 2A is a cross-sectional structural view and FIG. 2B is an operating characteristic view of a quantum wire device according to a second embodiment of the present invention.

FIG. 3 is a plan view showing a manufacturing process of a quantum wire device according to a third embodiment of the present invention.

FIG. 4 is a sectional view of a conventional quantum wire producing process.

[Explanation of symbols]

10 ... GaAs (100) substrate, 11 ... GaP single crystal,
12 ... Misfit dislocation line, 13 ... Forbidden band of substrate, 14
... Forbidden band of growth film, 15 ... Energy level formed along misfit dislocations.

Front page continuation (72) Inventor Kiyokazu Nakagawa 1-280 Higashi Koigokubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (3)

[Claims] 1. A plurality of types of semiconductor or insulator materials are bonded together, and the first material and the second material are 0.2% to 5%.
In a system with a degree of lattice mismatch, the region where the first material and the second material are joined has a short side of 0.5 μm to 5 μm.
m, the long side is limited to a rectangle having a length more than twice the length, or an elongated shape similar to this, so that 1 to 5 misfit dislocations are present at the interface between both materials, and the joining region of both materials A quantum wire characterized in that the Fermi level is inside the forbidden band of both materials depending on the potential from the outside even if impurities are not doped in the vicinity or there is it. 2. An element using the quantum wire according to claim 1, wherein a pair of current injection / extraction means is provided, and a control electrode for applying an electric field to the quantum wire is provided therebetween. 3. The material according to claim 2, wherein Si or G is used as a material.
An element using a solid solution composed of e or at least two kinds of Group 4 elements such as Si, Ge, C and Sn.