JP3484005B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a heterojunction between a non-strained silicon germanium film (strained silicon germanium film) and a strained silicon film (non-strained silicon film).

[0002]

2. Description of the Related Art When semiconductors having different band gaps are joined to form a heterojunction, various unique properties which cannot be obtained by a semiconductor material having a homogeneous composition can be obtained.

In particular, the level of a quantum structure in which a thin film layer made of a material having a small band gap is sandwiched between two thin film layers made of a material having a larger band gap, that is, quantization that can be performed in a quantum well layer of a quantum well structure. Various elements can be formed by utilizing the above levels.

When forming a heterojunction having a thin width in only one of the three-dimensional directions, such as a quantum well structure, it is possible to easily form it by the current thin film growth technique. It is difficult to easily form a structure confined by a thin heterojunction also in the second and third directions, that is, a fine quantum wire structure and a quantum box structure.

Quantum confinement structures such as the quantum well structure have been conventionally formed mainly of compound semiconductor materials represented by GaAs. In the case of a compound semiconductor, there is an advantage that the lattice constant of a crystal and the band gap can be independently designed with a wide degree of freedom by combining the elements constituting the semiconductor.

On the other hand, active research has also been conducted on the production of quantum confinement structures such as quantum wires and quantum boxes made of silicon-based materials that can be used with the fine processing technology developed with the progress of the ULSI process.

For example, in a silicon-based heteromaterial, it is possible to form a quantum well structure by a thin film growth method using a combination of silicon and germanium mixed crystals in addition to silicon. It is also possible to form a quantum well structure with germanium alone.

However, although there have been some attempts to create a quantum confinement structure using a heterojunction of silicon and silicon germanium, there is a problem that it is difficult to form a fine quantum confinement structure.

[0009]

As described above, the quantum confinement structure of silicon-based heteromaterial has been used in the conventional ULS.
It is expected because it can follow the microfabrication technology of the I process, but it was difficult to form a fine quantum confinement structure.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a heterojunction structure capable of easily forming a fine quantum confinement structure by using a heterojunction of silicon and silicon germanium. It is to provide a semiconductor device having the same.

[0011]

[Summary] A semiconductor device according to the present invention (claim 1) is made of silicon oxide.
And a quantum wire structure formed on the silicon oxide film.
And a field effect transistor having
Field effect transistor is formed on the silicon oxide film.
And non-strained sill with striped regions
And a non-strained silicon film on the stripe shape.
The gate oxide film formed on the processed region and the
The non-strained silicone on both sides of the short side of the region processed into a lip shape
Is formed on the exposed surface of
Unstrained silicon germanium film and the unstrained silicon
Formed on the germanium film and the gate oxide film
On the strained silicon film and the unstrained silicon germanium film
A source electrode provided through the strained silicon film and
Drain electrode and the stripe of the unstrained silicon film
Electrode for applying a voltage to the region processed into a shape
It is characterized by comprising: The present invention also relates to
According to another aspect of the present invention, there is provided a semiconductor device comprising:
An electrode formed on a silicon oxide film and having a quantum wire structure.
A field effect transistor, and the field effect transistor
The transistor is formed on the silicon oxide film and
First unstrained silicon having a region processed into a lip shape
A film and a stripe of the first unstrained silicon film.
A gate oxide film formed on the processed region,
The first non-sides on both sides of the short side of the region processed into a tripe shape.
The source and drain are formed on the exposed surface of the strained silicon film.
A second non-strained silicon film as an insulating film and the second non-strained silicon film.
The strain film formed on the silicon film and the gate oxide film is
Recon germanium film and on the second non-strained silicon film
On the strained silicon germanium film
A source electrode and a drain electrode, and the first non-strain silicon
Applying voltage to the striped area of the film
And a gate electrode for
It

[0012]

[0013]

[0014]

[0015]

[0016]

[0017]

[0018]

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[0020]

[0021]

[0022]

[0023]

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments (embodiments) of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a sectional view showing a quantum wire according to a first embodiment of the present invention.

This quantum wire is a stripe-shaped silicon oxide film (SiO ₂ ) formed on the silicon substrate 11 with a width (length in the x direction) of 50 nm and a length (direction perpendicular to the x and y directions) of 500 nm. Film 12 and the silicon substrate 11 so as to avoid the silicon oxide film 12 by the selective growth method.
N-type silicon film 13 having a facet thickness (y-direction length) of 100 nm selectively formed on the exposed surface of
A silicon germanium film (Ge composition 20%) 14 having a thickness of 10 nm formed on the entire surfaces of the n-type silicon film 13 and the silicon oxide film 12 by the non-selective growth method, and the entire surface of the silicon germanium film 14 by the non-selective growth. It is composed of the formed undoped silicon film 15 having a thickness of 10 nm.

Since the silicon germanium film 14 is thinner than the silicon film 13, it is formed in a strained state (hereinafter referred to as a strained silicon germanium film 14). As a result, most of the difference in the forbidden band width between Si and SiGe is distributed to the valence band, so that holes can be confined in the strained silicon germanium film 14 in the x direction. Further, the thin silicon film 15 can confine holes in the strained silicon germanium film 14 in the y direction. Therefore, a quantum wire confining holes in the x and y directions is realized.

In the quantum wire of the present embodiment, most of the strained silicon germanium film 14 is the silicon films 13 and 1.
Although the structure is surrounded by 5, only a part (fine region) is in direct contact with the silicon oxide film 12.

That is, a MOS structure is formed in which the silicon substrate 11 is used as a gate electrode, the silicon oxide film 12 is used as a gate oxide film, and the strained silicon germanium film 14 is used as a semiconductor substrate.

Therefore, by applying an appropriate electric field to the silicon substrate 11, holes can be effectively trapped at the interface between the silicon oxide film 12 and the strained silicon germanium film 14.

Therefore, according to the quantum wire of the present embodiment, a very narrow quantum wire that can surely confine holes in a stripe-shaped fine region determined by the processing limit of the silicon oxide film 12 can be easily formed. It will be realized. (Second Embodiment) FIG. 2 is a plan view of a field effect transistor (FET) according to a second embodiment of the present invention.
Further, FIGS. 3 and 4 respectively show AA of the FET of FIG.
It is a ′ sectional view and a BB ′ sectional view. The parts corresponding to the quantum wires in FIG. 1 are designated by the same reference numerals as those in FIG.

The FET of this embodiment uses the quantum wire of the first embodiment as a channel. An example of the method of manufacturing the FET of this embodiment will be described below. First, the gate oxide film 22 is formed on the surface of the low resistance p-type silicon substrate 21.
Forming a thermal oxide film.

Next, an n-type dopant (for example, arsenic) is ion-implanted into the surface of the p-type silicon substrate 21 through the thermal oxide film to form n-type regions 23 and 24 which define channel regions. A narrow striped region sandwiched between these n-type regions 23 and 24 becomes a channel region.

Next, the thermal oxide film other than the FET formation region is removed. As a result, like the pattern shown in FIG.
The thermal oxide film as the gate oxide film 22 remains. At this time, as shown in FIG. 2, since the thermal oxide film on the n-type regions 23 and 24 is removed, the n-type silicon region is exposed.

Next, an n-type silicon film 13 similar to that of the first embodiment is selectively formed on the exposed surface of the silicon region by the selective growth method, and then the whole surface of the first embodiment is formed by the non-selective growth method. A similar strained silicon germanium film (hereinafter referred to as a strained silicon germanium film) 14 and a silicon film 15 are sequentially formed.

Next, as shown in FIG. 4, a source electrode 25 and a drain electrode 26 are formed on the silicon film 15, and a gate electrode 27 is formed on the p-type silicon substrate 21 on the source electrode 25 side.
To form. In the case of this embodiment, the gate electrode 27 is formed in a region different from the channel region. That is, the gate voltage applied to the gate electrode 27 is applied to the channel region via the p-type silicon substrate 21.

5 (a) and 5 (b) are band diagrams in the XX 'and YY' cross sections of the FET of FIG. 3, respectively. In the figure, the solid line shows the band diagram when the gate voltage is not applied, and the broken line shows the band diagram when the gate voltage is applied. The gate voltage is a negative voltage.

When a negative voltage is applied to the gate electrode 27, n
Since holes are accumulated at the interface between the type silicon film 13 and the strained silicon germanium film 14 to form a channel,
The source and drain are electrically connected, and the element is turned on. At this time, since the depletion layer extends to the n-type regions 23 and 24, it is expected that the hole confinement region will be narrowed.

As a result, the narrow quantum wire can be used as a channel also in the first embodiment, and carrier scattering can be effectively prevented. Therefore, it becomes possible to realize an FET having a very high operating speed. (Third Embodiment) FIG. 6 is a sectional view showing a quantum wire according to a third embodiment of the present invention.

The quantum wires of this embodiment are the silicon substrate 3
Stripe-shaped silicon oxide film 32 formed on 1
A first silicon germanium film (Ge composition 35%) 33 having a facet thickness and selectively formed on the exposed surface of the silicon substrate 31 by a selective growth method so as to avoid the silicon oxide film 32; A strained silicon film 34 having a thickness of 5 nm and a second silicon germanium film 3 having a thickness of 15 nm which are sequentially formed on the entire surfaces of the silicon oxide film 32 and the silicon germanium film 33 by the non-selective growth method.
5, and a silicon film 36 having a thickness of 5 nm.

Here, the strain of the strained silicon film 34, which is the silicon film formed on the silicon germanium film 33, occurs as follows. Silicon germanium film 33
Has a lattice relaxation because its thickness is thicker than the critical thickness. Therefore, the silicon film formed on the silicon germanium film 33 is subjected to tensile stress by the silicon germanium film 33 to generate strain.

The quantum wire of the present embodiment differs from that of the first embodiment in that a quantum well in which electrons are confined is formed at the interface between the silicon germanium film 33 and the strained silicon film 34. In this embodiment, the same effect as that of the first embodiment can be obtained. Further, even if the quantum thin wire of the present embodiment is used, an FET can be formed as in the second embodiment. (Fourth Embodiment) FIGS. 7A to 7C are process sectional views showing a manufacturing process of a quantum wire according to a fourth embodiment of the present invention.

First, an SOI substrate as shown in FIG. 7A is prepared. That is, a thickness of 1 on the silicon support plate 41.
An SOI substrate having a structure in which a silicon oxide film 42 having a thickness of 100 μm and a silicon film 43 having a thickness of 100 μm are sequentially provided is prepared.
The main surface of the silicon film 43 is the (100) surface.

Next, as shown in FIG. 7B, the silicon film 43 is etched into a stripe shape having a long side of 100 nm and a short side of 10 nm. At this time, the thickness of the stripe-shaped silicon film 43 becomes 5 nm, and the silicon oxide film 42 is formed on the substrate surface other than the stripe-shaped silicon film 43.
To be exposed.

Next, as shown in FIG. 7C, a 100-nm-thick silicon germanium film (Ge composition 30%) 44 is selectively formed on the silicon film 43 by the selective growth method, and then the selective growth method is used. A strained silicon film 45 having a thickness of 10 nm is selectively formed on the silicon germanium film 44.

Here, since the silicon film 43 is thin, the silicon germanium film 44 grown thereon easily causes lattice relaxation. As a result, the strained silicon film 45 on the silicon germanium film 44 is in a state in which strain due to tensile stress is applied.

In the heterojunction of strained Si and SiGe, S
The conduction band of iGe has higher energy than that of strained Si. Therefore, the electrons are accumulated on the strained silicon film 45 side. Here, conventionally, a heterojunction of Si and SiGe is formed as follows.

First, a silicon oxide film is formed on the entire surface of a silicon film (corresponding to the silicon film 43), fine stripe-shaped openings are formed in the silicon oxide film, and then the surface of the silicon film is exposed.

Thereafter, a silicon germanium film (corresponding to the silicon germanium film 44) and a silicon film (strained silicon film 45) are formed on the exposed surface of the silicon film by the selective growth method.
Is formed), and a heterojunction of Si and SiGe is obtained.

In the case of such a conventional method, the thickness of the silicon germanium film is several hundreds in order to cause lattice relaxation in the silicon germanium film and reduce the dislocation density.
It is necessary that the thickness is not less than nm.

When such a thick silicon germanium film is formed, the silicon germanium film is also formed on the silicon oxide film, so that it becomes impossible to selectively form the silicon germanium film on the exposed surface of the silicon film. There is a problem that it becomes difficult to form the quantum wires.

Further, according to the conventional method, the selective growth is possible.
When the thickness is 0 nm or less, the silicon germanium film does not cause lattice relaxation, so that a quantum well for confining electrons cannot be formed.

On the other hand, in the case of this embodiment, the silicon film 4 is used.
3, each of the silicon germanium film 44 and the strained silicon film 45 has a unique surface called a facet formed as the growth progresses.

As a result, the cross-sectional shape of each film 43, 44, 45 becomes trapezoidal as shown in FIG. 7C, and the width of the interface between the silicon germanium film 44 and the strained silicon film 45 is
The width is narrower than the width of the interface between the silicon film 43 and the silicon germanium film 44.

Therefore, according to this embodiment, a quantum wire thinner than the quantum wire determined by the limit of the processing size can be obtained. (Fifth Embodiment) FIG. 8 is a perspective view of a field effect transistor (FET) according to a fifth embodiment of the present invention.
The parts corresponding to the quantum wires in FIG. 7 are designated by the same reference numerals as those in FIG.

The FET of this embodiment uses the quantum wire of the fourth embodiment as a channel. An example of the method of manufacturing the FET of this embodiment will be described below. First, similarly to the fourth embodiment, the stripe-shaped silicon film 43 is formed.
After a silicon germanium film 44 and a strained silicon film 45 are sequentially formed on the strained silicon film 45, an n-type silicon germanium film 46 having a thickness of 15 nm and a silicon film 47 having a thickness of 8 nm are sequentially and selectively formed on the strained silicon film 45 by a selective growth method. Form.

As a result, the silicon germanium film 44,
Strained silicon film 45 and n-type silicon germanium film 4
A quantum well structure of 6 is obtained. In this case, the strained silicon film 45 becomes a quantum well layer, and a two-dimensional electron gas is formed by the electrons supplied from the n-type silicon germanium film 46. Electrons are confined in the film thickness direction by such a quantum well structure, but are also confined in the width direction by the quantum wire structure as in the fourth embodiment.

Next, the silicon film 47 is oxidized to form a gate oxide film (not shown), and then a gate electrode 48 made of polycrystalline silicon is formed. Finally, a source region and a drain region (not shown) are formed by ion implantation, and a source electrode 49 and a drain electrode 50 are formed to complete the process.

Although the gate electrode 48 is formed only on the upper surface of the quantum wire in this embodiment, a gate oxide film is formed on the upper surface and the side surface of the quantum wire, and the gate electrode 48 is formed on the upper surface and the side surface of the quantum wire. May be formed. This makes it possible to further enhance the electron confinement effect of the quantum wire.

In the FET of this embodiment, unlike the second embodiment, the two-dimensional electron gas already exists in the quantum well structure in the state where no voltage is applied to the gate electrode 48, and the source / drain is formed. It is in a conducting state during the period.
That is, the FET of this embodiment is a normally-on type. Therefore, the element can be turned off by applying a voltage to the gate electrode 48.

By using an undoped silicon germanium film in place of the n-type silicon germanium film 46, it is possible to change to a normally-off type FET as in the second embodiment. In this case, the source region and the drain region must be close to the gate electrode 48 so that the channel can be easily formed. (Sixth Embodiment) FIG. 9 is a perspective view of a field effect transistor (FET) according to a sixth embodiment of the present invention.
The parts corresponding to the quantum wires in FIG. 8 are designated by the same reference numerals as those in FIG.

This FET is formed by using a plurality of quantum wires shown in FIG. That is, the three quantum wires 51
Are arranged in parallel, and a gate electrode 48, a source electrode 49, and a drain electrode 50 common to the quantum wires 51 are provided. In the figure, the structure of the quantum wire 51 is omitted. Further, in the figure, reference numeral 52 indicates an insulating film for insulating the quantum wires 51 from each other.

Since all of the quantum wires described so far have a high mobility but a narrow width, the total amount of electrons when used in a FET is insufficient, and it may be difficult to obtain a desired transconductance. is there.

However, by coupling a plurality of quantum wires 51 as in this embodiment, an FET having a desired transconductance can be easily realized. Although the quantum wires of FIG. 8 are used in this embodiment, the same effect can be obtained by using other quantum wires. (Seventh Embodiment) FIGS. 10A to 10C are process sectional views showing a method for forming a field effect transistor (FET) according to a seventh embodiment of the present invention.

This embodiment is a combination of selective growth and non-selective growth techniques of silicon and silicon germanium,
Is an example of forming. First, as shown in FIG. 10A, a thickness of 100 n is formed on a silicon oxide film 61 having a thickness of 1 μm.
SO formed by forming a low-resistance p-type silicon film 62 of m
Prepare an I substrate.

Next, as shown in FIG. 10B, a thermal oxide silicon film 63 having a thickness of 5 nm is formed as a gate oxide film on the surface of the p-type silicon film 62 by the thermal oxidation method. The width of the film 63 and the p-type silicon film 62 is 15
Processed in a stripe shape of nm × 100 nm in length. The stripe-shaped p-type silicon film 62 is used as a gate. The width of the p-type silicon film 62 is 100 nm.
The following is preferable.

At this time, the silicon oxide film 61 is left with the p-type silicon film 62 in the non-striped region left by about 5 nm.
Not be exposed. The p-type silicon film 62 is not directly etched with an etching solution or the like, but the p-type silicon film 62 of the portion to be removed is processed, for example.
After selective oxidation, the oxidized portion may be removed by etching with an HF solution or the like.

Next, as shown in FIG. 10C, a thickness of 200 n is formed on the exposed surface of the p-type silicon film 62 by the selective growth method.
m n-type silicon germanium film (Ge composition 25%) 6
4 are selectively formed. n-type silicon germanium film 6
4 includes 1 × 10 ¹⁹ m ⁻³ of n-type dopant (eg, As)
Has been added. The thickness of the n-type silicon germanium film 64 is preferably 100 to 300 nm.

Since the n-type silicon germanium film 64 is grown thick, the n-type silicon germanium film 64 is lattice-relaxed. In addition, the n-type silicon germanium film 64
Is protruded from the exposed surface of the p-type silicon film 62, which remains thin, and is also formed on the thermal silicon oxide film 63. As a result, the exposed surface of the thermally oxidized silicon film 63 is smaller than that before the growth of the n-type silicon germanium film 64 is started.

Next, as shown in FIG. 10D, an undoped strained silicon film 65 having a thickness of 10 nm is formed on the entire surfaces of the thermal silicon oxide film 63 and the n-type silicon germanium film 64 by the non-selective growth method. The quantum wire is completed. The strained silicon film 65 has the same thickness on the thermal silicon oxide film 63 and the n-type silicon germanium film 64.

Since the width of the thermally oxidized silicon film 63 is narrow, the silicon film 65 on the thermally oxidized silicon film 63 should be made of single crystal silicon by lateral solid phase growth from the n-type silicon germanium film 64. Is also possible.

In the case of this embodiment, the n-type silicon germanium film 64 is lattice-relaxed and the strained silicon film 65 is formed, so that a two-dimensional electron gas is formed on the strained silicon film 65 side.

Next, as shown in FIG. 10E, an n-type dopant is ion-implanted into the n-type silicon germanium film 64 to form high-concentration n-type contact regions 66 and 67. In the case of the quantum wire of the present embodiment, the source and drain are formed on both sides of the quantum wire, not on both ends. Therefore, the channel length can be made very small.

Finally, as shown in FIG. 7E, the source electrode 68, is formed on the n-type contact regions 66, 67, respectively.
A gate electrode (not shown) for forming the drain electrode 69 and applying a voltage to the stripe-shaped p-type silicon film 62.
To complete.

In the FET of this embodiment, the strained silicon film 65 having a high electron mobility can be used as the channel region, and the parasitic capacitance can be reduced by forming the device on the SOI substrate, so that a very high speed operation can be achieved. It will be possible.

Further, the problem of hole generation due to impact ionization, which is a particular problem when using an SOI substrate, is as follows.
In the case of the present embodiment, the source / drain region (n-type silicon germanium film 64) has a smaller bandgap than the channel region (strained silicon film 65), which can be solved.

Further, during the selective growth of the n-type silicon germanium film 64, the n-type silicon germanium film 64 bites on the thermally oxidized silicon film 63, so that a gate length narrower than the precision of lithography is effectively achieved in a self-aligned manner. it can.

In this FET, by applying a positive voltage to the gate electrode, the inversion layer 3 is formed on the stripe-shaped p-type silicon film 62 on the thermally-oxidized silicon film 63, electrons are stored, and the source-drain region is stored. Becomes conductive.

Although the n-type contact regions 66 and 67 are not close to the stripe-shaped p-type silicon film 62,
The electrons supplied from the n-type silicon germanium film 64 are accumulated in the Si film strained silicon film 65 above the electrons. Therefore, the resistance between the n-type contact regions 66 and 67 and the stripe-shaped p-type silicon film 62 becomes low, and stable FET operation becomes possible. Therefore, it is not necessary to increase the accuracy of source / drain formation in addition to the accuracy of gate processing as in the conventional case.

In this embodiment, a structure is adopted in which electrons are stored in the strained silicon film as in the case of the third embodiment, but holes are stored in the strained silicon germanium film as in the case of the first embodiment. It is also possible to form the FET with a shape. (Eighth Embodiment) FIG. 11 is a sectional view of a field effect transistor (FET) according to an eighth embodiment of the present invention.

An example of the method of manufacturing the FET of this embodiment will be described below. First, a 10-nm-thick thermally-oxidized silicon film 72 is formed on the surface of a low-resistance p-type silicon substrate 71.

Next, a width of 80 n is formed on the thermal silicon oxide film 72.
A stripe-shaped opening of m × 1200 nm is formed to expose the surface of the p-type silicon substrate 71. However, before the opening is formed, the p-type silicon substrate 7 below the thermally oxidized silicon film 72 other than the region where the opening is formed.
An n-type dopant is ion-implanted into the surface of No. 1 to form a gated n-type region 73.

Next, p-type silicon substrate 71 is formed by selective growth.
A strained silicon germanium film 74 having a thickness of 15 nm is selectively formed on the exposed surface of. Instead of directly forming the strained silicon germanium film 74, the strained silicon germanium film 74 may be formed after growing a thin p-type silicon film on the exposed surface of the p-type silicon substrate 71.

Next, the entire surface is made to have a thickness of 50 n by the non-selective growth method.
A silicon film 75 of m is formed. In this step, quantum wires are completed on the stripe-shaped openings. Then, a source electrode and a drain electrode are formed on both ends of this quantum wire, and n
FE is formed by forming a gate electrode for applying a voltage to the mold region 73.
T is completed.

In the FET of this embodiment, since the quantum wires are formed using the strained silicon germanium film 74,
Most of the difference between the forbidden band widths of Si and SiGe is distributed to the valence band, so that the holes supplied from the p-type silicon substrate 71 are stored as a two-dimensional hole gas on the strained silicon germanium film 74 side.

When a positive voltage is applied to the gate electrode in this state, the depletion layer extends from the n-type region 73 toward the strained silicon germanium film 74 in the stripe-shaped opening.
The confinement effect of the quantum wire is increased. When the voltage applied to the gate electrode is increased, the strained silicon germanium film 74
The number of holes supplied to is reduced, and the source and drain become non-conductive. (Ninth Embodiment) FIG. 12 is a sectional view of a field effect transistor (FET) according to a ninth embodiment of the present invention.

The FET of this embodiment is an FET of the opposite conductivity type to that of the eighth embodiment formed by using the SOI substrate.
An example of the method of manufacturing the FET of this embodiment will be described below. First, an SOI substrate in which a silicon film 81 having a thickness of 5 nm is formed on the silicon oxide film 80 is prepared.

Next, the entire surface of the silicon film 81 has a thickness of 300 n.
After forming the silicon germanium film 82 of m (Ge composition 25%) 82, a silicon film 83 having a thickness of 20 nm is formed on the entire surface of the silicon germanium film 82.

Next, the surface 10 nm of the silicon film 83 (Si
The crystal silicon) is thermally oxidized to form a thermally oxidized silicon film 84. The thermal silicon oxide film 84 is thicker than the silicon film 83 before being oxidized.

Next, a 200 nm-thick SiO ₂ film, that is, a BSG film (not shown) added with a high concentration of boron (B) is formed on the thermally oxidized silicon film 84, and then this BSG film is formed.
Film, thermal silicon oxide film 84, width 50 nm × length 1000
An opening 85 having a stripe shape of nm is formed.

Next, after annealing at a high temperature, boron in the BSG film is diffused into the silicon germanium film 82 and the silicon film 81 to form a p-type region 86 as a gate.
The BSG film is removed.

Next, the entire surface is made to a thickness of 30 n by the non-selective growth method.
m n-type silicon germanium film (Ge composition 25%) 8
7 is formed, and subsequently, a silicon film 88 having a thickness of 10 nm is formed on the entire surface by a non-selective growth method.

Here, the silicon germanium films 82, 8
Since 7 is thick and the silicon film 83 is thin, the silicon germanium films 82 and 87 relax the lattice. Therefore, the silicon film 83 is formed in a strained state (hereinafter referred to as a strained silicon film 83). As a result, most of the difference in the forbidden band width between Si and SiGe is distributed to the valence band.

Therefore, as in the present embodiment, the structure in which the strained silicon film 83 having a narrow width on the opening 85 is surrounded by the silicon germanium film 82 and the n-type silicon germanium 87 is supplied from the n-type silicon germanium 87. It becomes a quantum wire that stores electrons as a two-dimensional electron gas on the strained silicon film 83 side.

Finally, similarly to the second embodiment, a source electrode and a drain electrode (not shown) are formed at both ends of the quantum wire, and a gate electrode (not shown) for applying a voltage to the p-type region 86. Are formed to complete the FET using the quantum wires.

Also in this embodiment, as in the ninth embodiment,
When a voltage is applied to the gate electrode, the depletion layer extends from the p region 86 toward the strained silicon film 83 in the stripe-shaped opening 85, so that the quantum wire confinement effect is enhanced. Then, when the voltage applied to the gate electrode is increased, the electrons supplied to the strained silicon film 83 are decreased, and the source and drain are brought out of conduction.

Note that, similarly to the seventh embodiment, the source electrode and the drain electrode may be formed on both sides of the quantum wire.
The present invention is not limited to the above embodiment. For example, in the above embodiment, FE is used as a specific element.
Although the case of T has been described, the present invention can be applied to other elements. In addition, within the scope of the present invention,
Various modifications can be implemented.

[0097]

As described above, according to the present invention, it is possible to realize a semiconductor device having a heterojunction structure in which a fine quantum confinement structure can be easily formed by using a heterojunction of silicon and silicon germanium. .

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a quantum wire according to a first embodiment of the present invention.

FIG. 2 is a plan view of an FET according to a second embodiment of the present invention.

FIG. 3 is a sectional view taken along the line AA ′ of the FET of FIG.

FIG. 4 is a cross-sectional view taken along the line BB ′ of the FET of FIG.

5 is a cross-sectional view of the FET of FIG.

FIG. 6 is a sectional view showing a quantum wire according to a third embodiment of the present invention.

FIG. 7 is a process sectional view showing a process of manufacturing a quantum wire according to a fourth embodiment of the present invention.

FIG. 8 is a perspective view of an FET according to a fifth embodiment of the present invention.

FIG. 9 is a perspective view of an FET according to a sixth embodiment of the present invention.

FIG. 10 is a process sectional view showing the method for forming the FET according to the seventh embodiment of the present invention.

FIG. 11 is a sectional view of an FET according to an eighth embodiment of the present invention.

FIG. 12 is a sectional view of an FET according to a ninth embodiment of the present invention.

[Explanation of symbols]

11 ... Silicon substrate 12 ... Silicon oxide film 13 ... n-type silicon film 14 ... Strained silicon germanium film 15 ... Silicon film 21 ... p-type silicon substrate 22 ... Gate oxide film 23 ... n-type region 24 ... n-type region 25 ... Source electrode 26 ... Drain electrode 27 ... Gate electrode 31 ... Silicon substrate 32 ... Silicon oxide film 33 ... First silicon germanium film 34 ... Strained silicon film 35 ... Second silicon germanium film 36 ... Silicon film 41 ... Silicon support plate 42 ... Silicon oxide film 43 ... Silicon film 44 ... Silicon germanium film 45 ... Strained silicon film 46 ... n-type silicon film 47 ... Silicon film 48 ... Gate electrode 49 ... Source electrode 50 ... Drain electrode 51 ... Quantum wire 61 ... Silicon oxide film 62 ... p-type silicon film 63 ... Thermally oxidized silicon film 64 ... n-type silicon germanium film 65 ... Strained silicon film 71 ... p-type silicon substrate 72 ... Thermally oxidized silicon film 73 ... n-type region 75 ... Strained silicon germanium film 81 ... Silicon film 82 ... Silicon germanium film 83 ... Strained silicon film 84 ... Thermally oxidized silicon film 85 ... Opening 86 ... p-type region 87 ... n-type silicon germanium film 88 ... Silicon film

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Seiji Imai 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Toshiba Research & Development Center, Inc. (72) Inventor Keiko Hiraoka Komukai-Toshiba, Kawasaki-shi, Kanagawa No. 1 in the Toshiba Research & Development Center Co., Ltd. (72) Inventor Atsushi Kurobe No. 1, Komukai Toshiba Town, Komukai-ku, Kawasaki-shi, Kanagawa Within the Toshiba R & D Center Co., Ltd. (56) Reference JP-A-6-224122 (JP, 224122) A) JP-A-6-85317 (JP, A) JP-A-7-162015 (JP, A) JP-A-6-188414 (JP, A) JP-A-5-275473 (JP, A) Taro ARAKAWA, Shi ro TSUKAMOTO, Yasushi NAGAMUNE, Masao NISHIOKA, Jin-Hee Lee, Ya uhiko ARA KAWA, "Fabrication of InGaAs strained Quantum Wire Structure Using Slectic ve-Area Metal-April Apo, Apr 1975, Jap. .L1377-L 1379, title deficiency there N. Usami, T. Min e, S. Fukatsu, Y. Shiraki, "FABRICATI ON OF SiGe / Si QUAN TUM WIRE STRUCTURE ON A V-GROOVE PAT TERNED Si SUBSTRAT E BY GAS- SOURCE S i, Solid-State Elec ronics, 1994 years, Vol. 37, Nos. 4-6, pp. 539-541, Title defect (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/80 H01L 29/06 H01L 29/66 H01L 29/78 H01L 21/20 H01L 21/205 Web of Science

Claims (4)

(57) [Claims] 1. A silicon oxide film and a quantum wire structure formed on the silicon oxide film.
That it comprises a field effect transistor, the field effect transistor is formed on the silicon oxide film, processed into a stripe shape
And a region of the non-strained silicon film processed into the stripe shape.
The gate oxide film formed on the region and the non-side regions on both sides of the short side of the stripe-shaped region.
The source and drain are formed on the exposed surface of the strained silicon film.
As a non-strained silicon germanium film, and the non-strained silicon germanium film and the gate oxide
A strained silicon film formed on the film, and the strained silicon film on the non-strained silicon germanium film
A source electrode and a drain electrode provided through the non-strained silicon film and the region processed into the stripe shape of the non-strained silicon film.
And a gate electrode for applying a voltage to the region . 2. The non-strained silicon gate is formed on the gate oxide film.
The rumanium film invades.
1. The semiconductor device according to 1 . 3. A silicon oxide film and a quantum wire structure formed on the silicon oxide film.
That it comprises a field effect transistor, the field effect transistor is formed on the silicon oxide film, processed into a stripe shape
A first non-strained silicon film having a patterned region, and the first non-strained silicon film processed into the stripe shape.
The gate oxide film formed on the exposed region and the first and second sides on the short sides of the striped region.
1 formed on the exposed surface of the non-strained silicon film,
And a second non-strained silicon film as a drain, and on the second non- strained silicon film and the gate oxide film.
The formed strained silicon germanium film and the strained silicon germanium film on the second non-strained silicon film.
Source electrode and drain electrode provided through the um film.
The poles and the stripes of the first non-strained silicon film.
And a gate electrode for applying a voltage to the isolated region . 4. The second non-strained silicon layer on the gate oxide film.
4. The film according to claim 3, characterized in that the con-membrane is invaded.
Mounted semiconductor device.