JP3753391B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a quantum effect element and a manufacturing method thereof.
[0002]
[Prior art]
It is known that a quantum effect element can be manufactured by stacking semiconductor layers having different band gaps. A quantum well for confining carriers can be formed adjacent to the interface so that the current flowing between the source and drain regions can be modulated by the voltage applied to the gate electrode above it.
[0003]
Such carriers usually have a high mobility and exist in two dimensions and behave as “two-dimensional electron gas” (2DEG), or exist in a substantially one-dimensional manner depending on the applied voltage, that is, often “ It can exist as “one-dimensional gas” (1DEG), also called “quantum wire”.
[0004]
Needless to say, an element using two-dimensional hole gas (2DHG) or one-dimensional hole gas (1DHG) with majority carriers as holes can be formed. However, for simplicity, here, 2DEG and 1DEG are used in a broad sense, and unless otherwise indicated, 2DEG and 1DEG include both two-dimensional gas and one-dimensional gas of both electrons and holes. It shall be.
[0005]
By the way, if the barrier potential is formed in three dimensions, it is estimated that about 100 electrons can be confined as a lump. This accumulation of electrons is generally called a “quantum dot” or “quantum box”. In such a configuration, the electrons are confined in all three dimensions.
[0006]
However, here, these terms (quantum dots, quantum boxes) are confined in three dimensions, but the wave function of the particles is very spatially smaller than the linear dimension of the volume that confines the particles. Since it is small, a case where a three-dimensional quantum action does not occur is also included.
[0007]
Conventionally, confinement of electrons by this type of quantum dot has been realized as follows. That is, it is realized by configuring four or more depletion type Schottky gates on the surface of the heterojunction semiconductor structure having 2DEG, for example, like a turnstile.
[0008]
Since the electron gas is crushed by the Schottky gate, the remaining two degrees of freedom are lost. This added squashing or confinement creates a tunnel barrier around the quantum dot, and electrons enter and exit the quantum dot through this tunnel barrier.
[0009]
Such movement of electrons through the quantum dots is affected when a current or voltage is applied to the quantum dots from the outside. This external bias increases the energy of the electrons, so that the electrons can jump over or penetrate the tunnel barrier.
[0010]
If the confinement length is sufficiently short (<300 nm) and the number of electrons is sufficiently small (hundreds or less), single electron charging, commonly called coulomb blockade, is quantum. It appears as a change in the current-voltage characteristics of the dots.
[0011]
Coulomb energy, which is the energy of one-electron charging, causes the entire electron to be transferred to the quantum dot, despite the fractional charge that forms an electrical neutral state between the quantum dot and the surrounding electron reservoir. This is an energy penalty caused by the addition. This charging energy is e ² / 2C, where C is the capacitance of the quantum dot.
[0012]
As a result of this charging energy, when the conductance or resistance is measured as a function of the voltage applied to the quantum dot via the capacitance C, it can be seen that the conductance and resistance values “fluctuate” with a period of e / C.
[0013]
Alternatively, when the conductance or resistance is measured as a function of the confinement width, it can be seen that the oscillation similarly occurs. Than confinement swung by change in width occurs, to vary the capacitance depending on the confinement width, or put electrons into the quantum dots, because also changed discharge energy e2 / 2C needed to and out from there is there.
[0014]
In the case of a quantum dot formed by a depletion type Schottky gate, the confinement width varies depending on the voltage (gate bias) Vfg applied to the gate. Therefore, the fluctuation of conductance and resistance is a function of the gate bias Vfg.
[0015]
In principle, the application range of a quantum effect device using Coulomb brocade is wide, and can be used for, for example, a micro transistor or a memory. However, a Coulomb brocade having a conventional structure in which a Schottky gate is configured like a turnstile does not function unless the temperature is very low, for example, an absolute temperature of 4K or less. Therefore, there is a problem that the operating temperature of the quantum effect element using this type of Coulomb brocade is also low.
[0016]
[Problems to be solved by the invention]
As described above, the quantum effect element using the conventional Coulomb brocade has a problem that the operating temperature is low.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device including a quantum effect element using a Coulomb brocade that can operate even at a higher temperature than the conventional one.
[0017]
[Means for Solving the Problems]
The present invention has taken the following measures in order to solve the above problems. In order to achieve the above object, a semiconductor device according to the present invention includes a plurality of second conductivity type layers and a plurality of first conductivity type layers that serve as barrier layers, which are alternately stacked. A laminated structure in which a rear barrier confinement potential is formed, an inclined surface formed so as to obliquely cross the laminated structure, and an end portion of each layer of the laminated structure is exposed, and covers the inclined surface An active layer in a plane parallel to the inclined surface and for allowing carriers to flow in the stacking direction of the stacked structure; and an upper portion of the active layer, wherein the carriers are formed in each layer of the stacked structure. A gate electrode having a constricted region having a notch for allowing the flow to exceed the end of each layer of the stacked structure only in the tilt direction defined by the end of the stacked structure, and the upper portion of the tilted surface. And the game A drain connected to one of the electrodes via an implant layer; and a source below the inclined surface and connected to the other of the gate electrodes via an implant layer. A quantum effect element using a Coulomb brocade formed in a laminated structure is provided .
[0018]
Preferred embodiments of the present invention are as follows.
(1) The narrowed region extends in a direction substantially perpendicular to each end of the plurality of layers.
[0019]
(2) In each of the above-described configurations, the first and second contacts that are provided on the respective sides of the constricted portion and contact the carrier are provided .
[0020]
( 3 ) In the above configuration, the at least one layer is a layer made of SiO ₂ .
( 4 ) In each of the above-described configurations , the stacked structure includes a doped quantum well inducing layer and first and second doped layers separated from the doped quantum well inducing layer by an insulating barrier layer, respectively.
[0021]
( 5 ) In each of the above configurations , the at least one layer is narrow below a narrow portion of the gate electrode.
( 6 ) In each of the above configurations , the quantum well inducing layer is narrow below the narrow portion of the gate electrode.
[0022]
( 7 ) In the configuration of ( 6 ), the first and second doped layers are narrowed below the narrow portion of the gate electrode.
( 8 ) In the configuration of ( 6 ) or ( 7 ), the quantum well inducing layer and the first and second doped layers are disposed between insulating or semi-insulating side walls standing upright from the inclined surface.
[0023]
(9) In the configuration of (8), the side wall, it is SiO _2.
( 10 ) In each configuration described above, the constricted region is formed of a gate electrode having a narrow portion formed by a notch.
[0024]
( 11 ) In each of the above configurations, the constricted region is a narrow portion of an active layer constituting a region covering the inclined surface.
( 12 ) In each of the above configurations, the layer covering the inclined surface has a HEMT structure.
[0025]
( 13 ) In each of the above structures, the layer covering the inclined surface is an active layer made of InGaAs covered with an impurity-doped AlInAs layer.
( 14 ) In each configuration described above, the plurality of layers are a plurality of layers in which delta doped layers having different conductivity types are alternately arranged.
[0026]
( 15 ) In the configuration of ( 14 ), the plurality of delta doped layers include first, second, and third layers of the first conductivity type, and first, second conductivity type of the first conductivity type opposite to the first conductivity type, A first layer of the second conductivity type is disposed between the first layer of the first conductivity type and the second layer of the first conductivity type, and The second conductivity type second layer is disposed between the first conductivity type second layer and the first conductivity type third layer.
[0027]
( 16 ) In the constitution of ( 14 ) or ( 15 ), the delta doped layer is a delta doped layer made of silicon.
( 17 ) In each of the above configurations , the plurality of layers include two SiO ₂ layers provided in an impurity-doped silicon layer.
[0028]
( 18 ) In each of the above-described configurations , the plurality of layers are a plurality of layers in which layers made of a material having a higher band gap and layers made of a material having a lower band gap are arranged alternately than adjacent layers. .
[0029]
( 19 ) Arrange the semiconductor devices in any of the above-described structures to form a memory device.
According to the present invention, there is provided a method for manufacturing a semiconductor device having a quantum effect element using a Coulomb brocade, wherein the first conductive type layer and the second conductive type layer, which serve as a barrier layer, are alternately stacked. Forming a stack structure by sandwiching the second conductive type layer between the mold layers, and etching the stack structure to expose the inclined surface so that the end of each layer of the stack structure is exposed Forming at least one layer that covers the inclined surface by regrowth, and forming a gate electrode having a constricted region on the at least one layer. To do.
[0030]
A preferred embodiment of the method of the present invention is as follows.
(1) A gate electrode is formed on top of at least one layer and a narrowed region is formed by an etching process to constitute the constriction means. The etching is performed following the at least one layer first. And is performed on the ramp to leave an upright portion below the narrowed region of the gate electrode.
[0031]
(2) In the aspect of (1), after the etching process reaches the at least one layer, an insulating layer is formed on the upper wafer surface before continuing the etching on the inclined surface.
[0032]
(3) In the aspect of (2), the insulating layer is formed of silicon nitride.
(4) In the aspects of (1) to (3), an insulating layer or a semi-insulating side wall is formed around at least one portion of the upright portion.
[0033]
(5) In the aspect of (4), the plurality of layers include an impurity-doped silicon layer, and the sidewall is formed of SiO ₂ formed by oxidation of at least some of the impurity-doped silicon. thing.
[0034]
The semiconductor device manufactured by the semiconductor device according to the present invention and the semiconductor device manufacturing method according to the present invention is not only operated at a temperature higher than the conventional one, but also considerably smaller by using a substrate whose surface is obliquely patterned. Can be The structure itself requires a smaller space than a flat system, and the external wiring can be shortened. The shortening of the wiring is a particularly important factor when a plurality of wirings are arranged on one wafer to function as a semiconductor memory. Also, the power consumption when charging the quantum dot electrons is very low.
[0035]
The constriction region can take several different forms depending on the structure of the device. In one form of device based on a silicon wafer, a SiO ₂ layer and a gate electrode are formed on an inclined surface, and carriers are generated on the inclined surface. Carriers are generated only on the inclined surface under the gate electrode. In this case, the constriction region is a narrow portion of the gate electrode that covers each end of the plurality of layers and extends in a direction inclined with respect to each end.
[0036]
In another form, an active layer (such as a HEMT structure) is formed on the inclined surface to generate carriers under the active layer. In this case, carriers other than the desired portion are depleted by the gate electrode covering the active layer. The gate electrode has a cut-away portion corresponding to its shape. The notch has a narrow portion that covers each end of the plurality of layers and extends in a direction inclined with respect to each end. The term “notch” means that the gate electrode material is not present in a predetermined region of the gate electrode. In practice, the notch can be formed by selective etching. Alternatively, the active layer or the HEMT structure itself can be selectively etched to form a narrow region that covers each end of the plurality of layers and extends in a direction inclined with respect to each end.
[0037]
The device according to the invention can be manufactured for various applications. For example, it can be manufactured as a transistor. By arranging such transistors, a small memory device can be manufactured.
[0038]
In a typical transistor device, electrical contacts are provided so that the active layer is in contact with each end of the constriction region and a conduction channel is formed between the ends.
[0039]
As will be apparent from the description of the preferred embodiment below, this conduction channel “interrupted” in use, and a pool of electrons separated by a three-dimensional barrier under the constriction region , ie, “quantum dots”. ”Is formed.
[0040]
Although not wishing to be limited to any theoretical explanation, the semiconductor device according to the present invention is formed by separating quantum dots, which are electron pools, by a three-dimensional confinement barrier as follows.
[0041]
Initially, the carriers are two-dimensionally confined in the inclined surface or in the HEMT layer or active layer covering the ends of the layers as close as possible to the edges of the layers to produce a 2DEG. Multiple layers create at least one double confinement barrier in 2DEG.
[0042]
Next, the carrier of 2DEG is depleted except in the narrow region under the gate electrode, particularly under the narrow part of the gate electrode, thereby creating a barrier in the third direction across the edges of the plurality of layers. It is confined in the quantum dot.
[0043]
Some embodiments are covered with a layer of silicon dioxide so that they can function at room temperature. A carrier is generated just in the inclined plane. Alternatively, the uppermost layer may be part of the HEMT structure.
[0044]
The HEMT is composed of a material having a relatively high bandgap and a material having a relatively low bandgap, for example, GaAs / AlGaAs. The carrier from the impurity-doped layer has a high bandgap and a material having a low bandgap. It is confined in 2DEG near the boundary. Such a structure has been studied in detail (Japanese Journal of Applied Physics, Vol. 21, No. 6, June 1992, p. L381).
[0045]
In advances in molecular beam growth and other technologies in semiconductor manufacturing, the device according to the present invention is easily formed using a regrowth process. Accordingly, an apparatus according to the present invention comprises a step of forming a stack structure, a step of etching the stack structure to expose an inclined side surface, a step of forming at least one layer by regrowth, and the at least one layer And forming a constricted region on top of the layer.
[0046]
When the constriction region is a narrow part of the gate electrode, for example, when the at least one layer is formed of SiO ₂ , the narrow part can be formed by selective etching. This is done following one layer, and then on the sides that are sloped to leave an upright portion at the bottom of the narrow region of the gate electrode.
[0047]
After this etching step reaches the at least one layer, an insulating layer such as Si ₃ N ₄ can be formed on top of the upper wafer surface. This etching can be performed following the sloped sides, removing either the top of this insulating layer and the sides of the constriction gate. The exposed side of the upright portion can then be covered with an insulating or semi-insulating sidewall structure. If the plurality of layers are formed of doped silicon, for example, if SiO ₂ is scattered, the sidewall structure can form SiO ₂ by an oxidation process.
[0048]
Another known heterostructure system, for example an InGaAs active layer covered with an impurity-doped AlInAs layer, can be the top layer.
The plurality of layers generate a pair of barriers in the 2DEG plane, and a well is formed between the pair of barriers. In a preferred embodiment, the barrier height (well depth) to the well is at least on the order of 0.3 eV.
[0049]
Fortunately, multiple layers can be formed in a silicon-based or III / V semiconductor-based structure by alternately forming two layers of different conductivity types by delta doping.
[0050]
For example, when one quantum well is formed, the first, second, and third layers of the first conductivity type and the first and second layers of the second conductivity type opposite to the first conductivity type are formed. Forming a layer. The first conductivity type first layer is disposed between the first conductivity type first layer and the first conductivity type second layer, and the second conductivity type second layer is disposed in the first conductivity type. Between the second layer and the third layer of the first conductivity type. In this case, both layers of the second conductivity type create a barrier, and the second layer of the first conductivity type becomes a well.
[0051]
Another silicon-based system has a pair of silicon dioxide layers (corresponding to a barrier) with an impurity-doped silicon layer sandwiched between the two layers. The same effect can be obtained by forming a plurality of layers in which a layer having a high band gap and a layer having a low band gap are alternately stacked with respect to adjacent layers.
[0052]
According to the present invention, since the region where carriers flow is limited by the constriction region , the level between the sub-bands of the rear barrier confinement potential is increased as compared with the case where the carrier is not limited. When the level between subbands becomes large, the carrier of the ground level becomes difficult to be excited even if the temperature rises accordingly. Therefore, it can operate normally even at a higher temperature than before.
[0053]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a sectional view showing a schematic configuration of the quantum effect element according to the first embodiment of the present invention, and FIG. 2 is a plan view of the quantum effect element of FIG. FIG. 1 is a cross-sectional view taken along the line AA ′ of FIG.
[0054]
On the p ⁻ type substrate 3 made of silicon, a plurality of delta doped layers having an impurity concentration of the order of 10 ¹³ cm ⁻² for forming the rear barrier confinement potential are alternately formed as follows.
[0055]
A first p-type delta doped layer 9 exists between the first n-type delta doped layer 5 and the second n-type delta doped layer 7. A second p-type delta doped layer 13 exists between the second n-type delta doped layer 7 and the third n-type delta doped layer 11 on the second n-type delta doped layer 7. The remaining portion of the wafer above these delta doped layers is comprised of a p ^- type layer 15 .
[0056]
The distance between the first p-type delta doped layer 9 and the second p-type delta doped layer 13 is about 100 to 400 angstroms. An inclined surface 17 (<111> surface inclined by 56 ° with respect to the wafer plane) is formed on the wafer by patterning.
[0057]
Also, the doping concentration is such that by introducing a p-type delta doped layer, as shown in FIG. 3, two barriers (backward barrier confinement potential) are generated in the conduction band (EC) on the inclined surface, thereby forming a Coulomb brocade. select. In FIG. 3, EF represents the Fermi level.
[0058]
A first n-type implant layer 19 is formed on the lower horizontal surface 21 of the wafer exposed by etching, and a second n-type implant layer 23 is formed on the upper surface of the unetched wafer.
[0059]
A lower ohmic contact layer (source) 25 is formed on the first n-type implant layer 19, and an upper ohmic contact layer (drain) 27 is formed on the second n-type implant layer 23.
[0060]
The exposed <111> plane is covered with a SiO ₂ active layer 29 formed by a growth method, and a gate electrode 31 is formed on the SiO ₂ active layer 29.
The lower ohmic contact layer 25 that is a source is formed via the first n-type implant layer 19, while the upper ohmic contact layer 27 that is a drain is formed below the inclined surface 17 via the second n-type implant 23 layer. In contact with the two-dimensional electron gas (2DEG).
[0061]
As is apparent from the plan view of FIG. 2, the gate electrode 31 includes a lower wide portion 33 extending toward the lower ohmic contact layer 25 serving as a source and an upper wide portion extending toward the upper ohmic contact 27 serving as a drain. 35.
[0062]
The lower wide portion 33 and the upper wide portion 35 are connected to each other by a narrow portion 37. The narrow portion 37 covers the end of the entire delta doped layer along the inclined surface 17. The narrow portion 37 is arranged to extend at an angle of 90 ° with respect to the extending direction of the edge of the delta doped layer and is separated from the delta doped layer by the SiO ₂ active layer 29.
[0063]
However, in the embodiment in which an active layer for confining carriers inside is formed by regrowth, there are two types of “ constriction regions ” as follows. The first type is to form a gate electrode (depleting gate) covering the active layer or HEMT. The gate electrode may have any shape as long as it can cover the inclined surface. However, the gate electrode must have a notch (a portion without material) in accordance with the shape of the gate electrode shown in FIG. I must.
[0064]
In the second type, the active layer or HEMT is selectively etched to form a narrow portion, which has the same shape as the gate electrode in FIG.
According to the present embodiment, since the narrow portion 37 of the gate electrode 31 is located on the inclined surface 17 where the rear barrier confinement potential is formed, the carrier flow path is narrowed there. This increases the level between the subbands of the rear barrier confinement potential. When the level between subbands becomes large, the carrier of the ground level becomes difficult to be excited even if the temperature rises accordingly. Therefore, it can operate normally even at a higher temperature than before.
[0065]
4 and 5 are sectional views showing a schematic configuration of a quantum effect element according to the second embodiment of the present invention. In the following drawings, the same reference numerals as those in the previous drawings indicate the same or corresponding parts, and detailed description thereof is omitted .
[0066]
The overall structure of the quantum effect element of this embodiment is almost the same as that of the first embodiment, but the p ⁻ -type substrate 41 includes a lower SiO ₂ layer 43 and an upper SiO ₂ layer 45 instead of the delta doped layer. Have.
[0067]
A p ⁻ type layer 47 exists between the lower SiO ₂ layer 43 and the upper SiO ₂ layer 45. The thickness of both SiO ₂ layers 43, 45 is less than about 20 angstroms, and the distance between both SiO ₂ layers 43, 45 is less than about 1000 angstroms. The remainder of the wafer above this layer structure is covered with a p ⁻ -type layer 49.
[0068]
The vertical surface 51 which is the <111> plane is exposed by dry etching, and the lower n-type implant layer 53 and the upper n-type implant layer 55 are respectively corresponding to the lower n-type implant layer 19 and the corresponding quantum effect element of the first embodiment. It is formed at the same position as the upper n-type implant layer 23.
[0069]
The ohmic contact layer (source) 57 is formed in contact with the lower n-type implant layer 53, and the ohmic contact layer (drain) 59 is formed in contact with the upper n-type implant layer 55.
[0070]
In the present embodiment, the SiO ₂ active layer 61 is formed by regrowth so as to cover the inclined surface 51 (backward vertical), and the gate electrode 31 having the same shape is formed on the SiO ₂ active layer 61.
[0071]
In the present embodiment, the ohmic contact layers 53 and 55 and the n-type implant layers 57 and 59 are in contact with the two-dimensional electron gas (2DEG) under the inclined surface 51 as in the first embodiment. Plays the function.
[0072]
A preferred method of forming the barrier layer is a silicon recrystallization technique. FIG. 6 is a schematic view showing the recrystallization process. As will be described in more detail below, this technique can be used effectively to produce the deformation of the structure shown in FIG. 4, so that not only the narrowed gate region 37 as shown in FIG. A narrowed conduction region defined by the narrowed region of the SiO ₂ layer 51, barrier layers 43 and 45, a well layer 47, and p ^- silicon regions 41 and 49 are formed. Here, a narrowly defined quantum box region can be created using ULSI technology.
[0073]
After the first SiO ₂ barrier layer 43 is grown, it is patterned to expose the silicon substrate in the region 40 as shown in FIG. Then, Si is deposited so that the Si layer covers the entire surface. This is heated and crystallized. Under normal circumstances, this process results in polysilicon. However, as shown in FIG. 7, which will be described in detail later, the exposed silicon surface is simply grown on the SiO ₂ layer until interrupted by the formation of the polysilicon region 44 at some distance from the SiO ₂ edge. It behaves as a seed crystal center of silicon crystal that can form crystalline Si. The distance between the boundary surface and the SiO ₂ edge depends on the recrystallization process and the thickness of the amorphous Si layer 42. In general, the greater the thickness, the greater the distance. However, if the SiO ₂ layer 43 is very thin (1-2 nm), this direction is reversible and the silicon layer exceeds about 1 μm. This is long enough to further process the state of the finishing lithographic apparatus and is an excellent process for making the barrier layers 43, 45 under these conditions.
[0074]
This technology is not only compatible with ULSI, but does not cause significant yield loss due to grain boundaries and the like. The critical processing step is a first recrystallization step that requires only a very thin Si layer. The second and last recrystallized Si layers must be relatively hot (> 200 nm) to reduce stray capacitance.
[0075]
FIG. 7 is a schematic explanatory diagram for forming a complete barrier layer / quantum well structure. The SiO ₂ barrier layers 43 and 45 have different widths. This ensures that the source / drain sweep exhibits a step-like characteristic in conductance due to the tunneling effect of one electron. If the tunnel probability is the same for both barriers 43 and 45, theoretically no structure in the source / drain sweep is observed. However, resonance appears to be observed in source / drain conductance as a function of gate bias.
[0076]
By recrystallization, the deposition of the second Si layer 46 on the first polysilicon region 44 is repeated, leaving the second polysilicon region 48 at the end.
Despite the progress of thin film oxidative growth for MOSULSI submicron gate technology, the required oxide thickness for such devices is the dielectric breakdown due to pinholes over relatively uniform areas. It means that the strength can be reduced. Properties such as dielectric constant and composition are similarly difficult to control the potential. However, since the final device active area is designed to be smaller than 10 ^-11 cm ^-2 , the equipment design can tolerate very high pinhole densities and can achieve high yields. . For example, at a yield of just 99% relative to the barrier oxide layer, the defect density is only required to be less than 10 ⁹ cm ⁻² .
[0077]
A process flow for fabricating the complete structure of FIG. 4 from the basic barrier layer / quantum well structure of FIG. 7 will be described with reference to FIGS. Although the outline of the technique is described, a narrowly defined gate region and a conduction channel can be formed so as to cover the well inducing layer 47. Another method of fabricating the buried SiO ₂ layer is by double band and etch back.
[0078]
First, the SiO ₂ layer 61 is made 100 nm thick by thermal growth. The change in oxide thickness between the facet and the (100) plane depends on the growth process of the oxide and the direction of the facet relative to the (110) plane.
[0079]
FIG. 12 shows various synthetic sidewall crystal faces formed by 90 ° etching to the wafer face for a (100) wafer. If the mesa direction is 45 ° with respect to the (011) direction, the side wall surfaces are all flat surfaces such as (100). Thus, the oxide growth rate should be approximately the same as on the sidewalls and (100) substrate surface. If the mesa plane is 45 ° with respect to the (011) plane, the plane is one of the (001) planes, so that the oxide film grows uniformly. From the point of view of processing points, this is the optimal direction since all oxide films grow on a plane like (100).
[0080]
Next, a poly n-Si layer 50 is deposited, annealed and covered with a Si ₃ N ₄ layer 52. This Si ₃ N ₄ layer 52 acts as a dry etch mask and protects the poly-Si against subsequent Si etching as described below. The main gate structure is then defined by etching, forming a narrow 100 nm limit in the facet region. The narrowed region 50 of poly n-Si represents a restricted region 37 of the gate electrode. This region where the source / drain contacts are defined is left unpatterned.
[0081]
A further Si ₃ N ₄ layer 54 is then deposited on the entire wafer surface (FIG. 8). Thereby, the poly n-Si sidewall is passivated by the nitride layer 54. Therefore, subsequent oxidation of the substrate does not result in significant oxidation of the remnant poly n-Si 50. The thickness of the second nitride layer 54 is minimal, and this technique increases the line width for etched silicon in the following manner. However, as a sufficient nitride, it is necessary that the effective oxidation rate of poly n-Si is smaller than (100) p ^- Si. If the initial nitride layer (layer 52) is thicker than the oxide layer, the selectivity from oxide to nitride can be as low as 1 when the oxide layer is etched. The planar region of the Si ₃ N ₄ layer 54 that is in direct contact with the SiO ₂ layer 61 and the layer 52 is etched using anisotropic dry etching (FIG. 9). Etching is continued through the recrystallized Si layers 44 and 46 and the thin film SiO ₂ barrier layers 43 and 45 until a depth of 400 nm or more is reached. This etching leaves an upstanding proud gate region of the substrate as seen in FIG.
[0082]
Then, SiO ₂ grows on the exposed side walls 56 and 58 (FIG. 11). With the exposed (001) sidewall exposed in the previous etching step, the oxide grows in the first thermal oxide region 61, ie, in a narrow gate that leaves a limited conduction channel 60.
[0083]
FIG. 13: is sectional drawing which shows schematic structure of the quantum effect element which concerns on the 3rd Embodiment of this invention.
The first n ⁺ -type GaAs layer 65 having a thickness of 1000 Å is covered with a semi-insulating GaAs layer 67 having a thickness of 5000 Å.
[0084]
In order to alternately form n-type delta doped layers and p-type delta doped layers of GaAs, delta doping is used exactly as in the first embodiment.
A first p-type delta doped layer 73 exists between the lower n-type delta doped layer 69 and the intermediate n-type delta doped layer 71. In addition, a second p-type delta doped layer 77 exists between the intermediate n-type delta doped layer 71 and the upper n-type delta doped layer 75. An upper semi-insulating layer 79 having a thickness of 5000 Å is provided on the upper n-type delta doped layer 75.
[0085]
The n-type delta doped layers 69 and 75 are both about 50 angstroms thick, and the distance between the p-type delta doped layers 73 and 77 is on the order of less than 1000 angstroms.
[0086]
A second n ⁺ -type GaAs layer 81 having a thickness of 400 angstroms is formed on the top of the wafer. By the selective etching, an inclined <311> B inclined surface 83 intersecting with the entire delta doped layer is formed.
[0087]
A GaAs layer 85 having a thickness of less than 100 angstroms covering this structure is formed by regrowth, and this GaAs layer 85 is covered with a HEMT structure 87. As already described, the gate electrode 31 has a notch. Alternatively, the HEMT structure 87 is selectively etched into this shape.
[0088]
The lower ohmic contact layer 89 as the source and the upper ohmic contact layer 91 as the drain are in contact with the first n ⁺ -type GaAs layer 65 and the second n ⁺ -type GaAs layer 81, respectively, and thereby activate the HEMT structure 87. It is in electrical contact with a two-dimensional electron gas (2DEG) in the layer.
[0089]
FIG. 14 is a cross-sectional view showing a schematic configuration of a quantum effect element according to the fourth embodiment of the present invention.
The quantum effect element of this embodiment is different from that of the third embodiment in that GaAs is used as an underlying wafer. This wafer has a lower GaAs layer 95, a lower AlGaAs layer 97 and an upper AlGaAs layer 99 provided on the lower GaAs layer 95.
[0090]
A GaAs layer 101 exists between the upper and lower AlGaAs layers 97 and 99, and the top of the wafer is a GaAs layer 103. Similar to the third embodiment, the GaAs layer 103 is covered with a second n ⁺ -type GaAs layer 81, and an inclined surface 83 is formed by selective etching, so that upper and lower ohmic contact layers 89 and 91 are formed. It is formed. In this case, the AlGaAs layers 97 and 99 form a pair of barriers that separate the quantum dots.
[0091]
FIG. 15: is sectional drawing which shows schematic structure of the quantum effect element which concerns on the 5th Embodiment of this invention.
In this embodiment, an implant layer and an ohmic contact layer (source, drain) are used as in the first three embodiments, but this is not shown in FIG. 15 for simplicity. The source and drain are in contact with an InGaAs layer 107 (active layer) covered with an n-type AlInAs layer 109. The InGaAs layer 107 and the n-type AlInAs layer 109 are formed by regrowth so as to cover the wafer having the inclined surface 111 formed by exposing the (311) B surface by selective etching.
[0092]
This etched wafer has a lower n-type InP layer 113. On this lower n-type InP layer 113, there is an InGaAs layer 115 thicker than 1000 angstroms. A lower InGaAs layer 121 having a thickness of 100 to 400 angstroms exists between the lower InP layer 117 and the upper InP layer 119, and an upper InGaAs layer (p ⁻ type In 0.53 Ga 0.47 As) layer is formed on the upper InP layer 119. 123 exists.
[0093]
FIG. 16 is a characteristic diagram showing the relationship between the gate voltage Vg and the conductance for a pair of layers forming the rear barrier confinement potential (Coulomb brocade) in the stacked structure of the quantum effect device of the present invention (curve B).
[0094]
FIG. 16 also shows the relationship between the gate voltage Vg and conductance of a conventional FET (curve A).
It can be seen from FIG. 16 that the conductance initially increases with an increase in the gate voltage Vg, but thereafter the conductance decreases with an increase in the gate voltage Vg.
[0095]
However, in the present invention, as can be seen from the curve B, the conductance fluctuates (pulsates). From this, it can be seen that one electron enters or leaves the quantum dot. That is, it can be seen that the coulomb brocade functions effectively.
[0096]
FIG. 17 is a characteristic diagram showing the relationship between the source-drain voltage VDS and the conductance for a pair of layers forming the rear barrier confinement potential (Coulomb brocade) in the stacked structure of the quantum effect device of the present invention (curve). D).
[0097]
FIG. 17 also shows the relationship between the source-drain voltage VDS and the conductance of a conventional FET (curve D).
It can be seen from FIG. 17 that the conductance initially increases as the source-drain voltage VDS increases, but then the conductance saturates.
[0098]
However, in the case of the present invention, as can be seen from the curve D, the conductance increases while swinging (pulsating). On the other hand, in the conventional case, as can be seen from the curve C, the conductance increases linearly. From this, it can be seen that one electron enters or leaves the quantum dot. That is, it can be seen that the coulomb brocade functions effectively.
[0099]
As is clear from the change in conductance as shown in FIGS. 16 and 17, since electrons are present or absent in the quantum dot, this device can be used as a memory cell. .
[0100]
Therefore, by arranging a large number of the quantum effect elements of the above embodiment, it is possible to realize an ultra-compact memory device with low consumption. Moreover, such a memory device can be manufactured by a single wafer process. According to the semiconductor device according to the present invention such as a memory device using such a quantum effect element, the above-described effect (wiring compression described in the section of means) can be obtained.
[0101]
In addition, this invention is not limited to embodiment mentioned above. For example, more quantum dots may be formed by providing a plurality of barrier pairs by providing a plurality of layers on an etched basic wafer (wafer having an inclined surface).
[0102]
In this case, the elongated portion of the gate electrode must be extended to cover each barrier. If it does in this way, one electron can be made to pass continuously from a quantum dot to a quantum dot like operation of a charge coupled device (CCD) or a shift register.
[0103]
In addition, various modifications can be made without departing from the scope of the present invention.
The present invention is not limited to the embodiment of the invention described above, and it is needless to say that various modifications can be made without departing from the scope of the invention.
[0104]
【The invention's effect】
According to the present invention, the following effects can be obtained. As described above in detail, according to the present invention, the region through which carriers flow is limited by the constriction region , and therefore, the level between the sub-bands of the rear barrier confinement potential is increased as compared with the case where it is not limited. When the level between subbands becomes large, the carrier of the ground level becomes difficult to be excited even if the temperature rises accordingly. Therefore, it can operate normally even at a higher temperature than before.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a schematic configuration of a quantum effect device according to a first embodiment of the invention.
FIG. 2 is a plan view of the quantum effect element according to the first embodiment of the invention.
FIG. 3 is a diagram showing a change in a conduction band due to introduction of a p-type delta doped layer.
FIG. 4 is a sectional view showing a schematic configuration of a quantum effect element according to a second embodiment of the invention.
FIG. 5 is a cross-sectional view showing a schematic configuration of a quantum effect element according to a second embodiment of the present invention.
FIG. 6 is a schematic diagram showing a recrystallization process.
FIG. 7 is a schematic explanatory diagram for forming a barrier layer / quantum well structure.
8 is a diagram showing a flow of steps for manufacturing the structure of FIG. 4 from the barrier layer / quantum well structure of FIG. 7;
9 is a diagram showing a flow of steps for manufacturing the structure of FIG. 4 from the barrier layer / quantum well structure of FIG. 7;
10 is a diagram showing a flow of steps for manufacturing the structure of FIG. 4 from the barrier layer / quantum well structure of FIG. 7;
11 is a diagram showing a flow of steps for manufacturing the structure of FIG. 4 from the barrier layer / quantum well structure of FIG. 7;
FIG. 12 shows various synthetic sidewall crystal planes formed by 90 ° etching to the wafer surface for (100) wafer.
FIG. 13 is a sectional view showing a schematic configuration of a quantum effect element according to a third embodiment of the invention.
FIG. 14 is a sectional view showing a schematic configuration of a quantum effect element according to a fourth embodiment of the invention.
FIG. 15 is a sectional view showing a schematic configuration of a quantum effect element according to a fifth embodiment of the invention.
FIG. 16 is a characteristic diagram showing the relationship between gate voltage V and conductance.
FIG. 17 is a characteristic diagram showing a relationship between a source-drain voltage and conductance.
[Explanation of symbols]
3 ... p ^- type substrate 5 ... first n-type delta doped layer 7 ... second n-type delta doped layer 9 ... first p-type delta doped layer 11 ... third n-type delta doped layer 13 ... second p-type delta doped Layer 15 ... Upper p ^- type layer 17 ... Inclined surface 19 ... First n-type implant layer 21 ... Horizontal plane 23 ... Second n-type implant layer 25 ... Lower ohmic contact layer (source)
27. Upper ohmic contact layer (drain)
29 ... SiO ₂ active layer 31 ... Gate electrode 33 ... Wide portion of gate electrode 35 ... Wide portion of gate electrode 37 ... Narrow portion of gate electrode ( constriction region )

Claims (5)

A laminated structure in which a rear barrier confinement potential is formed by the barrier layer by alternately laminating a plurality of second conductivity type layers and a plurality of first conductivity type layers serving as barrier layers ;
An inclined surface formed so as to obliquely traverse the laminated structure, and an end of each layer of the laminated structure is exposed;
An active layer formed to cover the inclined surface, in a plane parallel to the inclined surface, for carriers to flow in the stacking direction of the stacked structure;
A notch formed on the active layer for allowing the carrier to flow beyond the end of each layer of the stacked structure only in the tilt direction defined by the end of each layer of the stacked structure A gate electrode having a constriction region having
A drain at the top of the inclined surface and connected to one of the gate electrodes via an implant layer;
A quantum effect device using a Coulomb brocade formed in the stacked structure, comprising a source below the inclined surface and connected to the other of the gate electrodes via an implant layer. A semiconductor device provided . 2. The semiconductor device according to claim 1, wherein the first conductivity type layer is an impurity layer . 2. The semiconductor device according to claim 1, wherein the active layer includes a constricted region having the same shape as the gate electrode .   2. The semiconductor device according to claim 1, wherein the thickness of the second conductivity type layer is approximately 100 to 400 angstroms. Alternately stacking a plurality of second conductivity type layers and a plurality of first conductivity type layers serving as barrier layers to form a stacked structure in which a rear barrier confinement potential is formed by the barrier layers ; ,
Etching the laminated structure, the steps of the ends of each layer of the laminated structure to expose the inclined surface so as to expose,
Forming an active layer formed by regrowth so as to cover the inclined surface, in a plane parallel to the inclined surface, and for carriers to flow in the stacking direction of the stacked structure;
A notch formed on the active layer for allowing the carrier to flow beyond the end of each layer of the stacked structure only in the tilt direction defined by the end of each layer of the stacked structure Forming a gate electrode with a constriction region having :
The manufacturing method of the semiconductor device provided with the quantum effect element using the Coulomb brocade formed in the said laminated structure characterized by comprising .

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