JPH05218273A - Resin-molded semiconductor device and manufacture of semiconductor chip used therefor - Google Patents
Resin-molded semiconductor device and manufacture of semiconductor chip used thereforInfo
- Publication number
- JPH05218273A JPH05218273A JP4019025A JP1902592A JPH05218273A JP H05218273 A JPH05218273 A JP H05218273A JP 4019025 A JP4019025 A JP 4019025A JP 1902592 A JP1902592 A JP 1902592A JP H05218273 A JPH05218273 A JP H05218273A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- resin
- die pad
- semiconductor device
- pad portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 100
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 claims description 6
- 239000011347 resin Substances 0.000 abstract description 11
- 229920005989 resin Polymers 0.000 abstract description 11
- 238000007789 sealing Methods 0.000 abstract description 9
- 238000000465 moulding Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、極めて薄く構成した
樹脂封止型半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device having an extremely thin structure.
【０００２】[0002]
【従来の技術】従来技術を図４乃至図９を用いて説明す
る。図４は従来技術の第１の例である樹脂封止型半導体
装置を示しており、同図Ａはその平面図、同図Ｂは同図
ＡのＡ−Ａ線上における断面図であり、図５は図４に示
した樹脂封止型半導体装置の代表的な厚さの関係寸法を
示した概念的な断面図である。そして、図６は従来技術
の第２の例である樹脂封止型半導体装置を示しており、
同図Ａはその平面図、同図Ｂは同図ＡのＡ−Ａ線上にお
ける断面図である。そしてまた、図７は従来技術の第３
の例である樹脂封止型半導体装置を示しており、同図Ａ
はその平面図、同図Ｂは同図ＡのＡ−Ａ線上における断
面図である。そして更にまた、図８は従来技術の第４の
例である樹脂封止型半導体装置を示しており、同図Ａは
その平面図、同図Ｂは同図ＡのＡ−Ａ線上における断面
図であって、図９は図８に示した樹脂封止型半導体装置
の代表的な厚さの関係寸法を示した概念的な断面図であ
る。2. Description of the Related Art A conventional technique will be described with reference to FIGS. 4A and 4B show a resin-encapsulated semiconductor device which is a first example of the prior art. FIG. 4A is a plan view thereof, and FIG. 4B is a cross-sectional view taken along line AA of FIG. 5 is a conceptual cross-sectional view showing the relational dimensions of typical thickness of the resin-encapsulated semiconductor device shown in FIG. FIG. 6 shows a second example of the prior art, which is a resin-sealed semiconductor device,
FIG. 3A is a plan view thereof, and FIG. 3B is a sectional view taken along the line AA of FIG. Also, FIG. 7 shows a third example of the prior art.
2 shows a resin-encapsulated semiconductor device which is an example of FIG.
Is a plan view thereof, and FIG. 6B is a sectional view taken along line AA of FIG. Furthermore, FIG. 8 shows a resin-encapsulated semiconductor device which is a fourth example of the prior art. FIG. 8A is a plan view of the same, and FIG. 8B is a sectional view taken along the line AA of FIG. FIG. 9 is a conceptual cross-sectional view showing typical relational dimensions of thickness of the resin-sealed semiconductor device shown in FIG.
【０００３】図４において、符号１はＱＦＰ型の樹脂封
止型半導体装置を示す。この樹脂封止型半導体装置１
は、リードフレームの単一のダイパッド部２に半導体チ
ップＳを搭載する共に、その周辺に配置された各リード
３の内端部とその半導体チップＳの表面に形成された各
電極とを金線やアルミ線などのワイヤ４でボンディング
し、トランスファーモールド方式により封止樹脂５でこ
の半導体チップＳと各リード３の内部を封止した構成に
なっており、この封止樹脂５により各リード３を表面処
理すると共に、所定の形状にリード３を成形して完成品
となる。なお、符号６は半導体チップＳの左右両側で相
対して配置され、左右のリード３の間に存在する一対の
支持リードであり、打ち抜き形成されたものである。In FIG. 4, reference numeral 1 indicates a QFP type resin-sealed semiconductor device. This resin-sealed semiconductor device 1
Mounts the semiconductor chip S on the single die pad portion 2 of the lead frame, and connects the inner end portions of the leads 3 arranged around the die pad portion 2 and the electrodes formed on the surface of the semiconductor chip S with gold wires. The semiconductor chip S and the inside of each lead 3 are sealed by a transfer molding method with a wire 4 such as an aluminum wire or the like, and each lead 3 is sealed with the seal resin 5. The surface is treated and the leads 3 are molded into a predetermined shape to obtain a finished product. Note that reference numeral 6 is a pair of support leads which are disposed on the left and right sides of the semiconductor chip S so as to face each other and are present between the left and right leads 3, and are formed by punching.
【０００４】しかし、このような樹脂封止型半導体装置
１は、図５に示したように、ダイパッド部２の厚みが約
０．１５ｍｍ、半導体チップＳの厚みが約０．４ｍｍ、
ワイヤ４のループの高さが約０．２ｍｍであるため、封
止樹脂５の全体の厚みを１．０ｍｍ以下にしようとする
と、半導体チップＳの上側、及びダイパッド部２の下側
の樹脂の厚みを充分に確保できないという問題があり、
封止樹脂や封止技術を改良しても、樹脂封止型半導体装
置１の全体の厚みを１ｍｍ以下、例えば、０．８ｍｍ程
度まで薄型化できないという問題があった。However, in such a resin-encapsulated semiconductor device 1, as shown in FIG. 5, the die pad portion 2 has a thickness of about 0.15 mm, and the semiconductor chip S has a thickness of about 0.4 mm.
Since the height of the loop of the wire 4 is about 0.2 mm, if the total thickness of the sealing resin 5 is set to 1.0 mm or less, the resin on the upper side of the semiconductor chip S and the resin on the lower side of the die pad portion 2 are There is a problem that the thickness cannot be secured sufficiently,
Even if the sealing resin and the sealing technique are improved, there is a problem that the entire thickness of the resin-sealed semiconductor device 1 cannot be reduced to 1 mm or less, for example, about 0.8 mm.
【０００５】このような問題は、リードフレームのダイ
パッド部２の厚みを薄くするか、半導体チップＳの厚み
を薄くするか、或いはワイヤ４のループ部の高さを低く
すると、一応解決されることになる。Such a problem can be solved by reducing the thickness of the die pad portion 2 of the lead frame, the thickness of the semiconductor chip S, or the height of the loop portion of the wire 4. become.
【０００６】そこで、半導体チップＳの厚みを薄くする
ことを考察すると、その厚みを薄くするためにはウエハ
状態において、その裏面を研磨することが必要になる。
しかし、最近のウエハはその直径が１２．７ｃｍ（５イ
ンチ相当）、または１５．２ｃｍ（６インチ相当）のも
のが多く、これを０．４ｍｍ以下、例えば、０．２ｍｍ
〜０．３ｍｍに研磨すると強度が大幅に低下するため、
その後のそのようなウエハの取扱が困難になるという不
都合が生じる。Therefore, considering the reduction of the thickness of the semiconductor chip S, it is necessary to polish the back surface of the semiconductor chip S in a wafer state in order to reduce the thickness.
However, most of recent wafers have a diameter of 12.7 cm (equivalent to 5 inches) or 15.2 cm (equivalent to 6 inches), which is 0.4 mm or less, for example, 0.2 mm.
Since the strength is greatly reduced when polished to ~ 0.3 mm,
The inconvenience arises that subsequent handling of such wafers becomes difficult.
【０００７】また、ワイヤ４のループ部の高さを低くす
ることについては、半導体チップＳとのエッジタッチや
ボンディングの信頼性の点から０．１５ｍｍが限度であ
り、たとえそのループ部の高さを０．１５ｍｍまで減少
させたとしても、封止樹脂５の全体の厚みを大幅に薄く
することはできない。Further, regarding the height of the loop portion of the wire 4, the height of the loop portion is limited to 0.15 mm from the viewpoint of reliability of edge touch with the semiconductor chip S and bonding. Even if it is reduced to 0.15 mm, the overall thickness of the sealing resin 5 cannot be significantly reduced.
【０００８】[0008]
【発明が解決しようとする課題】そこで、図６に示した
ように、リードフレームのダイパッド部２の中央部を抜
いて枠に構成し、このような枠状のダイパッド部２の下
面部に、例えば、ポリイミドのような薄膜７を被着し、
この薄膜７の上に半導体チップＳを搭載したものや、図
７に示したように、ダイパッド部２をエッチングして、
厚みが薄くなった部分８に半導体チップＳを搭載したも
のや、図８に示したように、前記ダイパッド部２が無い
リードフレームを用いたものが提案されている。Therefore, as shown in FIG. 6, the center portion of the die pad portion 2 of the lead frame is removed to form a frame, and the lower surface portion of the frame-shaped die pad portion 2 is For example, by depositing a thin film 7 such as polyimide,
A semiconductor chip S mounted on the thin film 7 or the die pad portion 2 is etched as shown in FIG.
It has been proposed to mount the semiconductor chip S on the thinned portion 8 or to use a lead frame without the die pad portion 2 as shown in FIG.
【０００９】図９に、後者のダイパッド部２が無いリー
ドフレームを用いた樹脂封止型半導体装置１の構図の断
面図を示したが、この場合、全体の厚みを０．８ｍｍま
で薄くすることができるが、半導体チップＳをワイヤ４
で支えるため、製造しにくいという欠点がある。この発
明は前述した様々な欠点を無くすことを課題とした。FIG. 9 shows a sectional view of the composition of the resin-sealed semiconductor device 1 using the latter lead frame without the die pad portion 2. In this case, the entire thickness should be reduced to 0.8 mm. However, the semiconductor chip S is connected to the wire 4
It is difficult to manufacture because it is supported by. The object of the present invention is to eliminate the various drawbacks described above.
【００１０】[0010]
【課題を解決するための手段】そのため、この発明で
は、ダイパッド部を、例えば、２分割し、且つ狭い面積
で構成し、前記半導体チップの裏面の前記ダイパッド部
で支持される側縁部にそのダイパッド部の厚さ以上の深
さの切り欠きを形成し、このような半導体チップを前記
ダイパッド部に接着、固定して、従来技術のように樹脂
封止した。また、前記の段差は、表面に所定の配列で半
導体集積回路が形成されたウエハの裏面から、それらの
半導体集積回路の中間部で所定の幅で溝を形成し、これ
らの溝の中間部でダイシングすることにより形成した。Therefore, in the present invention, the die pad portion is divided into, for example, two parts and has a small area, and the side edge portion supported by the die pad portion on the back surface of the semiconductor chip is provided. A notch having a depth equal to or larger than the thickness of the die pad portion was formed, and such a semiconductor chip was adhered and fixed to the die pad portion and resin-sealed as in the prior art. Further, the step is formed by forming a groove with a predetermined width in the middle part of the semiconductor integrated circuit from the back surface of the wafer on which the semiconductor integrated circuits are formed in a predetermined arrangement on the front surface, and in the middle part of these grooves. It was formed by dicing.
【００１１】[0011]
【作用】従って、この発明の樹脂封止型半導体装置は、
従来技術のものと比較して大幅に薄型化することができ
る。しかも、樹脂封止される半導体チップも簡単に製造
することができる。Therefore, the resin-sealed semiconductor device of the present invention is
It can be made significantly thinner than that of the prior art. Moreover, a resin-sealed semiconductor chip can be easily manufactured.
【００１２】[0012]
【実施例】以下、この発明の実施例を図１乃至図３を用
いて説明する。図１はこの発明の第１の実施例である樹
脂封止型半導体装置を示しており、同図Ａはその平面
図、同図Ｂは同図ＡのＡ−Ａ線上における断面図であ
り、図２はこの発明の第２の実施例である樹脂封止型半
導体装置の斜視図であり、そして図３はこの発明の樹脂
封止型半導体装置に用いる半導体チップの製造方法を説
明するための一部工程を示す平面図である。なお、図４
乃至図９に示した従来技術の樹脂封止型半導体装置の構
成部分と同一の構成部分には同一の符号を付し、それら
の構成及び機能の説明を省略する。Embodiments of the present invention will be described below with reference to FIGS. 1 to 3. 1 shows a resin-encapsulated semiconductor device according to a first embodiment of the present invention, FIG. 1A is a plan view thereof, and FIG. 1B is a sectional view taken along line AA of FIG. 2 is a perspective view of a resin-sealed semiconductor device according to a second embodiment of the present invention, and FIG. 3 is a diagram for explaining a method of manufacturing a semiconductor chip used in the resin-sealed semiconductor device of the present invention. It is a top view which shows some processes. Note that FIG.
The same components as those of the conventional resin-encapsulated semiconductor device shown in FIG. 9 are designated by the same reference numerals, and the description of their configurations and functions will be omitted.
【００１３】この発明では、従来技術の説明で記したダ
イパッド部２を二分し、ダイパッド部２０Ａ及び２０Ｂ
とした。これらの各ダイパッド部２０Ａ、２０Ｂは、図
１において、半導体チップＳａの左右両側縁部の僅かな
周辺を支持できるだけの矩形状をした微小な面積の金属
板で構成されている。これらのダイパッド部２０Ａ、２
０Ｂは厚さ約０．１５ｍｍの４２アロイやＣｕ系の金属
板を打ち抜いて形成することができる。In the present invention, the die pad portion 2 described in the description of the prior art is divided into two, and die pad portions 20A and 20B are provided.
And Each of these die pad portions 20A and 20B is made of a metal plate having a rectangular area and having a small area capable of supporting a small amount of the periphery of the left and right edges of the semiconductor chip Sa in FIG. These die pad parts 20A, 2
OB can be formed by punching out a 42 alloy or Cu-based metal plate having a thickness of about 0.15 mm.
【００１４】一対の支持リード６は左右のリード３の間
に存在し、そしてそれらのリード３よりも内部へ突出し
て前記両ダイパッド部２０Ａ及び２０Ｂの中央部に連な
り、そして、同図Ｂに示したように、半導体チップＳａ
を封止樹脂５の中の中心に位置するように、下方に折り
曲げられている。これらの支持リード６は、前記ダイパ
ッド部２０Ａ、２０Ｂ及びリード３と共に同時に打ち抜
き形成することができる。A pair of support leads 6 are present between the left and right leads 3, project inward from the leads 3 and are continuous with the central portions of the die pad portions 20A and 20B, and are shown in FIG. As described above, the semiconductor chip Sa
Is bent downward so as to be located in the center of the sealing resin 5. These support leads 6 can be simultaneously punched and formed together with the die pad portions 20A, 20B and the leads 3.
【００１５】一方、この発明に用いられる半導体チップ
Ｓａは、図１Ｂに示したように、その裏面の左右両側縁
部の周辺に、それらの側縁部に沿って微小な幅で、帯状
の切り欠き２１Ａ及び２１Ｂが形成されている。これら
の切り欠き２１Ａ、２１Ｂの深さはダイパッド部２０
Ａ、２０Ｂの厚み以上になるように切り欠かれている。On the other hand, the semiconductor chip Sa used in the present invention, as shown in FIG. 1B, has a strip-shaped cut around the left and right side edges of its back surface with a minute width along those side edges. Notches 21A and 21B are formed. The depth of these notches 21A, 21B is the die pad portion 20.
It is cut out so as to be thicker than A and 20B.
【００１６】このような半導体チップＳａを、その両切
り欠き２１Ａ、２１Ｂが前記ダイパッド部２０Ａ、２０
Ｂに乗るようにしてダイボンドすると、ダイパッド部２
０Ａ、２０Ｂの裏面を半導体チップＳａの裏面と同一面
内に、或いはそれより窪んだ状態にすることができ、図
４及び図５に示したダイパッド部２の半導体チップＳの
裏面に対する出っ張りが無くなり、従って、封止樹脂５
に対して出っ張りを０にすることができる。そして同時
に半導体チップＳａがダイパッド部２０Ａ、２０Ｂに接
着されるため、封止厚方向に安定した状態で封止するこ
とができる。In such a semiconductor chip Sa, both the notches 21A and 21B have the die pad portions 20A and 20B.
When die-bonding so as to ride on B, die pad 2
The back surfaces of 0A and 20B can be in the same plane as the back surface of the semiconductor chip Sa or can be recessed from the back surface, and the protrusion of the die pad portion 2 shown in FIGS. 4 and 5 on the back surface of the semiconductor chip S is eliminated. , Therefore, the sealing resin 5
You can set the protrusion to 0. At the same time, the semiconductor chip Sa is bonded to the die pad portions 20A and 20B, so that the semiconductor chip Sa can be stably sealed in the sealing thickness direction.
【００１７】以下、従来技術と同様に、各リード３の内
端部と半導体チップＳａの表面の各電極とをワイヤ４で
ボンディングし、封止樹脂５でこの半導体チップＳａと
各リード３の内部を封止し、リード３をフォーミングす
ると、この発明の樹脂封止型半導体装置１Ａが完成す
る。Thereafter, as in the prior art, the inner end of each lead 3 and each electrode on the surface of the semiconductor chip Sa are bonded with a wire 4, and the inside of each semiconductor chip Sa and each lead 3 is sealed with a sealing resin 5. And the leads 3 are formed, the resin-sealed semiconductor device 1A of the present invention is completed.
【００１８】図２に、この発明の第２の実施例の樹脂封
止型半導体装置１Ａを示した。この実施例では、両端の
支持リード６が分岐支持リード６Ａ及び６Ｂに分かれて
半導体チップＳａの両側縁部に沿って存在するように掛
け渡した構成にした。この構成は半導体チップＳａの裏
面に２本のリード６Ａ、６Ｂを掛け渡したので、第１の
実施例より、より安定した状態で支持することができ
る。FIG. 2 shows a resin-sealed semiconductor device 1A according to the second embodiment of the present invention. In this embodiment, the support leads 6 at both ends are divided into branch support leads 6A and 6B, and the support leads 6 are provided so as to be present along both side edges of the semiconductor chip Sa. In this configuration, since the two leads 6A and 6B are laid over the back surface of the semiconductor chip Sa, the semiconductor chip Sa can be supported in a more stable state as compared with the first embodiment.
【００１９】次に、図１に示した半導体チップＳａの裏
面に形成した前記切り欠き２１Ａ、２１Ｂは、次のよう
にして形成することができる。図３には、表面に所定の
配列で複数の半導体集積回路が形成された半導体ウエハ
ー３０の裏面の一部分を示した。Next, the notches 21A and 21B formed on the back surface of the semiconductor chip Sa shown in FIG. 1 can be formed as follows. FIG. 3 shows a part of the back surface of the semiconductor wafer 30 having a plurality of semiconductor integrated circuits formed in a predetermined array on the front surface.
【００２０】符号３１は相隣る半導体集積回路の中間を
通る仮想の縦のダイシングラインであり、符号３２は横
のダイシングラインである。これらのダイシングライン
３１、３２で囲まれた半導体ウエハー３０の表面に個々
の半導体集積回路が形成されている。Reference numeral 31 is a virtual vertical dicing line passing through the middle of adjacent semiconductor integrated circuits, and reference numeral 32 is a horizontal dicing line. Individual semiconductor integrated circuits are formed on the surface of the semiconductor wafer 30 surrounded by the dicing lines 31 and 32.
【００２１】それらの個々のダイシングライン３１を中
心にして所定の幅Ｗで、例えば、ダイシングソウで溝３
３を形成し、それらの各溝３３の中間部でダイシングラ
イン３１に沿ってダイシングし、またダイシングライン
３２に沿ってダイシングすると、両側縁部に切り欠き２
１Ａ及び２１Ｂが同時に形成された半導体チップＳａを
取り出すことができる。A groove 3 having a predetermined width W centering on each of the individual dicing lines 31, for example, a dicing saw.
3 is formed and is diced along the dicing line 31 at the middle portion of each of the grooves 33, and when the dicing is performed along the dicing line 32, notches 2 are formed on both side edges.
The semiconductor chip Sa in which 1A and 21B are formed at the same time can be taken out.
【００２２】この溝３３の深さは、例えば、前記の厚み
が約０．１５ｍｍのダイパッド部２０Ａ、２０Ｂを使用
する場合には、約０．１６ｍｍの深さに削り、その幅
は、例えば、２ｍｍで削ると、半導体チップＳａの両側
縁部には深さ約０．１６ｍｍ、幅１ｍｍ以下の切り欠き
２１Ａ、２１Ｂを形成することができる。The depth of the groove 33 is reduced to about 0.16 mm when the die pad portions 20A and 20B having a thickness of about 0.15 mm are used, and the width thereof is, for example, When the semiconductor chip Sa is cut by 2 mm, the notches 21A and 21B having a depth of about 0.16 mm and a width of 1 mm or less can be formed on both side edges of the semiconductor chip Sa.
【００２３】このような溝３３は、必要に応じてダイシ
ングライン３２に沿って形成することもでき、この場合
の半導体チップＳａには、その四側縁部に切り欠きが形
成されることになり、従って、それらの各側縁部を前記
ダイパッド部で支持することができる。Such a groove 33 can be formed along the dicing line 32 if necessary, and in this case, the semiconductor chip Sa has a notch formed at its four side edges. Therefore, the respective side edges thereof can be supported by the die pad portion.
【００２４】前記の実施例では、ＱＦＰ型の樹脂封止型
半導体装置で説明したが、この発明はＱＦＰ型のものだ
けでなく、ＳＯＰ型にも、またＱＦＪ型、ＳＯＪ型な
ど、他の面実装型樹脂封止型半導体装置にも適用するこ
とができることは容易に理解されよう。Although the QFP type resin-sealed semiconductor device has been described in the above embodiments, the present invention is not limited to the QFP type, but may be applied to the SOP type, and other aspects such as the QFJ type and the SOJ type. It will be easily understood that the present invention can also be applied to a mounted resin-sealed semiconductor device.
【００２５】[0025]
【発明の効果】以上のように、この発明の樹脂封止型半
導体装置は、従来技術のものに比較して大幅に薄型化す
ることができ、しかも成形性や信頼性の点でも優れてい
る。また、この樹脂封止型半導体装置に使用する半導体
チップの製造方法も、その製造工程を従来技術のそれに
１工程増やすだけで簡単に、しかも量産できるので、比
較的安価に製造できるという優れた効果がある。As described above, the resin-encapsulated semiconductor device of the present invention can be made significantly thinner than that of the prior art, and is excellent in moldability and reliability. .. In addition, the method of manufacturing a semiconductor chip used for this resin-encapsulated semiconductor device can be easily mass-produced by increasing the manufacturing process by one process as compared with the conventional technique, and thus has an excellent effect that the manufacturing process can be relatively inexpensive. There is.
【図１】この発明の第１の実施例である樹脂封止型半導
体装置を示しており、同図Ａはその平面図、同図Ｂは同
図ＡのＡ−Ａ線上における断面図である。1 shows a resin-encapsulated semiconductor device according to a first embodiment of the present invention, FIG. 1A is a plan view thereof, and FIG. 1B is a sectional view taken along line AA of FIG. ..
【図２】この発明の第２の実施例である樹脂封止型半導
体装置の斜視図である。FIG. 2 is a perspective view of a resin-sealed semiconductor device which is a second embodiment of the present invention.
【図３】この発明の樹脂封止型半導体装置に用いる半導
体チップの製造方法を説明するための一部工程を示す平
面図である。FIG. 3 is a plan view showing a partial process for explaining a method of manufacturing a semiconductor chip used for the resin-sealed semiconductor device of the present invention.
【図４】従来技術の第１の例である樹脂封止型半導体装
置を示しており、同図Ａはその平面図、同図Ｂは同図Ａ
のＡ−Ａ線上における断面図である。4A and 4B show a resin-encapsulated semiconductor device which is a first example of the prior art, where FIG. 4A is a plan view thereof and FIG.
3 is a cross-sectional view taken along line AA of FIG.
【図５】図４に示した樹脂封止型半導体装置の代表的な
厚さの関係寸法を示した概念的な断面図である。5 is a conceptual cross-sectional view showing typical relational dimensions of thickness of the resin-encapsulated semiconductor device shown in FIG.
【図６】従来技術の第２の例である樹脂封止型半導体装
置を示しており、同図Ａはその平面図、同図Ｂは同図Ａ
のＡ−Ａ線上における断面図である。6A and 6B show a resin-encapsulated semiconductor device which is a second example of the prior art. FIG. 6A is a plan view of the same, and FIG.
3 is a cross-sectional view taken along line AA of FIG.
【図７】従来技術の第３の例である樹脂封止型半導体装
置を示しており、同図Ａはその平面図、同図Ｂは同図Ａ
のＡ−Ａ線上における断面図である。7A and 7B show a resin-encapsulated semiconductor device which is a third example of the prior art, where FIG. 7A is a plan view thereof and FIG.
3 is a cross-sectional view taken along line AA of FIG.
【図８】従来技術の第４の例である樹脂封止型半導体装
置を示しており、同図Ａはその平面図、同図Ｂは同図Ａ
のＡ−Ａ線上における断面図である。8A and 8B show a resin-encapsulated semiconductor device which is a fourth example of the prior art, where FIG. 8A is a plan view thereof and FIG.
3 is a cross-sectional view taken along line AA of FIG.
【図９】図８に示した樹脂封止型半導体装置の代表的な
厚さの関係寸法を示した概念的な断面図である。9 is a conceptual cross-sectional view showing typical relational dimensions of thickness of the resin-encapsulated semiconductor device shown in FIG.
１Ａ 樹脂封止型半導体装置 ３ リード ４ ワイヤ ５ 封止樹脂 ６ 支持リード ２０Ａ ダイパッド部 ２０Ｂ ダイパッド部 ２１Ａ 切り欠き ２１Ｂ 切り欠き ３０ 半導体ウエハー ３３ 溝 Ｓａ 半導体チップ 1A Resin-encapsulated semiconductor device 3 Lead 4 Wire 5 Encapsulating resin 6 Support lead 20A Die pad part 20B Die pad part 21A Notch 21B Notch 30 Semiconductor wafer 33 Groove Sa Semiconductor chip
Claims (2)
数のリードとからなるリードフレームの、該ダイパッド
部で半導体チップを支持し、該リードの各内端部と該半
導体チップの各電極とをワイヤボンドし、封止樹脂で前
記半導体チップと前記各リードの内端部とを封止した樹
脂封止型半導体装置において、前記ダイパッド部は前記
半導体チップの裏面の少なくとも２辺の微小な面積の側
縁部を支持できるように構成されており、前記半導体チ
ップの裏面の該側縁部は前記ダイパッド部の厚さ以上の
深さに段差が形成されていることを特徴とする樹脂封止
型半導体装置。1. A semiconductor device is supported by the die pad portion of a lead frame including a die pad portion and a plurality of leads arranged around the die pad portion, and each inner end portion of the lead and each electrode of the semiconductor chip. In a resin-encapsulated semiconductor device in which the semiconductor chip and the inner ends of the leads are encapsulated by wire-bonding, and the die pad portion is a minute area on at least two sides of the back surface of the semiconductor chip. Is formed so as to be able to support the side edge portion of the semiconductor chip, and the side edge portion of the back surface of the semiconductor chip has a step formed at a depth greater than the thickness of the die pad portion. Type semiconductor device.
されたウエハの裏面から、それらの半導体集積回路の中
間部で所定の幅をもって溝を形成し、これらの溝の中間
部でダイシングすることにより、側縁部に段差が形成さ
れた半導体チップを取り出すことを特徴とする、前記請
求項１に記載の樹脂封止型半導体装置に使用し得る半導
体チップの製造方法。2. A groove having a predetermined width is formed at an intermediate portion of the semiconductor integrated circuit from the rear surface of a wafer having semiconductor integrated circuits formed in a predetermined array on the front surface, and dicing is performed at the intermediate portion of these grooves. The method for manufacturing a semiconductor chip usable in the resin-sealed semiconductor device according to claim 1, wherein the semiconductor chip having a step formed on the side edge is taken out.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4019025A JPH05218273A (en) | 1992-02-04 | 1992-02-04 | Resin-molded semiconductor device and manufacture of semiconductor chip used therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4019025A JPH05218273A (en) | 1992-02-04 | 1992-02-04 | Resin-molded semiconductor device and manufacture of semiconductor chip used therefor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05218273A true JPH05218273A (en) | 1993-08-27 |
Family
ID=11987930
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4019025A Pending JPH05218273A (en) | 1992-02-04 | 1992-02-04 | Resin-molded semiconductor device and manufacture of semiconductor chip used therefor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05218273A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7821116B2 (en) | 2007-02-05 | 2010-10-26 | Fairchild Semiconductor Corporation | Semiconductor die package including leadframe with die attach pad with folded edge |
-
1992
- 1992-02-04 JP JP4019025A patent/JPH05218273A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7821116B2 (en) | 2007-02-05 | 2010-10-26 | Fairchild Semiconductor Corporation | Semiconductor die package including leadframe with die attach pad with folded edge |
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