JPH0521795A - Fabrication of thin-film transistor - Google Patents

Abstract

PURPOSE:To effect automatic alignment by using one mask which serves as both a mask for ion implantation and a mask for a second gate formation. CONSTITUTION:A resist is applied over a second conductive film 12. This film is then patterned to form a resist mask 13 for forming a second gate electrode. The resist mask 13 is patterned in a shape matched with a first gate electrode 8. Using the resist mask 13 as a mask, ions are implanted into an operating semiconductor layer 10 through a second conductive film 12 and a second gate dielectric film 11. The region below the mask 13 turns to a channel, and regions on both sides of the channel become a source region and a drain region, respectively. Using the resist mask 13 as a mask, the second conductive film 12 is etched to form a second gate electrode 14. Automatic alignment can be achieved by using the same mask 13 in the formation of both the channel and the second gate electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor, and more particularly to a method of manufacturing a thin film transistor having two gate electrodes sandwiching an operating semiconductor layer.

SR in which resistive load inverter circuits are arranged
AM is widely used. FIG. 4 is a circuit diagram of an SRAM cell including a resistance load inverter circuit, where R is a load resistance,
T ₁ represents a driving transistor and T ₂ represents a transfer transistor.

With the recent high integration of LSIs, TFTs (thin film transistors) are used instead of resistive loads because of the demands for low voltage operation for low power consumption and stable operation of cells.
Introduction of load is being considered.

FIG. 5 shows an S including a TFT load inverter circuit.
RAM circuit schematic, TF with two gate electrodes
T is shown schematically. The TFT has a structure in which two gate electrodes are arranged with an operating semiconductor layer sandwiched therebetween in order to take a large current by driving at a low voltage.

[0005]

SRA including a TFT load inverter circuit
Regarding a conventional example of manufacturing an M cell, the formation of a TFT having two gate electrodes will be mainly described. Since the inverter circuit is symmetrical, the outline of formation of a half (a portion surrounded by a dotted line in FIG. 5) including one TFT and one driving transistor T ₁ will be described.

3 (a) to 3 (e) are process sectional views showing a conventional example, which will be described below with reference to these drawings. See FIG. 3A. The element isolation region 2 is formed on the Si substrate 1 by the LOCOS method. A drive transistor is formed in the element region by a general method. In the figure, 4 is a gate insulating film, 5 is a gate electrode, and 6 is a source / drain.

In order to separate the gate electrode 5 between layers, SiO
_{2 The} film 7 is grown. After opening a window (not shown) for contacting the gate electrode 5 in the SiO ₂ film 7, poly S is formed on the entire surface.
The i film is grown and patterned to form the first gate electrode 8 of the TFT.

Referring to FIG. 3B, a SiO ₂ film 9 is grown as a first gate insulating film on the entire surface. After opening a window in the SiO ₂ film 9 that contacts the node of the drive transistor, an amorphous Si film which will be a channel of the TFT is grown on the entire surface and is patterned to form an operating semiconductor layer 10 of the TFT.

Next, a resist covering the operating semiconductor layer 10 is applied and patterned to form a resist mask 13a covering the channel portion. The resist mask 13a is patterned into a shape overlapping the first gate electrode 8. Ions are implanted into the operating semiconductor layer 10 using the resist mask 13a as a mask to form the source / drain on both sides of the channel.

Referring to FIG. 3C, after removing the resist mask 13a, a SiO ₂ film 11 serving as a _second gate insulating film is grown on the entire surface. After opening a window (not shown) in the SiO ₂ film 11 for contacting the gate electrode 5 of the drive transistor, a poly-Si film 12 is grown as a second conductive film 12 on the entire surface.

A resist is applied on the second conductive film 12, and the resist is patterned to form a resist mask 13b for forming a second gate electrode. Resist mask 13b
Is patterned into a shape overlapping the first gate electrode 8.

Referring to FIG. 3D, the second conductive film 12 is etched by using the resist mask 13b as a mask to form the second gate electrode 14.

Referring to FIG. 3 (e), an SiO ₂ film 15 as an insulating film 15 and a P as an insulating film 16 are formed on the entire surface.
The SG film 16 is sequentially grown. Source of drive transistor
A window for taking out an electrode is opened in the drain region and Al wiring is performed to form a source / drain electrode 17.

By the way, this conventional method has the following problems. When the operating semiconductor layer 10 is ion-implanted using the resist mask 13a as a mask, the operating semiconductor layer 10 is thin, so that the ions penetrate into the base and the operating semiconductor layer
Hard to inject into 10. Even if an attempt is made to reduce the acceleration energy to keep it in the operating semiconductor layer 10, it is difficult to control, and it takes a long time because the injection current cannot be increased.

Since the resist mask 13a is peeled off after the ion implantation, when the resist mask 13b for forming the second gate electrode 14 is formed next, it is difficult to confirm the ion implantation region and the alignment accuracy is improved. Absent.

[0016]

In view of the above problems, the present invention suppresses implanted ions from penetrating the operating semiconductor layer 10 and implants the operating semiconductor layer 10 with high accuracy, and at the same time, the channel portion and the second portion are formed. It is an object of the present invention to provide a method with which the position of the gate electrode can be easily adjusted and the accuracy is high.

[0017]

[Means for Solving the Problems] FIG. 1 (P1) to (P4), (S1) to
(S4) and FIGS. 2 (P5) to (P7), (S5) to (S7) are a process sequence plan view and a cross-sectional view (No. 1) and (No. 2) showing an embodiment.

The above problems are solved by the first gate electrode 8, the first gate insulating film 9, the operating semiconductor layer 10, and the second gate insulating film.
A method of manufacturing a thin film transistor having a structure in which 11 and a second gate electrode 14 are laminated in this order, in which a first conductive film is formed on a substrate whose surface is an insulator 7, and is patterned to form a first conductive film. The step of forming the gate electrode 8 of the above, the step of forming the first gate insulating film 9 on the first gate electrode 8, and the step of forming the first gate insulating film 9 on the first gate electrode 8. The step of forming the operating semiconductor layer 10 extending from the side to the both sides, the step of forming the second gate insulating film 11 and the second conductive film 12 on the operating semiconductor layer 10 in this order, and the step of forming the second conductive film. A step of forming a mask 13 on the film 12 so as to overlap with the first gate electrode 8; and the operation semiconductor layer 10 through the second conductive film 12 and the second gate insulating film 11 using the mask 13 as a mask. After ion implantation into the substrate, the second conductive film 12 is etched using the mask 13 as a mask. And, a second gate electrode 14
This is solved by a method for manufacturing a thin film transistor having a step of forming.

[0019]

According to the present invention, since ion implantation into the operating semiconductor layer 10 is performed through the second conductive film 12 and the second gate insulating film 11, the ion implantation conditions can be set even if the operating semiconductor layer 10 is thin. It becomes easy and accurate injection can be performed.

Since the mask for ion implantation and the mask for forming the second gate electrode are shared, the alignment is automatically performed and the second gate electrode can be accurately formed with respect to the channel. it can.

[0021]

EXAMPLE FIG. 1 (P1)-(P4), (S1)-(S4) and FIG. 2 (P5)-
(P7), (S5) to (S7) are process order plan views and cross-sectional views (No. 1) and (No. 2) showing an embodiment forming a portion surrounded by a dotted line in FIG. Description will be given with reference to these figures.

P1 to P7 are plan views, and S1 to S7 are sectional views taken along the line AA. 1 (P1), (S1). An element isolation region 2 having a thickness of 5000Å is formed on a Si substrate 1 by a LOCOS method to partition the element region 3. A gate insulating film 4 having a thickness of 200Å is formed in the element region 3.

Referring to FIGS. 1 (P2) and 1 (S2), a drive transistor for an inverter is formed in the element region 3 by a general method. In the figure, 5 is a gate electrode and 6 is a source / drain.

See FIGS. 1 (P3) and (S3). The thickness of the gate electrode 5 is separated by CVD in order to separate it from the gate electrode 5.
A 1000 Å SiO ₂ film 7 is grown. After opening a window in the SiO ₂ film 7 for contacting the gate electrode 5, CV is formed on the entire surface.
As the first conductive film 4 by the D method, poly-Si having a thickness of 500 Å
The film is grown and patterned to form the first gate electrode 8 of the TFT. First gate electrode 8 of TFT
Is connected to the gate electrode 5 of the drive transistor.

See FIGS. 1 (P4) and (S4). The thickness of the first gate insulating film 3 is formed on the entire surface by the CVD method.
A 00Å SiO ₂ film 9 is grown. After opening a window in the SiO ₂ film 9 that contacts the node of the drive transistor,
Thickness of 400 Å to be the operating layer of TFT by CVD method on the entire surface
The amorphous Si film is grown and patterned to form the operating semiconductor layer 10.

2 (P5), (S5) See FIG. 2 (P5), (S5).
A 00Å SiO ₂ film 11 is grown. After opening a window for contacting the gate electrode 5 of the drive transistor in the SiO ₂ film 11, a poly-Si film having a thickness of 500 Å is grown as a second conductive film 12 on the entire surface by the CVD method.

Next, a resist is applied on the second conductive film 12 and patterned to form a resist mask 13 for forming a second gate electrode. Resist mask
13 is patterned in a shape overlapping the first gate electrode 8.

Using the resist mask 13 as a mask, ions are implanted into the operating semiconductor layer 10 through the second conductive film 12 and the second gate insulating film 11. The implantation conditions are, for example, ion species BF ⁺ , acceleration energy 20 keV, and dose 1 × 10 ^14.
cm ^-2 . A channel is formed under the mask 13, and source and drain are on both sides of the channel.

Referring to FIGS. 2P6 and 2S6, the second conductive film 12 is etched using the resist mask 13 as a mask to form the second gate electrode 14.

2 (P7), (S7) See FIG. 2 (P7), (S7). As shown in FIG.
As the O ₂ film 15 and the insulating film 16, a PSG film 16 having a thickness of 4000 Å is sequentially grown. A window for taking out an electrode is opened in the source / drain region of the driving transistor, and an Al wiring is used for the source / drain region.
The drain electrode 17 is formed and the process is completed.

As described above, the operating semiconductor layer of the TFT
Ion implantation can be performed accurately. Since the mask 13 is shared by the formation of the channel portion and the formation of the second gate electrode, the alignment is automatically performed and the process is shortened.

Although the operating semiconductor layer 10 is an amorphous Si film in the above example, it is needless to say that a semiconductor film of poly-Si or single crystal Si can be used.

[0033]

As described above, according to the present invention,
It is possible to suppress implantation ions from penetrating the operating semiconductor layer 10 in the formation of the TFT and to perform ion implantation into the operating semiconductor layer 10 with high accuracy. The process is shorter than the conventional method in which the mask is formed twice for the formation of the channel portion and the second gate electrode and the alignment is performed twice, and the alignment is easy and the accuracy is high.

The present invention contributes to improving the performance of a thin film transistor having two gate electrodes, and thus to improving the performance of an inverter circuit having a TFT load, and further improving the performance of an SRAM in which such an inverter circuit is arranged. ..

[Brief description of drawings]

1 (P1) to (P4) and (S1) to (S4) are a process sequence plan view and a cross-sectional view (No. 1) showing an embodiment.

2 (P5) to (P7) and (S5) to (S7) are a process sequence plan view and a cross-sectional view (No. 2) showing an embodiment.

3A to 3E are cross-sectional views in order of the processes, showing a conventional example.

FIG. 4 is a circuit diagram of an SRAM cell including a resistance load inverter circuit.

FIG. 5 is a circuit diagram of an SRAM cell including a TFT load inverter circuit.

[Explanation of symbols]

Reference numeral 1 is a semiconductor substrate, Si substrate 2 is a device isolation region, field insulating film 3 is a device region 4, gate insulating film 5 is a gate electrode, and gate electrode 6 of a driving transistor is a source / drain. The source / drain 7 of the transistor is an insulating film, the SiO ₂ film 8 is the first gate electrode 9 the first gate insulating film, the SiO ₂ film 10 is the operating semiconductor layer, and the amorphous Si film 11 is the first 2 is a gate insulating film, the SiO ₂ film 12 is a second conductive film, the poly-Si films 13, 13a and 13b are masks, the resist mask 14 is a second gate electrode 15 is an insulating film. The SiO ₂ film 16 is an insulating film, the PSG film 17 is the source / drain electrode T _1, the driving transistor T _2, the transfer transistor R is the load resistance, and the TFT is the thin film transistor.

Claims (1)

Claims: 1. A first gate electrode (8), a first gate insulating film (9), an operating semiconductor layer (10), and a second gate insulating film (11).
A method of manufacturing a thin film transistor having a structure in which a second gate electrode (14) and a second gate electrode (14) are laminated in this order, in which a first conductive film is formed on a substrate whose surface is an insulator (7),
Patterning it to form a first gate electrode (8); forming a first gate insulating film (9) on the first gate electrode (8); The first gate electrode (8) on the insulating film (9)
A step of forming an operating semiconductor layer (10) extending from both sides from above, and forming a second gate insulating film (11) and a second conductive film (12) in this order on the operating semiconductor layer (10) And a step of forming a mask (13) on the second conductive film (12) overlapping the first gate electrode (8), and using the mask (13) as a mask After ion-implanting the operating semiconductor layer (10) through the film (12) and the second gate insulating film (11), the second conductive film (12) is formed using the mask (13) as a mask. The second gate electrode (1
A method of manufacturing a thin film transistor, comprising the step of forming 4).