JPH05216985A - Data density conversion circuit - Google Patents

Abstract

PURPOSE:To improve conversion speed by operating a data density conversion by a hardware, in a data density conversion circuit which converts m-bit parallel data into the m-bit parallel data in which one bit data are thinned out at every n-th bit. CONSTITUTION:The m-bit parallel data are converted into serial data by a parallel/serial conversion circuit 1, shifted by each one bit, and transferred to a serial/parallel conversion circuit 2. Then, the transferred data are shifted by each one bit by the serial/parallel conversion circuit 2, converted into the m-bit parallel data, and outputted. At that time, a data shift at the parallel/ serial conversion circuit 1 is operated synchronously with a clock, and the data shift at the serial/parallel conversion circuit 2 is stopped at every n-th bit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data density conversion circuit. A display device or printer such as a CRT or liquid crystal displays or prints an image according to dot data, but when displaying / printing data having different dot densities, or when performing image reduction / enlargement processing even if the dot densities are the same. Must convert the dot data.

[0002]

2. Description of the Related Art Conversion of data density is performed by thinning out data at a constant rate or adding data from parallel data input one after another, for example, 8-bit parallel data. FIG. 6 shows an example of patterns before and after data density conversion. The pattern in the figure shows the data density in dpi indicating the number of data per inch, and when converting from 240 dpi to 160 dpi, the 8-bit parallel data that is input one after another is
When converting every 3rd bit into data with 1 bit thinned out, and when converting from 160dpi to 240dpi, the 8bit parallel data that is input one after another is converted into 1bit for every 3rd bit. Convert minute data to added data. The numbers shown in the figure are given to distinguish individual data. Of the data before conversion, 8 pieces of data from number 1 to number 8 enclosed by the dotted line in the figure are input first, 8-bit parallel data, and pieces of data after number 9 are input 8-bit parallel. Data ... is shown. As can be seen in the figure, the 8-bit parallel data after conversion is data in which data is thinned out every 3rd bit or data is added every 3rd bit.

Conventionally, the above conversion was performed by causing the MPU to execute a program for data density conversion. The program is composed of an instruction for shifting a certain amount of data and a repeating instruction for thinning or adding data at each data shift.

[0004]

The method of converting the data density by software has the advantage that no special circuit needs to be provided, but since the number of data representing a pattern is generally enormous, the number of instructions also increases. It becomes enormous. Therefore, there is a problem that the conversion process requires a long time, and the printing speed of the printer is reduced or the drawing speed of the display device is reduced.

Therefore, an object of the present invention is to improve conversion speed by performing data density conversion by hardware.

[0006]

A solution to the above problems is a data density conversion circuit for converting m-bit parallel data into m-bit parallel data in which 1-bit data is thinned out every nth bit. , A parallel-serial conversion circuit 1 for converting m-bit parallel data into serial data and then shifting by 1 bit in synchronization with a clock, and data transferred from the parallel-serial conversion circuit 1 in synchronization with a clock by 1 bit Serial-to-parallel conversion circuit 2 for converting to m-bit parallel data
An input control circuit 3 for inputting new m-bit parallel data to the parallel-serial conversion circuit 1 when the amount of data shift in the parallel-serial conversion circuit 1 becomes m bits; and a data shift in the serial-parallel conversion circuit 2. A shift control circuit 4 for stopping every nth bit and an output control circuit 5 for outputting m-bit parallel data from the serial-parallel conversion circuit 2 when the data shift amount in the serial-parallel conversion circuit 2 becomes m bits. A data density conversion circuit characterized by being provided, or a data density conversion circuit for converting m-bit parallel data into m-bit parallel data in which 1-bit data is added for every n-th bit. A parallel-to-serial conversion circuit 1 for converting bit-parallel data into serial data and then shifting by 1 bit in synchronization with a clock, and transferred from the parallel-to-serial conversion circuit 1. A serial-parallel conversion circuit 2 for converting data into 1-bit parallel data after shifting by 1 bit in synchronization with a clock, and a parallel-serial conversion circuit 1 when the data shift amount in the parallel-serial conversion circuit 1 becomes m bits. Input control circuit 3 for inputting new m-bit parallel data to
A shift control circuit 4 for stopping the data shift in the parallel-serial conversion circuit 1 every nth bit, and the serial-parallel conversion circuits 2 to m when the data shift amount in the serial-parallel conversion circuit 2 becomes m bits. This is achieved by a data density conversion circuit having an output control circuit 5 for outputting bit parallel data.

[0007]

1 is a block diagram showing the principle of the present invention.
When converting m-bit parallel data into m-bit parallel data in which 1-bit data is thinned out every nth bit, the m-bit parallel data input to the parallel-serial conversion circuit 1 is converted into serial data. After that, the data is shifted bit by bit in synchronization with the clock and transferred to the serial-parallel conversion circuit 2. Then, in the serial-parallel conversion circuit 2, the data shift is stopped every nth bit in synchronization with the signal from the shift control circuit 4. Therefore, the n-th bit data of the transferred data is the serial-parallel conversion circuit 2
Will not be entered in. That is, the serial-parallel conversion circuit 2 receives the data obtained by thinning out 1-bit data for every n bits. In addition, the parallel-serial conversion circuit 1
When the amount of data shift in m becomes m bits, the m-bit parallel data initially set in the parallel-serial conversion circuit 1 is all transferred by shift, and the amount of data shift in the serial-parallel conversion circuit 2 becomes m bits. When this happens, the m-bit data has been set in the serial-parallel conversion circuit 2. Therefore, by inputting data to the parallel-serial conversion circuit 1 and outputting data from the serial-parallel conversion circuit 2 in synchronization with the signals from the input control circuit 3 and the output control circuit 5, m is input one after another. This means that m-bit parallel data in which 1-bit data is thinned out every nth bit from the bit-parallel data is output.

Further, in the case of converting m-bit parallel data into m-bit parallel data in which 1-bit data is added for every n-th bit, the data shift in the parallel-serial conversion circuit 1 is input in the above configuration. If the data is shifted in the serial-parallel conversion circuit 2 in synchronism with the signal of the control circuit 3 every n-th bit, and the data is shifted in the serial-parallel conversion circuit 2 in synchronism with the clock, the serial-parallel conversion circuit 2 has the n-th bit. Data in which the previous bit is repeated is input for each, and therefore, m-bit parallel data in which 1-bit data is added every nth bit from the m-bit parallel data that is input sequentially is output. Can be made

[0009]

1 is a circuit diagram showing a first embodiment of the present invention,
FIG. 3 is a timing chart in the first embodiment. In this embodiment, 8-bit parallel data sequentially input from an MPU (not shown) is converted into 8-bit parallel data in which one bit of data is thinned out every third bit and then output. Further, it is assumed that the clock and the start signal are sent from the MPU together with the 8-bit parallel data.

In FIG. 2, the parallel-serial conversion circuit has eight A's.
It comprises an ND gate 11 and an 8-bit shift register 12.
When the AND gate 11 is turned on by the signal a,
The 8-bit parallel data input from the MPU is set in the shift register 12. The data set in the shift register 12 is shifted bit by bit in the arrow direction in synchronism with the clock and is sequentially sent to the serial-parallel conversion circuit.

The serial-parallel conversion circuit comprises an 8-bit shift register 14 and eight AND gates 15. Shift register
The data transferred from 12 is input to the shift register 14, and when the signal b is "1", it is set to 1 in the direction of the arrow by the clock.
It is shifted bit by bit. AND with signal c
It is output to the outside when the gate 15 is turned on.

The signals a, b and c are supplied by the input control circuit, shift control circuit and output control circuit described below.
The input control circuit comprises an OR gate 16 and an octal counter 17. The OR gate 16 has a start signal and an octal counter 17
Carry signal is input and the output is ANDed as signal a
Sent to gate 11. Further, the octal counter 17 starts counting clocks when a start signal arrives. With the above configuration, the AND gate 11 is turned on by the arrival of the start signal, the first 8-bit parallel data is set in the shift register 12, and the octal counter 17 starts counting the clock. Since the data set in the shift register 12 is shifted bit by bit in the arrow direction in synchronization with the clock, all the data in the shift register 12 is discharged at the 8th count after the start signal is input. Then, the carry signal output from the octal counter 17 sets the next 8-bit parallel data in the shift register 12.

The shift control circuit includes a ternary counter 18, NOT
It is composed of a gate 19 and an AND gate 13.
The ternary counter 18 starts counting clocks with the arrival of the start signal and outputs a carry signal at every third count. The carry signal is inverted by the NOT gate 19 and sent to the AND gate 13, and the data shift in the shift register 14 is controlled by the output signal b of the AND gate 13. That is, when b = “1”, the data is shifted, and when b = “0”, the data shift is stopped.
Therefore, the shift of the data in the shift register 14 is stopped every time the carry signal of the ternary counter 18 is output.
Therefore, the data transferred from the shift register 12 is not input to the shift register 14 every third bit, and as a result, the data of the third bit is thinned out and input to the shift register 14 in the arrow direction. It will be shifted.

The output control circuit comprises an octal counter 20. The octal counter 20 starts counting the clock with the arrival of the start signal, but stops counting the clock every time the carry signal is output from the ternary counter 18. Therefore, when the net data shift amount in the shift register 14 reaches 8 bits, the carry signal of the octal counter 20 is output, and at this time, 8 bits of data are set in the shift register 14. .. Therefore, the carry signal of the octal counter 20 is used as the signal c.
By sending the data to the ND gate 15 and turning it on, 8-bit parallel data is output from the shift register 14.

By repeating the same process thereafter, it is possible to convert 8-bit parallel data input one after another into 8-bit parallel data thinned out every third bit and output it.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention. Components having the same functions as those in FIG. 2 are designated by the same reference numerals. FIG. 5 is a timing chart in the second embodiment. In this embodiment, 8-bit parallel data sequentially input from the MPU is converted into 8-bit parallel data in which 1-bit data is added every third bit and then output. Further, it is assumed that the clock and the start signal are sent from the MPU together with the 8-bit parallel data.

In FIG. 4, the parallel-serial conversion circuit includes eight A's.
It consists of ND gate 11 and 8-bit shift register 12,
When the AND gate 11 is turned on by the signal a,
The 8-bit parallel data input from the MPU is set in the shift register 12. The data set in the shift register 12 is shifted bit by bit in the direction of the arrow by the clock when the signal b = "1", and is sequentially sent to the serial-parallel conversion circuit.

The serial-parallel conversion circuit comprises an 8-bit shift register 14 and eight AND gates 15. Shift register
The data transferred from 12 is input to the shift register 14 and is shifted by 1 bit in the arrow direction in synchronization with the clock. When the AND gate 15 is turned on by the signal c, it is output to the outside.

The signals a, b and c are supplied by the input control circuit, shift control circuit and output control circuit described below.
The input control circuit comprises an OR gate 16 and an octal counter 17. The OR gate 16 has a start signal and an octal counter 17
Carry signal is input and the output is AN as signal a
It is sent to the D gate 11. The octal counter 17 starts counting clocks when the start signal arrives, but stops counting clocks each time a carry signal is output from the ternary counter 18. Therefore, the shift register 12 described later
The carry signal of the octal counter 17 is output when the net data shift amount at 8 is 8 bits, and at this time, all the data set in the shift register 12 is discharged. Therefore, by sending the carry signal of the octal counter 17 to the AND gate 11 to turn it on, the next 8-bit parallel data is set in the empty shift register 12.

The shift control circuit comprises a ternary counter 18, NOT
It is composed of a gate 19 and an AND gate 13.
The ternary counter 18 starts counting clocks with the arrival of the start signal and outputs a carry signal at every third count. This carry signal is inverted by the NOT gate 19 and sent to the AND gate 13. The output signal b of the AND gate 13 controls the data shift in the shift register 12. That is, when b = “1”, the data is shifted, and when b = “0”, the data shift is stopped.
Therefore, every time the carry signal of the ternary counter 18 is output, the shift of the data in the shift register 12 is stopped.
On the other hand, since the shift register 14 shifts the data in synchronization with the clock, the previous data is continuously input to the shift register 14 every 3rd bit of the data transferred from the shift register 12, and is sequentially input in the arrow direction. Will be shifted to.

The output control circuit comprises an octal counter 20. The octal counter 20 starts counting clocks when a start signal arrives. On the other hand, since the data input to the shift register 14 is shifted bit by bit in the direction of the arrow in synchronization with the clock, the data shift amount in the shift register 14 becomes 8 bits at the 8th count after the start signal is input. The carry signal of the counter 20 is output. Therefore, by sending the carry signal of the octal counter 20 to the AND gate 15 as the signal c to turn it on, 8-bit parallel data can be output from the shift register 20.

By repeating the same process thereafter, 8
It is possible to convert the bit parallel data into 8-bit parallel data in which 1-bit data is added for every 3rd bit and output.

As is apparent from the above-mentioned embodiment, the present invention can be applied to the case of thinning out or adding the data for every arbitrary number of bits from the parallel data of the arbitrary number of bits.

[0024]

As described above, according to the present invention, the data density can be converted only by hardware, which is useful for improving the conversion speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of the present invention,

FIG. 2 is a circuit diagram showing a first embodiment,

FIG. 3 is a timing chart showing the first embodiment,

FIG. 4 is a circuit diagram showing a second embodiment,

FIG. 5 is a timing diagram showing a second embodiment,

FIG. 6 is a diagram showing patterns before and after data density conversion,

[Explanation of symbols]

1 parallel-serial conversion circuit, 5 shift control circuit, 2
Data transfer circuit, 6 output control circuit, 3 serial-parallel conversion circuit, 11, 13, 15 AND gate, 4
Input control circuit, 12, 14 shift register,
16 OR gate, 18 ternary counter, 17,
20 octal counter, 19 NOT gate,

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location B41J 5/30 Z 8907-2C G09G 5/36 9177-5G H04N 1/387 101 4226-5C // G06F 5/00 E 9189-5B

Claims (2)

[Claims] 1. A data density conversion circuit for converting m-bit parallel data into m-bit parallel data in which 1-bit data is thinned out every nth bit, and the m-bit parallel data is converted into serial data. After that, a parallel-serial conversion circuit that shifts by 1 bit in synchronization with the clock
(1), a serial-parallel conversion circuit (2) for converting the data transferred from the parallel-serial conversion circuit (1) into m-bit parallel data after shifting by 1 bit in synchronization with a clock, and the parallel-serial conversion In the input control circuit (3) for inputting new m-bit parallel data to the parallel-serial conversion circuit (1) when the data shift amount in the circuit (1) becomes m bits, and in the serial-parallel conversion circuit (2) A shift control circuit (4) for stopping the data shift every nth bit, and an m-bit parallel circuit from the serial-parallel conversion circuit (2) when the data shift amount in the serial-parallel conversion circuit (2) becomes m bits. A data density conversion circuit comprising an output control circuit (5) for outputting data. 2. A data density conversion circuit for converting m-bit parallel data into m-bit parallel data in which 1-bit data is added every nth bit, wherein the m-bit parallel data is converted into serial data. A parallel-serial conversion circuit that shifts by 1 bit in synchronization with the subsequent clock
(1), a serial-parallel conversion circuit (2) for converting the data transferred from the parallel-serial conversion circuit (1) into m-bit parallel data after shifting by 1 bit in synchronization with a clock, and the parallel-serial conversion An input control circuit (3) for inputting new m-bit parallel data to the parallel-serial conversion circuit (1) when the data shift amount in the circuit (1) becomes m bits, and an input control circuit (3) for the parallel-serial conversion circuit (1). A shift control circuit (4) for stopping the data shift every nth bit, and an m-bit parallel circuit from the serial-parallel conversion circuit (2) when the data shift amount in the serial-parallel conversion circuit (2) becomes m bits. A data density conversion circuit comprising an output control circuit (5) for outputting data.