JPH0225347A - Data density conversion control circuit - Google Patents

Abstract

PURPOSE:To control the conversion of image data density using hardware and make possible the acceleration of printing speed of a printer by providing an image data transfer section, a counter group, the first and second clock control devices, a data control/composition device and a shift register. CONSTITUTION:If a SEF signal from a data writing section 7 is HIGH, a transfer clock pulse is entered into a base-N counter 2, a base-(N+1) counter 3 and a base-(N+2) counter, and the counter 2 generates a carry signal with the N-1st clock pulse and the counter 3 generates the carry signal with the Nth clock pulse. The carry output is entered into a clock control circuit 5 to control the clock pulse to be connected to a shift register 8 and data B is retained by a data control circuit 6 without being transferred to the shift register 8, if the Nth clock pulse is generated. With the N+1st clock pulse, the N+1st data C and data B retained by the control circuit 6 are ORed by a data composition circuit 9.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to image reduction by dot density conversion of a printed output image, and particularly to density conversion control in which data is thinned out for each arbitrary pulse train.

(Prior Art) Conventionally, image reduction by dot density conversion of a printout image has been done by a program.

(Problems to be Solved by the Invention) Since the conventional dot density conversion described above is based on program processing, it has the disadvantage that it takes a long time and reduces the printing speed of the printer.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data density conversion control circuit that eliminates the above-mentioned drawbacks by performing data density conversion control of image data using hardware, and is configured so as not to reduce the printing speed of a printer.

(Means for Solving the Problems) A data density conversion control circuit according to the present invention includes an image data transfer section, a counter group, a first clock control means, a data control/synthesis means, a shift register, a second This configuration includes clock control means.

The image data transfer unit is for transferring image data.

The counter groups each include N-ary, N+1-ary, and N-) binary counters, and are used to generate a clock for thinning out image data every arbitrary number of data.

The first clock control means is for supplying a clock for thinning data to the counter group.

The data control/synthesizing means is for thinning out the image data sent from the image data transfer section into arbitrary data numbers based on the clock output of the counter group.

The shift register is used to sequentially store data thinned out and output from the data control/synthesizing means.

The second clock control means is for supplying a clock corresponding to the thinned out data to the shift register.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a data density conversion control circuit according to the present invention.

In FIG. 1, 1 is an image data transfer unit, 2 is an N-ary counter, 3 is an N+1-ary counter, 4 is an N+2-ary counter,
5 is a clock control circuit, 6 is a data control circuit, 7 is a data writing section, 8 is a shift register group, 9 is a data synthesis circuit, and 10 is a clock control circuit. Further, in the clock control circuit 5, 51 is a free lag flop, 52 is an A
It is an ND gate.

FIG. 2 is a time chart showing the operation of each part of the data density conversion control circuit shown in FIG.

FIG. 3 is an explanatory diagram showing an output image reduced in size by density conversion.

The data density conversion control circuit according to the present invention controls the image data sent from the data transfer section by thinning it into arbitrary data numbers.

In FIG. 3, (a) is image data before conversion, and (b) is converted image data.

The explanation will be given below with reference to FIGS. 1 to 3.

In order to thin out data every arbitrary number of data, the data writing section 7 writes desired values into the N-ary counter 2, the N+1-ary counter 3, and the N+2-ary counter 4, respectively. At the same time, image data is input from the data transfer unit 1 to the data control unit 6, and the image transfer is locked by the clock control circuit 5.
Enter each into ゜10.

Next, as shown in FIG.
By controlling the L signal, when the SEL signal is high level, the transfer lock is applied to each N-ary counter 2. N
The signal is input to the +1-base counter 3 and the N+2-base counter, and the N-base counter 2 generates a carry signal at the N-1st clock, and the N+1-base counter 3 generates a carry signal at the Nth clock.

Therefore, the carry output is input to the clock control circuit 5, and the clock connected to the shift register 8 is controlled during the period T shown in the time chart, and data B is not transferred to the shift register 8 at the Nth clock.

Data B to be transferred at the Nth clock is held in the data control circuit 6 by the carry signal of the N-ary counter 2. At the next N+1 clock pulse, N+
Data C sent first and data B held in data control circuit 6 are ORed by data synthesis circuit 9.

As a result of the above, data B1C is sent to the shift register 8, and the data is thinned out.

As a result, the original image data is reduced and output as shown in FIG.

When the SEL signal is at a low level, the transfer lock is not supplied to any of the N-ary counter 2, the N+1-ary counter 3, and the N+2-ary counter 4, so that data is not thinned out. Therefore, only image data synchronized with the transfer lock is supplied to the shift register group 8, and data that has not been density-converted is transferred.

(Effects of the Invention) As described above, the present invention has the advantage that the printing speed of the printer can be increased by controlling data density conversion of image data using hardware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a data density conversion control circuit according to the present invention. FIG. 2 is a time chart showing signals of each part in FIG. 1. FIG. 3 is an explanatory diagram showing the effect of image data density conversion according to the present invention. Image data transfer unit 2...N-ary counter 3...N+1-ary counter 4...N+2-ary counter 5...Clock control circuit 6...Data control circuit 7...Data writing 4 Section 8...Shift register 9...Data synthesis circuit 10...Clock control circuit 51...Free lag flop 52...AND gate

Claims (1)

[Claims] an image data transfer unit for transferring image data; a group of counters each including N-ary, N+1-ary, and N+2-ary counters for generating a clock for thinning out the image data every arbitrary number of data; A first clock for supplying a clock for thinning out the data to the counter group.
a clock control means, a data control/synthesis means for thinning out the image data sent from the image data transfer unit according to the clock output of the counter group into the arbitrary number of data; A shift register for sequentially storing thinned and output data; and a second clock control means for supplying the shift register with a clock corresponding to the thinned out data. A data density conversion control circuit comprising: