JPS6399963A - Printing control circuit - Google Patents

Printing control circuit

Info

Publication number
JPS6399963A
JPS6399963A JP61247070A JP24707086A JPS6399963A JP S6399963 A JPS6399963 A JP S6399963A JP 61247070 A JP61247070 A JP 61247070A JP 24707086 A JP24707086 A JP 24707086A JP S6399963 A JPS6399963 A JP S6399963A
Authority
JP
Japan
Prior art keywords
signal
register
output
gate circuit
dots
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61247070A
Other languages
Japanese (ja)
Other versions
JPH0661956B2 (en
Inventor
Shinichi Hori
堀 新一
Hidejiro Ueyama
植山 秀二郎
Masayuki Suzuki
正幸 鈴木
Daisuke Yagi
大亮 八木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Platforms Ltd
NEC Corp
Original Assignee
NEC Corp
NEC AccessTechnica Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC AccessTechnica Ltd filed Critical NEC Corp
Priority to JP61247070A priority Critical patent/JPH0661956B2/en
Publication of JPS6399963A publication Critical patent/JPS6399963A/en
Publication of JPH0661956B2 publication Critical patent/JPH0661956B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/22Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of impact or pressure on a printing material or impression-transfer material
    • B41J2/23Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of impact or pressure on a printing material or impression-transfer material using print wires
    • B41J2/30Control circuits for actuators

Abstract

PURPOSE:To reduce processing time for software and improve the execution of printing speed by performing a thinning-out operation on continuous dot information by using hardware. CONSTITUTION:A dot information signal 10 is entered into a register 1 through a gate circuit 2, and another input signal through the gate circuit 2 is a signal which has passed through a gate circuit 3 with a high-speed printing mode control signal 14. If said signal is in 'active' state, the logic of contents stored in the register 1 is reversed and output, then it is subjected to a logic product arithmetic operation with a signal 10 at the gate circuit 2 and input in the register 1. Output data 11 from the gate circuit 2 contain no dots, if an output from the register 1 indicates contained dots, and also the signal 10 indicates contained dots. On the other hand, the output of the gate circuit 2 contains the same as the signal 10, if the output of the register 1 indicates no contained dots. The register 1 maintains the output of the gate circuit 2 and said output is used as a head drive signal. The operation is performed in accordance with a signal 12, and the signal 10 is temporarily stored by the register 1. At the same time, the signal 10 is compared to a next signal to thin out dots and the thinned-out dots are output as non-continuous dot information.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ドツトマトリックスプリンタに用いられる印
字制御回路に関する。特に、印字ヘッドの応答周波数の
2倍の印字速度を可能にする印字制御回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a print control circuit used in a dot matrix printer. In particular, the present invention relates to a print control circuit that enables a print speed that is twice the response frequency of a print head.

〔概要〕〔overview〕

本発明は、ドツトマトリックスプリンタに用いれる印字
制御回路において、 ハードウェアを用いて連続するドツト情報を間引きする
ことにより、 印字の画質をやや犠牲にしても、印字速度を向上させる
ようにしたものである。
The present invention uses hardware to thin out consecutive dot information in a print control circuit used in a dot matrix printer, thereby improving printing speed even at the expense of some print quality. be.

〔従来の技術〕[Conventional technology]

従来、高速印字モードの印字は、ソフトウェアで印字文
字パターンの連続するドツトを検出して連続するドツト
を間引きする処理を行い、非連続の印字文字パターンと
して行っていた。また、この処理は1カラムの印字ごと
にもしくは印字開始前に1行単位に行っていた。
Conventionally, printing in high-speed printing mode has been performed using software to detect consecutive dots in a printed character pattern and thin out the consecutive dots, resulting in a non-continuous printed character pattern. Further, this process is performed every time one column is printed or one line before printing starts.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

このように、従来例では、−行印字開始直前もしくは印
字中にドツト情報と次のドツト情報とをソフトウェアを
用いて演算して連続ドツトを検出しているので、ソフト
ウェアの処理時間が長くなり、実行印字速度が低下する
欠点がある。
In this way, in the conventional example, continuous dots are detected by calculating the dot information and the next dot information using software immediately before or during printing of the - line, which increases the processing time of the software. The disadvantage is that the actual printing speed decreases.

また、高速印字になるに伴いソフトウェアの処理時間が
プリンタの印字速度の制約条件になり、ソフトウェアの
処理時間を短くする必要が生じているが、これが容易に
実現できず印字速度を制約する欠点がある。
In addition, as high-speed printing becomes faster, software processing time becomes a constraint on the printer's printing speed, and there is a need to shorten the software processing time, but this cannot be easily achieved and has the disadvantage of limiting printing speed. be.

本発明は、このような欠点を除去するもので、ソフトウ
ェアに代わりハードウェアを用いて連続ドツト情報の間
引き処理が行える印字制御回路を提供することを目的と
する。
SUMMARY OF THE INVENTION The present invention aims to eliminate such drawbacks and provides a print control circuit that can thin out continuous dot information using hardware instead of software.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、ドツトマトリックスプリンタに与えるドソ°
ト情報を前処理する印字制御回路において、上記ドツト
マトリックスプリンタに出力するドツト情報の有無状態
を一時記憶するレジスタと、この出力するドツト情報お
よびこのレジスタにひきつづき入力するドツト情報がと
もに有状態のときに、この入力するドツト情報を無状態
に変更する論理演算手段と、この論理演算手段の出力を
上記レジスタの入力に接続する接続手段とを備えたこと
を特徴とする。
The present invention provides a dot matrix printer with a
In a print control circuit that preprocesses dot information, when a register that temporarily stores the presence/absence status of dot information to be output to the dot matrix printer, and both this output dot information and the dot information subsequently input to this register are in the presence state. The present invention is characterized in that it comprises a logic operation means for changing the input dot information to no state, and a connection means for connecting the output of the logic operation means to the input of the register.

〔作用〕[Effect]

レジスタに記憶された一つ前のドツト情報とひきつづき
レジスタに入力するドツト情報とを照合して、ともにド
ツトが有のときは、この新たに入力するドツト情報の入
力を禁止してレジスタにはドツト情報を無として記憶さ
せる。レジスタに記憶されたドツト情報がドツトマトリ
ックスプリンタに送出される。これにより、印字画質を
やや犠牲にしても、同種のメカニズムを使用して印字速
度を2倍にすることができる。
The previous dot information stored in the register is compared with the dot information subsequently input to the register, and if there is a dot in both, the input of this newly input dot information is prohibited and no dots are added to the register. Memorize information as nothing. The dot information stored in the register is sent to the dot matrix printer. This allows the same type of mechanism to be used to double the printing speed, at the expense of some print quality.

〔実施例〕〔Example〕

以下、本発明の実施例回路を図面に基づいて説明する。 DESCRIPTION OF THE PREFERRED EMBODIMENTS A circuit according to an embodiment of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例回路の構成を示す回路接続図
であり、印字ヘッドにおけるワイヤ1本当たりの回路図
である。この回路は、レジスタ1と、ゲート回路2と、
ゲート回路3とを備え、ドツト情報信号10は、文字ド
ツトパターンのN番ピンのドツトに対応した信号であり
、ドツトの有無を示し、出力データタイミング信号12
は、印字速度に対応した所定の周期を有し、ドツトパタ
ーンを横方向にスキャンする信号であり、レジスタ1へ
の入出力を制御し、高速印字モード制御信号14は、こ
の回路のアクティブ(3号である。
FIG. 1 is a circuit connection diagram showing the configuration of a circuit according to an embodiment of the present invention, and is a circuit diagram for one wire in a print head. This circuit includes a register 1, a gate circuit 2,
The dot information signal 10 is a signal corresponding to the dot of the Nth pin of the character dot pattern, and indicates the presence or absence of a dot, and the output data timing signal 12
is a signal that has a predetermined period corresponding to the printing speed and scans the dot pattern in the horizontal direction, and controls the input/output to the register 1, and the high-speed printing mode control signal 14 is the signal that This is the number.

さて、ドツト情報信号lOはゲート回路2を介してレジ
スタ1に入力する。ゲート回路2の他の一方の入力信号
はレジスタ1の出力高速印字モード制御信号14とを入
力とするゲート回路3を介した信号であり、この信号は
、高速印字モード制御信号14がアクティブ状態となっ
ているときに、レジスタ1に記憶されていく内容の論理
が反転して出力し、ゲート回路2でドツト情報信号10
と論理積演算されてレジスタ1に入力する。ゲート回路
2からの出力データ11は、レジスタ1の出力がドツト
有りを示しかつドツト情報信号10がドツト有りを示す
ときに、ドツト無しになり、また、レジスタ1の出力が
ドツト無しを示すときに、ドツト情報信号10と同一の
内容になる。レジスタlは、ゲート回路2の出力を保持
するレジスタであり、出力はヘッド駆動用信号として使
用される。この動作は出力データタイミング信号12に
応じて行われ、連続するドツト情報信号10をレジスタ
1により一時記憶し、次のドツト情報信号10と比較す
ることで、ドツトを間引きし、非連続のドツト情報とし
て出力する。
Now, the dot information signal lO is input to the register 1 via the gate circuit 2. The other input signal of the gate circuit 2 is a signal passed through the gate circuit 3 which receives the output high-speed printing mode control signal 14 of the register 1, and this signal is transmitted when the high-speed printing mode control signal 14 is in the active state. , the logic of the contents stored in the register 1 is inverted and output, and the gate circuit 2 outputs the dot information signal 10.
is ANDed and input to register 1. The output data 11 from the gate circuit 2 becomes no dot when the output of the register 1 indicates the presence of a dot and the dot information signal 10 indicates the presence of a dot, and when the output of the register 1 indicates the absence of a dot. , has the same content as the dot information signal 10. Register l is a register that holds the output of gate circuit 2, and the output is used as a head drive signal. This operation is performed in accordance with the output data timing signal 12, and the continuous dot information signal 10 is temporarily stored in the register 1, and is compared with the next dot information signal 10 to thin out the dots and remove the discontinuous dot information. Output as .

なお第2図は、この回路の動作を示すタイミングチャー
トであり、第3図に示すドツト情報が入力された場合を
示す。
Note that FIG. 2 is a timing chart showing the operation of this circuit, and shows the case where the dot information shown in FIG. 3 is input.

〔発明の効果〕〔Effect of the invention〕

本発明は、以上説明したように、ハードウェアを用いて
連続するドツト情報を間引きする処理を行うことにより
ソフトウェアの処理時間を軽減することができるので、
実行印字速度を向上させる効果がある。
As explained above, the present invention can reduce software processing time by thinning out consecutive dot information using hardware.
This has the effect of improving the actual printing speed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明実施例回路の構成を示す回路接続図。 第2図は本発明実施例回路の動作を示すタイミングチャ
ート。 第3図は本発明実施例回路の作用を示す説明図。 1・・・レジスタ、2.3・・・ゲート回路、10・・
・ドツト情報信号、11・・・出力データ、12・・・
出力データタイミング信号、13・・・リセット信号、
14・・・高速印字モード制御信号。
FIG. 1 is a circuit connection diagram showing the configuration of a circuit according to an embodiment of the present invention. FIG. 2 is a timing chart showing the operation of the circuit according to the embodiment of the present invention. FIG. 3 is an explanatory diagram showing the operation of the circuit according to the embodiment of the present invention. 1...Register, 2.3...Gate circuit, 10...
・Dot information signal, 11... Output data, 12...
Output data timing signal, 13...reset signal,
14...High-speed printing mode control signal.

Claims (1)

【特許請求の範囲】[Claims] (1)ドットマトリックスプリンタに与えるドット情報
を前処理する印字制御回路において、 上記ドットマトリックスプリンタに出力するドット情報
の有無状態を一時記憶するレジスタ(1)と、 この出力するドット情報およびこのレジスタにひきつづ
き入力するドット情報がともに有状態のときに、この入
力するドット情報を無状態に変更する論理演算手段(3
)と、 この論理演算手段の出力を上記レジスタの入力に接続す
る接続手段(2)と を備えたことを特徴とする印字制御回路。
(1) In the print control circuit that pre-processes the dot information given to the dot matrix printer, there is a register (1) that temporarily stores the presence/absence of the dot information to be output to the dot matrix printer, and a register (1) that temporarily stores the presence/absence of the dot information to be output to the dot matrix printer, and Logical operation means (3
); and connection means (2) for connecting the output of the logic operation means to the input of the register.
JP61247070A 1986-10-16 1986-10-16 Print control circuit Expired - Lifetime JPH0661956B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61247070A JPH0661956B2 (en) 1986-10-16 1986-10-16 Print control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61247070A JPH0661956B2 (en) 1986-10-16 1986-10-16 Print control circuit

Publications (2)

Publication Number Publication Date
JPS6399963A true JPS6399963A (en) 1988-05-02
JPH0661956B2 JPH0661956B2 (en) 1994-08-17

Family

ID=17157979

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61247070A Expired - Lifetime JPH0661956B2 (en) 1986-10-16 1986-10-16 Print control circuit

Country Status (1)

Country Link
JP (1) JPH0661956B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0225347A (en) * 1988-07-15 1990-01-26 Nec Niigata Ltd Data density conversion control circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5391532A (en) * 1977-01-22 1978-08-11 Nippon Telegr & Teleph Corp <Ntt> Pattern generating equipment
JPS59148668A (en) * 1983-02-16 1984-08-25 Hitachi Ltd Control system for character generator of dot printer
JPS6082361A (en) * 1983-10-13 1985-05-10 Seiko Epson Corp Printer enabling printing at double speed and density

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5391532A (en) * 1977-01-22 1978-08-11 Nippon Telegr & Teleph Corp <Ntt> Pattern generating equipment
JPS59148668A (en) * 1983-02-16 1984-08-25 Hitachi Ltd Control system for character generator of dot printer
JPS6082361A (en) * 1983-10-13 1985-05-10 Seiko Epson Corp Printer enabling printing at double speed and density

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0225347A (en) * 1988-07-15 1990-01-26 Nec Niigata Ltd Data density conversion control circuit

Also Published As

Publication number Publication date
JPH0661956B2 (en) 1994-08-17

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