JP2690508B2 - Data density conversion control circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to image reduction by dot density conversion of a print output image, and more particularly to density conversion control in which data is thinned out for each arbitrary pulse train.

(Prior Art) Conventionally, the image reduction by converting the dot density of a print output image was performed by a program.

(Problems to be Solved by the Invention) Since the conventional dot density conversion described above is performed by a program process, it takes a long processing time, and there is a drawback that the printing speed of the printer is reduced.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data density conversion control circuit configured so as to eliminate the above-mentioned drawbacks by controlling the data density conversion of image data by hardware so as not to reduce the printing speed of the printer. .

(Means for Solving the Problem) A data density conversion control circuit according to the present invention includes an image data transfer section for transferring image data and N-ary, N + 1-ary, and N + binary counters, respectively, and for each arbitrary number of data. A counter group for generating a clock for thinning out the image data; a first clock control means for supplying a clock to the counter group; and an Nth clock in a shift register by the output of the N-ary and N + 1-ary counters. Second clock control means for prohibiting input, and data control means for holding the data by the Nth clock until the carry signal by the N + 1th clock is input from the N + binary counter by the carry output of the N-ary counter , A data decimation is performed by ORing the data with the Nth clock and the next data. And data combining means, from said data combining means sequentially by a clock output of the second clock control means outputs data that has been thinned, is constructed by comprising a shift register for storing.

(Example) Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a data density conversion control circuit according to the present invention.

In FIG. 1, 1 is an image data transfer unit, 2 is an N-ary counter, 3 is an N + 1 binary counter, 4 is an N + binary counter, 5 is a clock control circuit, 6 is a data control circuit, 7 is a data writing unit, and 8 is A shift register group, 9 is a data synthesis circuit, and 10 is a clock control circuit. In the clock control circuit 5, 51 is a flip-flop and 52 is an AND.
The gate.

FIG. 2 is a time chart showing the operation of each part of the data density conversion control circuit shown in FIG.

FIG. 3 is an explanatory diagram showing an output image reduced in image by density conversion.

The data density conversion control circuit according to the present invention thins out and controls the image data sent from the data transfer unit every arbitrary number of data. In FIG. 3, (a)
Represents unconverted image data, and (b) represents converted image data.

 Hereinafter, description will be given with reference to FIGS. 1 to 3.

In order to thin out the data for each arbitrary number of data, the data writing unit 7 outputs an N-ary counter 2, an N + 1-ary counter 3,
Also, write desired values to the N + binary counter 4, respectively. At the same time, the image data is input from the data transfer unit 1 to the data control unit 6, and the image transfer clock is input to the clock control circuit.
Input to 5 and 10, respectively.

Next, as shown in FIG. 2, SE from the data writing unit 7
By controlling the L signal, the transfer clock is input to the N-ary counter 2, N + 1-ary counter 3 and N + binary counter, respectively, when the SEL signal is at a high level.
On the -1st clock, the N-ary counter 2 generates a carry signal, and on the N-th clock, the N + 1-ary counter 3 generates a carry signal.

Therefore, the carry output is input to the clock control circuit 5, the clock connected to the shift register 8 is controlled during the period T shown in the time chart, and the data B is not transferred to the shift register 8 at the Nth clock.

The data B to be transferred at the Nth clock is held in the data control circuit 6 by the carry signal of the N-ary counter 2. At the next N + 1th clock pulse, N
+ 1st data C sent and the data control circuit 6
The data synthesizing circuit 9 performs an OR operation on the data B held in the above.

By the above, the data B + C is sent to the shift register 8 and the data is thinned out. As a result, the original image data is reduced and output as shown in FIG.

When the SEL signal is at the low level, the transfer clock is not supplied to any of the N-ary counter 2, the N + 1-ary counter 3, and the N + binary counter 4, so that the data is not thinned out. Therefore, only the image data synchronized with the transfer clock is supplied to the shift register group 8 and the data which has not been subjected to the density conversion is transferred.

(Effect of the Invention) As described above, the present invention has an effect that the printing speed of the printer can be increased by controlling the data density conversion of the image data by hardware.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a data density conversion control circuit according to the present invention. FIG. 2 is a time chart showing signals of the respective parts of FIG. FIG. 3 is an explanatory diagram showing the effect of the image data density conversion according to the present invention. 1 ... Image data transfer unit 2 ... N-ary counter 3 ... N + 1-ary counter 4 ... N + binary counter 5 ... Clock control circuit 6 ... Data control circuit 7 ... Data writing unit 8 ... Shift register 9 ... … Data synthesis circuit 10 …… Clock control circuit 51 …… Flip-flop 52 …… AND gate

Claims (1)

(57) [Claims] 1. An image data transfer section for transferring image data, a counter group comprising N-ary, N + 1-ary, and N + binary counters, respectively, and a clock group for generating a clock for thinning out the image data for each arbitrary number of data, First clock control means for supplying a clock to the counter group; second clock control means for prohibiting the Nth clock input to the shift register by the output of the N-ary and N + 1-ary counters; Of the N + binary counter by the carry output of the counter of (1), the data control means for holding the data of the Nth clock until the carry signal of the N + 1th clock is input, and the data of the Nth clock and the next data. Data synthesizing means for decimating data by taking an OR, and decimating and outputting by the data synthesizing means Wherein the data sequentially by the clock output of the second clock control means, data density conversion control circuit, characterized in that configured by comprising a shift register for storing, a.