JPH07334412A - Picture data transferring circuit - Google Patents

Abstract

PURPOSE:To efficiently transfer data from a RAM to a SAM in a VRAM. CONSTITUTION:A clock counter 6 is reset by a pulse generated from a writing pulse generating part 4, counts up a clock generated from a clock generating part 5 and outputs a signal at the time of counting up 16 clocks. A transfer timing pulse generating part 7 generates a transfer timing pulse based upon the signal and inputs the generated pulse to a RAS/CAS generating part 9, which generates transfer timing based upon the transfer timing pulse and adds a writing pulse delayed by 16 clocks through a writing pulse delaying part 8 to a CAS signal and impresses the added signal to the VRAM 3. The VRAM 3 writes picture data obtained by digitally converting a video signal 1 through an A/D conversion part 2 in the RAM 3a with the writing pulse impressed together with the CAS signal and transfers the written picture data to the DAM 3b at the transfer timing. The picture data transferred to the SAM 3b are read out by a required reading pulse and sent to a signal processing circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data transfer circuit and relates to an R of VRAM (random access memory for video).
The present invention relates to a circuit for transferring data written in AM (random access memory) to SAM (serial access memory).

[0002]

2. Description of the Related Art VR for recording digital video signals
The AM writes the input image data to the RAM with a write pulse in the RAS (row address strobe) / CAS (column address strobe) signal, transfers the image data to the SAM line by line, and uses it as a read pulse. Accordingly, the SAM image data is read in the written order and sent to the required signal processing circuit. As shown in FIG. 4, RAM refresh or SA during the write timing is performed.
Although image data is transferred to M, 16 clocks are usually required between writing in order to include this transfer timing. Since the interval of this writing timing is determined by the image reduction rate, conventionally, there is one that sets the transfer timing when the image reduction rate is 16 clocks or more between writing and writing. When determining whether to allow image data transfer based on the reduction ratio, for example, as shown in FIG. 3, when 16 clocks or less and 16 clocks or more are mixed between writing and writing, the image data is transferred at a timing of 16 clocks or more. There is a problem that it is possible but not used effectively.

[0003]

In view of the above, the present invention does not judge whether or not image data can be transferred based on the reduction ratio of the image, but writes each time the image data is written.
It is determined whether or not the transfer timing can be inserted between the write operations, and if possible, a transfer timing pulse is generated and RA
This transfer timing pulse is included in the S / CAS signal so that image data can be transferred efficiently.

[0004]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention is an A / D for converting a video signal into a digital signal.
VRA for recording signals from the D converter and the A / D converter
M, a write pulse generator that generates a write pulse for the VRAM, a clock generator that generates a clock synchronized with the video signal, and a reset by the write pulse, the clock is counted, and the required number is counted. And a RAS / CAS generation unit that generates a RAS / CAS signal based on the signal from the clock counter and outputs the RAS / CAS signal together with the signal from the write pulse generation unit. -Providing an image data transfer circuit that writes the signal from the A / D converter to the RAM by the write pulse from the CAS generator and transfers the signal from the RAM to the SAM at the transfer timing of the RAS / CAS signal. To do.

[0005]

With the above construction, the image data transfer circuit according to the present invention is provided with a clock counter which is reset by a write pulse and counts the clock, and the transfer timing is set before the input of the next write pulse. When the required number of clocks, for example, 16 clocks are counted, a signal is output, a transfer timing pulse is generated, and RAS / C
Transfer timing is generated in the AS signal, and the image data is transferred from the RAM to the SAM one line at a time by a transfer command from the reading side. The image data transferred to the SAM is read by a required read pulse and sent to a required signal processing circuit.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an image data transfer circuit according to the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of essential parts of an embodiment of an image data transfer circuit according to the present invention. In the figure, 1 is a video signal, 2 is an A / D converter, and video signal 1 is converted into a digital signal by an A / D converter 2.
3 is VRAM, which is composed of RAM3a and SAM3b,
A / D based on the write pulse from the write pulse generator 4
The image data from the conversion unit 2 is written in the RAM 3a. Reference numeral 5 denotes a clock generator which generates a required clock synchronized with the horizontal synchronizing signal of the video signal 1 and the like. Reference numeral 6 denotes a clock counter which counts clocks from the clock generation unit 5 and which is reset by a write pulse from the write pulse generation unit 4 and outputs a signal when counting 16 clocks, for example. A transfer timing pulse generator 7 generates a transfer timing pulse by a signal from the clock counter 6. A write pulse delay unit 8 delays the signal from the write pulse generation unit 4 by 16 clocks. Reference numeral 9 denotes a RAS / CAS generation unit which generates a required RAS / CAS signal based on the signal from the transfer timing pulse generation unit 7 and which is delayed by 16 clocks from the write pulse delay unit 8 to the CAS signal. An additional pulse is applied to the VRAM3 together with the RAS signal, the image data from the A / D converter 2 is written to the RAM3a, and the written image data is SAM3b line by line.
Transfer to. The image data transferred to the SAM 3b is read by a required read pulse and sent to a signal processing circuit (not shown).

Next, the operation of the image data transfer circuit according to the present invention will be described with reference to the timing chart of FIG. The clock generator 5 generates a clock whose phase is synchronized with the horizontal synchronizing signal of the video signal 1. This clock is input to the clock counter 6, and the clock counter 6 outputs the write pulse output from the write pulse generator 4.
Is reset, and the clocks are counted, and a signal is output when the number of clocks required for the transfer timing, for example, 16 pulses is counted. Before the clock counter 6 counts 16 clocks, the next write pulse (in the figure ,,,
,) Are input, no signal is output because they are reset by these write pulses. Clock counter 6
Signal is input to the transfer timing pulse generator 7 to generate a transfer timing pulse. That is, FIG.
The transfer timing pulse is output when the write pulse is between 16 clocks and the transfer timing pulse is not output below 16 clocks.

The transfer timing pulse is a write pulse 'delayed by 16 clocks in the write pulse delay unit 8,
It is input to the RAS / CAS generator 9 together with ',' ... It is the RAS that delays the write pulse by 16 clocks.
The CAS generation unit 9 generates the transfer timing in accordance with the transfer timing pulse generated 16 clocks after the timing of the write pulse or the like, so that the timing of writing the image data matches the waveform of the transfer timing. This is because. The RAS / CAS generation unit 9 writes the write pulse 'from the write pulse delay unit 8 at the transfer timing generated based on the transfer timing pulse.
, '...' are added and applied to the RAM 3a.

The video signal 1 is converted into a digital signal by the A / D converter 2 and input to the VRAM 3. RAM3a is
Image data from the A / D converter 2 is written in accordance with the RAS signal and the CAS signal, and the written image data is transferred in the next transfer period (dotted portion) to which a read pulse is applied.
One line each is transferred to the SAM 3b, and the RAM 3a is refreshed during the transfer period in which the read pulse is not applied. The image data transferred to the SAM 3b is sent to a required signal processing circuit.

[0010]

As described above, according to the image data transfer circuit of the present invention, whether or not the image data can be transferred from the RAM to the SAM is determined by the write pulse interval each time the image data is written to the RAM. Since it is determined by counting, even if it is determined that the image data cannot be transferred from the image reduction rate, the image data is transferred at some timings. Compared to the above, more transfer timing can be inserted, and the transfer operation is performed smoothly.

[Brief description of drawings]

FIG. 1 is a block diagram of an essential part of an embodiment of an image data transfer circuit according to the present invention.

FIG. 2 is a timing chart for explaining writing / transferring of image data.

FIG. 3 is a diagram for explaining whether or not image data transfer is possible.

FIG. 4 is a timing chart for explaining transfer of image data.

[Explanation of symbols]

 1 Video Signal 2 A / D Converter 3 VRAM 3a RAM 3b SAM 4 Write Pulse Generator 5 Clock Generator 6 Clock Counter 7 Transfer Timing Pulse Generator 8 RAS / CAS Generator

Claims (4)

[Claims] 1. A for converting a video signal into a digital signal
VR for recording signals from the A / D converter and the A / D converter
AM, a write pulse generation unit that generates a VRAM write pulse, a clock generation unit that generates a clock synchronized with the video signal, and a reset by the write pulse, and the clock is counted to count the required number. And a RAS / CAS generation unit that generates a RAS / CAS signal based on the signal from the clock counter and outputs the RAS / CAS signal together with the signal from the write pulse generation unit. An image data transfer circuit that writes the signal from the A / D converter into the RAM by the write pulse from the CAS generator and transfers the signal from the RAM to the SAM at the transfer timing of the RAS / CAS signal. 2. A transfer timing pulse generator that generates a transfer timing pulse by a signal from the clock counter is provided, and the RAS / CAS signal of the RAS / CAS signal is generated by the RAS / CAS generator based on the signal from the transfer timing pulse generator. The image data transfer circuit according to claim 1, wherein transfer timing is generated. 3. The image data transfer circuit according to claim 1, wherein the clock counter outputs a signal by counting the number of clocks required for transfer timing. 4. The image data transfer circuit according to claim 1, wherein the clock counter outputs a signal at a count of 16 clocks.