JPH06214877A - Data processor - Google Patents

Abstract

PURPOSE:To accelerate data transfer speed by simultaneously transferring plural data while dividing a bus line so that the total sum of bit lengths can not exceed a bus width. CONSTITUTION:An image data generator 101 generates data for four images at a maximum. The generated image data are connected to a buffer register 102 by the image data bus of 16 bits. A look-up table 103 writes outputs corresponding to all the combination of status registers and previously reserves a method for dividing 16 bits. The buffer register 102 is controlled by the output of the table 103 and rearranges the image data bus of 16 bits divided so that the total sum of bit lengths can not exceed the bus width so as to easily process it. The rearranged image data are scrolled by scroll processing parts 105-108 just for a value set by a scroll register 111 and inputted to an image processor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device between a plurality of blocks in a computer, a game, multimedia and the like.

[0002]

SUMMARY OF THE INVENTION According to the present invention, in a bus line connecting a plurality of functional blocks and having a constant width, a plurality of data are stored in the bus line so as not to exceed the total bit length of the bus line. By mixing and transmitting at the same time,
The data transfer efficiency between the plurality of blocks and the data processing speed are improved.

[0003]

2. Description of the Related Art In a conventional data transfer system, a plurality of data are transferred by sharing a data bus among blocks in a system by time division or sharing the data bus. When the clock represents the unit of time in the system,
In order to transfer a plurality of data, when the number of clocks required for one data transfer process is 1, the same number of clocks as the number of data is required.

Even if each functional block is highly developed and has excellent performance, the performance of the system will deteriorate if there is a rate-determining step in data transfer between blocks.

For example, in FIG. 2, A blocks 21 to B
If data is transferred using a 16-bit width bus for the block 22, the effective bit length is 2 bits like the data format 23, and the number of data to be transferred is 20, 20 I need a clock. However, only 16 bits are used in the 16-bit data bus, and the remaining 14 bits transfer meaningless data. Considering the usage efficiency of the bus line, only 12% is used for 20 clocks, and if a large amount of this kind of data is transferred, the usage efficiency is low and the overall system performance is extremely high. I am depressed.

[0006]

As a concrete example, when there is a game machine, the inside of the image data processing system of the game machine is as shown in FIG. As the types of image data, as shown in FIG. 3, 2-bit 4-color image data, 4-bit 16-color image data, 8-bit 25-color image data
There are 6-color image data and 16-bit 64K color image data. The image data generation device 401 can generate data for up to four screens, and as a system of a game machine, can combine images for up to four screens. At this time, scroll,
It is not possible to understand which mode combination is required at one time for the path for performing special processing such as data conversion of some kind.
I had to prepare for the screen. This means an increase in the scale of the system, which results in a large influence on personnel costs and costs.

An improvement in information processing speed is considered as one of system performance improvements. In recent years, the speed of information processing for each block and device in the system has improved, but there is a bus width regulation for data transfer, and since the transfer speed is lower than the processing speed, it functions in a series of information processing processes. Blocks or devices must be weighted to transfer data. Since the bus width is specified, the number of data bits that can be transferred at one time is limited, so effective use of the bus becomes a problem.

[0008]

SUMMARY OF THE INVENTION Therefore, according to the present invention, in a system, there is provided a bus line having a certain width for holding a plurality of functional blocks and connecting the plurality of blocks, and When a means for defining the type of data in the bus is provided, the bus line is divided so that the total bit length does not exceed the bus width, and a plurality of data are transferred simultaneously.

[0009]

With the data transfer system configured as described above, the bus line having a limited bit length can be effectively used to improve the data transfer speed and the information processing speed of the entire system.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 partially shows an image data processing apparatus used in a game machine. The data processing device performs a scroll process on the image data output from the image data generating device, synthesizes a plurality of screens, and outputs the screen to a monitor.

The image data generator 101 can generate data for up to four screens. The generated image data is
As shown in FIG. 3, 2-bit 4-color image data, 4-bit 1
6-color image data, 8-bit 256-color image data, 16
There is 64K color image data of bits. The image data output from the image data generator is connected to the buffer register 102 by a 16-bit image data bus.
The image data generator 101 outputs to the buffer register 102, together with the image data, a control signal that defines which type of data exists in 16 bits of the image data bus. The status register 104 is a register that stores in advance which data and in what combination the image data generator outputs. The look-up table (hereinafter referred to as LUT) 103 is written with outputs for all combinations of status registers.
A 16-bit division method is reserved in advance. The buffer register 102 is controlled by the output of the LUT 103 and rearranges the adaptively divided 16-bit image data bus for easy processing. The rearranged image data is scrolled by the scroll processing units 105 to 1108 by the value set by the scroll register 111 and input to the image synthesizing device 109. A screen to be extracted in image composition is set in the extraction screen setting register 110, and the image composition device 109 outputs an arbitrary image to the monitor according to this value.

The image data generator 101 can output images for up to four screens for each dot.
However, 4 bits of 64K color data, which is 16-bit data,
Even if the screen data is output, the image data bus connected to the buffer register 102 is 16 bits, and therefore cannot be transferred. There are 69 combinations of the four types of color modes, of which 24 combinations can be transferred in 16 bits, and 35% of the combinations are possible.
This transferable combination greatly depends on the data, the type, and the width of the data bus. For example, the width of the data bus is 3
If there are 2 bits and other conditions are the same, 52 combinations, 75% of combinations are possible. The size is determined by looking at the entire system and flow.

The status register 104 is as shown in FIG. As shown in FIG. 5A, there are registers for four surfaces, and the values in FIG. 5B are written to each surface. For example, the first screen of the four screens is unused, the second screen has 256 colors, the third screen has 16 colors, and the fourth screen has 4 screens for the remaining three screens.
When data is written in the status register so that color data is assigned, it becomes as shown in FIG. The image data generator 101 divides the image data bus as shown in FIG. 6B and sends data. In addition, the image data generator 101
Is the data of the first dot of the second screen, the data of the first dot of the third screen, the data of the second dot of the fourth screen from the LSB side of the image data bus. It will output.

From the output of the status register 104, L
Since it is understood that the image data bus is divided as shown in FIG. 6B, the UT 103 outputs the control signal as reserved in advance to the buffer register 102. LUT
From the output of 103 and the control signal of the image generating apparatus 101,
The buffer register operates bit by bit and sends it to the next stage. The buffer register 102 includes storage means,
When the output of the image data generator 101 is arranged for each dot, and when it is in the state A of FIG. 7, it is stored in the storage means as in the state B of FIG. So that the timing is set every 8 dots.

With respect to the data sent for each bit, the scroll processing units 105 to 108 delay the data according to the parameters stored in the scroll register 111 and output the delayed data.

The data output from the scroll processing section is input to the image synthesizing device 109. The image composition device outputs the screen set in the extraction screen setting register 110 to the monitor. Since the information for each bit is sent from the LUT 103, the output of the extraction screen setting register 110 and the output of the LUT 103 cause the n + th bit from the nth bit.
The output of the y-th bit will be output to the monitor.

[0018]

As described above, according to the present invention, it is possible to improve the information processing speed and to improve the performance of the entire system by efficiently utilizing the limited data bus.

[Brief description of drawings]

FIG. 1 is a block diagram according to the present invention.

FIG. 2 is a block diagram relating to a conventional example.

FIG. 3 is a data format diagram related to the present invention.

FIG. 4 is a block diagram relating to a conventional example.

FIG. 5 is a diagram showing an example of register setting according to the present invention.

FIG. 6 is a diagram showing a data format according to the present invention.

FIG. 7 is a diagram showing a data format related to the present invention.

[Explanation of symbols]

 101 ... Image data generator 102 ... Buffer register 103 ... LUT 104 ... Status register 105 ... Scroll processing unit 106 ... Scroll processing unit 107 ... Scroll processing unit 108 ... Scroll processing unit 109 ... Image synthesizing device 110 ... Extraction plane setting register 111 ... Scroll register 21 ... A block 22 ... B block 23 ... 16-bit data 31 ... 16-bit data 32 ... 16-bit data 33 ... 16-bit data 34 ... 16-bit data 401 ... Image data generator 402 ... Special processing device 403 ... Special processing device 404 ... Special processing device 405 ... Special processing device 406 ... Image synthesizing device 407 ... Mode Data

Claims (3)

[Claims] 1. A data processing device for processing image data and the like, comprising a plurality of blocks for each function and having a bus line having a certain width for connecting the plurality of blocks, wherein A data processing device comprising means for dividing the bus line so that the total sum does not exceed the bus width and transferring a plurality of data at the same time. 2. The data processing apparatus according to claim 1, further comprising a control signal line that defines the type of data in the bus line, in addition to the bus line that connects a plurality of blocks. 3. The data processing apparatus according to claim 1, further comprising an external input means for defining the type of data in the bus line, in addition to the bus line connecting a plurality of blocks.