JPH05216818A - Bus circuit - Google Patents

Abstract

PURPOSE:To prevent a bus output from being a floating state by holding the final value of a bus signal and sending it as a bus output when all bus drivers are disabled. CONSTITUTION:A NOR circuit G1, a transfer gate T1, and inverter circuits 1 and 2 constitute a signal holding circuit. When control signals inputted to control input terminals CNT1-CNTn are not all '1', the drivers A1-An are all disabled. At this time, the output of the NOR circuit G1 is '1', so the transfer gate T1 turns ON and the value right before the bus drivers A1-An are all disabled is stored in the circuit consisting of the transfer gate T1 and inverter circuits 1 and 2 and sent out as the bus output. Consequently, the bus output is prevented from being the floating state even when the bus drivers A1-An are all disabled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus circuit composed of a MOS type semiconductor integrated circuit, and more particularly to a bus circuit capable of preventing an output from becoming a floating state.

[0002]

2. Description of the Related Art In a conventional bus circuit, input signals from input terminals IN1, IN2, ..., INn are, for example, high-enable bus drivers A1, A2, as shown in FIG.
,, An, respectively, and input to the control input terminals CNT1,
From CNT2, ..., CNTn, each bus driver A1, A
Control signals are input to 2, ..., An, respectively. Output terminals of these bus drivers A1, A2, ..., An are commonly connected, and a bus output is obtained from the output terminal OUT2.

[0003]

In the conventional bus circuit described above, the control input terminals CNT1, CNT2, ..., CNT are used.
Each bus driver A according to the control signal input from n.
, An can be freely controlled, and all bus drivers A1, A2, ..., An can be controlled.
Has a possibility of being disabled (disabled). In this way, all bus drivers A1, A2
.., An becomes in a disabled state, the potential of the bus output becomes unstable and the current consumption increases. In the worst case, the device will be destroyed.

The present invention has been proposed in order to solve the problems of the prior art, and it is an object of the present invention to provide a bus circuit capable of preventing the bus output from becoming a floating state.

[0005]

In order to achieve this object, a bus circuit according to the present invention has an input signal input from an input terminal, a control signal input from a control input terminal, and a common connection. A plurality of bus drivers from which bus output signals are taken out from the output terminals, and a signal holding circuit which holds the bus output signal immediately before and outputs it as a bus output when all the bus drivers are disabled by the control signal Preferably, the signal holding circuit has a gate circuit that receives all control signals from the control input terminal,
When a control signal that disables all bus drivers is input to this gate circuit, it is turned on by the output of this gate circuit, and the source terminal is connected to the above output terminal of the commonly connected bus driver. A transfer gate, and a first inverter circuit in which a source terminal of the transfer gate is connected to an input terminal,
The output of the first inverter circuit is used as an input, and the output terminal is composed of a second inverter circuit connected to the drain terminal of the transfer gate.

[0006]

According to the above-mentioned structure, when all the bus drivers are in the disabled state, the bus output signal immediately before that is held by the signal holding circuit, so that the bus output terminals are kept in the floating state. It can be prevented.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of a bus circuit according to the present invention will be described in detail below with reference to the drawings. FIG. 1 shows an embodiment of this bus circuit. In this figure, input terminals IN1, IN2, ..., INn to which input signals are input are respectively connected to input terminals of a plurality of high-enable bus drivers A1, A2, ..., An, and control signals are input. Input terminals CNT1, CNT2, ..., CNTn are respectively connected to control input terminals of these bus drivers A1, A2 ,. Further, control input terminals CNT1, CNT2, ..., C
NTn are respectively connected to the input ends of a NOR circuit (NOR circuit) G1 forming a gate circuit. The output terminal of the NOR circuit G1 is connected to the gate terminal G of the transfer gate T1. The transfer gate T1 is turned on when the output of the NOR circuit G1 is at high level (when it is "1"). The source terminal S of the transfer gate T1 is
It is connected to the input terminal of the first inverter circuit 1, and the output terminal of this inverter circuit 1 is connected to the input terminal of the second inverter circuit 2. The output terminal of the inverter circuit 2 is connected to the drain terminal D of the transfer gate T1. The output terminals of the bus drivers A1, A2, ..., An are commonly connected to the source terminal S of the transfer gate T1, and are connected to the output terminal OUT1. The bus output signal is taken out from the output terminal OUT1. Here, the NOR circuit G1, the transfer gate T1, and the inverter circuits 1 and 2 are
A signal holding circuit is configured.

Next, the operation of the bus circuit thus constructed will be described. Control input terminals CNT1, CNT2
When all the control signals input to CNTn are not "1", the bus drivers A1, A2, ..., An are all disabled. At this time, since the output of the NOR circuit G1 becomes "1", the value immediately before the transfer gate T1 is turned on and the bus drivers A1, A2, ..., An are all disabled is set to the transfer gate T1 and the inverter circuit. The circuit composed of 6 and 7 stores it and sends it as a bus output. As a result, even if the bus drivers A1, A2, ..., An are all disabled, it is possible to prevent the bus output from floating.

Next, a bus circuit of another embodiment shown in FIG. 2 will be described. In this embodiment, each bus driver is composed of low-enable bus drivers B1, B2, ..., Bn. Control input terminals CNT1, CNT2
, CNTn are respectively connected to the input terminals of a NAND circuit (NAND circuit) G2, and the output terminals of the NAND circuit G2 are connected to the gate terminal G of the transfer gate T2 which is turned on by the input of "0". ..

In the bus circuit having this structure, when the control signals input to the control input terminals CNT1, CNT2, ..., CNTn are not all "0", the bus drivers B1 and B are provided.
2, ..., Bn are all disabled, and the NAND circuit G2 outputs "0". The transfer gate T2 is turned on by the input of "0", and the value immediately before the bus drivers B1, B2, ..., Bn are all disabled is set in the circuit composed of the transfer gate T2 and the inverter circuits 1 and 2. Store and send as bus output. Therefore, the bus drivers B1, B2
Even if all Bn are in the disabled state, the bus output can be prevented from being in the floating state.

Next, a bus circuit of another embodiment shown in FIG. 3 will be described. In this embodiment, each bus driver is composed of high-enable bus drivers A1, A2, ..., An, and control input terminals CNT1, CNT2 ,.
Tn is connected to the input terminal of the OR circuit (OR circuit) G3. The output terminal of the OR circuit G3 is turned on by the input of "0", and the gate terminal G of the transfer gate T2.
Connected to.

In the bus circuit having this configuration, when a control signal which does not become "1" is input to any one of the control input terminals CNT1, CNT2, ..., CNTn, the bus drivers A1, A2 ,. Enabled state. At this time, the OR circuit G3 outputs "0", the transfer gate T2 is turned on, and the bus driver A
, An are stored in the circuit composed of the transfer gate T2 and the inverter circuits 1 and 2 immediately before the values are all disabled, and are sent as bus outputs. As a result, even if the bus drivers A1, A2, ..., An are all disabled, it is possible to prevent the bus output from floating.

Next, a bus circuit of another embodiment shown in FIG. 4 will be described. In this embodiment, each bus driver is composed of low-enable bus drivers B1, B2, ..., Bn. Control input terminals CNT1, CNT2
, CNTn are respectively connected to the input terminals of an AND circuit (AND circuit) G4, and the output terminals of the AND circuit G4 are connected to the gate terminal G of the transfer gate T1 which is turned on by the input of "1". ..

In the bus circuit having this structure, when a control signal which does not become "0" is input to any one of the control input terminals CNT1, CNT2, ..., CNTn, the bus drivers B1, B2 ,. The AND circuit G4 outputs "1" while the enable state is set. The transfer gate T1 is turned on by the input of "1" from the AND circuit G4, and the bus drivers B1, B2
..., the value immediately before Bn is all disabled,
The circuit composed of the transfer gate T1 and the inverter circuits 1 and 2 stores it and sends it as a bus output. As a result, even if all the bus drivers B1, B2, ..., Bn are in the disabled state, the bus output can be prevented from being in the floating state.

The present invention is not limited to the above-mentioned embodiments, and various modifications can be made within the scope of the invention.

[0016]

As described above, according to the present invention, when all the bus drivers are in the disable state, the value immediately before the disable state can be held and sent to the bus output. It can prevent the output from floating. This stabilizes the potential of the bus output and does not increase the current consumption, so that the device can be prevented from being destroyed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a bus circuit according to the present invention.

FIG. 2 is a circuit diagram showing a bus circuit of another embodiment.

FIG. 3 is a circuit diagram showing a bus circuit of still another embodiment.

FIG. 4 is a circuit diagram showing a bus circuit of still another embodiment.

FIG. 5 is a circuit diagram showing a conventional bus circuit.

[Explanation of symbols]

 A1, A2, ..., An bus driver B1, B2, ..., Bn bus driver IN1, IN2, ..., INn input terminal CNT1, CNT2, ..., CNTn control input terminal OUT1 output terminal G1 NOR circuit G2 NAND circuit G3 OR circuit G4 AND circuit T1, T2 Transfer gate 1, 2 Inverter circuit

Claims (2)

[Claims] 1. A plurality of bus drivers, each of which receives an input signal from an input terminal, a control signal from a control input terminal, and a bus output signal from a commonly connected output terminal, and the control signal. And a signal holding circuit that holds the immediately preceding bus output signal and sends it as a bus output when all the bus drivers are disabled by. 2. A gate circuit that receives all control signals from the control input terminal and a control signal that disables all bus drivers is input to this gate circuit. A transfer gate that is turned on by an output and has a source terminal connected to the output terminal of the commonly connected bus driver; a first inverter circuit having a source terminal of the transfer gate connected to an input terminal; 2. The bus circuit according to claim 1, wherein the signal holding circuit is composed of a second inverter circuit which receives an output of the first inverter circuit as an input and has an output end connected to the drain terminal of the transfer gate. ..