JPH0521400U - Data carrier - Google Patents

Abstract

(57) [Summary] [Object] According to the present invention, by controlling the data rewriting operation timing of the EEP-ROM from the outside, a built-in timer is not required, so that the scale of the integrated circuit can be reduced. The data carrier 15 is provided with an erase end circuit 14 and a write control circuit 9, and the erase operation is ended by receiving an erase end code from the reader / writer 1, and the memory cell is synchronized with the serial reception timing of a series of data groups. By writing data to 10, EEP-ROM
Rewrite the data. [Effect] Since the integrated circuit becomes small, a small and inexpensive data carrier can be provided.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a data carrier having a built-in EEP-ROM as a storage element and transmitting and receiving data by electromagnetic waves.

[0002]

[Prior Art]

 Normally, the EEP-ROM requires a considerable amount of time for rewriting data, that is, erasing existing retained data and storing and retaining new data because of its physical characteristics. Circuits that can collectively rewrite a series of data groups in the same area are provided, and efforts have been made to reduce the apparent data rewriting time. Especially, it takes a long time to erase the retained data, and the time is managed by a timer. Here, a series of data groups in the same area represents, for example, 32-byte data that differs only in the lower bits of the address. The configuration of a general EEP-ROM will be specifically described below with reference to the rewriting operation, based on the circuit block diagram of FIG.

The EEP-ROM 35 satisfies a predetermined condition for the memory cell 34, which is a main body unit for storing and holding data, the data-in buffer 31 for inputting data from the external CPU 30, and the data from the data-in buffer 31. It is composed of a peripheral part such as a data buffer 32 for temporarily storing up to and a timer 33 for monitoring and generating various timings. The timer 33 includes a data input timer 36 for monitoring external data input timing, a write timer 38 for generating data write timing to the memory cell 34, and an erase operation for erasing existing data held in the memory cell 34. It consists of an erase timer 37 which generates a signal.

First, when the CPU 30 writes the data S30 in the EEP-ROM 35, the write data is stored in the data buffer 32 through the data-in buffer 31, and the data-in buffer 31 outputs the data input detection signal S31. Subsequently, the above operation is repeated every time the data S30 is written from the CPU 30. The data input timer 36 starts the counting operation when the data input detection signal S31 is input, but is reset by the data input detection signal S31 by the next write data and executes the counting operation again. When the data input detection signal S31 is not input even after the lapse of a predetermined time, that is, when the data writing from the CPU 30 is completed, the time is up, the counting operation is stopped, and the input completion signal S36 is output. It At this point, the written data group is stored in the data buffer 32. Here, the predetermined time is the maximum value between the time when one data is written and the time when the next data is written, which is also called a byte load cycle time, and is generally 30 to 100 μs. is there. A series of data groups must be written within this time.

When the writing of a series of data is completed and the data input timer 36 outputs the input completion signal S36, the erase timer 37 starts the counting operation and outputs the erase signal S34 to output the memory cell. The erasing of 34 is started. It takes about 10 ms for erasing, and the erasing timer 37 finishes its time. At the same time, the erase end signal S37 is output and the write timer is operated. The write timer 38 is a timer for generating a timing for writing a series of data groups stored in the data buffer 32 into the memory cell 34 byte by byte, and outputs a write control signal S33 every time the time is up. The data is output and the data in the data buffer 32 is written in the erased area of the memory cell 34. The time required for writing is about 1 ms for all 32-byte data. When the writing is completed, the writing of the data S30 from the CPU 30 is repeated again.

It is to be noted that erasing of the memory cell 34, area designation for writing data, that is, address is not particularly necessary for explaining the conventional example, and is therefore omitted in FIG. For the same reason, the data read circuit from the EEP-ROM 35, the power supply, the clocks for system operation and timer operation, etc. are also omitted.

[0007]

[Problems to be solved by the device]

 A conventional timer having a built-in EEP-ROM generally has a configuration in which flip-flop circuits are connected in a plurality of stages. Therefore, the circuit scale, that is, the integrated circuit, becomes large to some extent, and the mounting area becomes large. Of course, the price of the integrated circuit itself will increase.

An object of the present invention is to solve the above problems and provide a small-sized and low-cost data carrier.

[0009]

[Means for Solving the Problems]

 According to the present invention, this object is achieved by the following configuration. That is, data is transmitted and received to and from the reader / writer by electromagnetic waves, and the data carrier storing the received data in the internal EEP-ROM receives the erasing end code and the erasing end code. An erasing end circuit for this purpose and a writing control circuit for controlling data writing to the EEP-ROM are provided.

[0010]

【Example】

 FIG. 1 is a circuit block diagram showing the present invention. Further, FIG. 2 shows the timing of each signal line in FIG. The circuit for reading data from the EEP-ROM described in the conventional example, that is, the transmission of data from the data carrier 15 to the reader / writer 1 in FIG. 1 is omitted because it is not directly related to the description of the present invention. I am doing it. Similarly, the power supply of the data carrier 15 and the clock for system operation are omitted.

In FIG. 1, the data carrier 15 receives serial data from the reader / writer 1 via the coils L1 and L2 by electromagnetic waves, and is converted into a digital signal by the AD conversion unit 2 and further converted into serial-parallel conversion. The data is converted into parallel data in the section 3 and processed by each internal processing circuit or data is written in the memory cell 10 of the EEP-ROM. The transmission contents from the reader / writer 1 include an instruction code indicating the processing content, write data to the memory cell 10 inside the data carrier 15, and an erase end code transmitted at the erase end timing of the memory cell 10. , A check code for determining in the data carrier 15 whether or not the transmission is normally performed. It should be noted that, as the instruction code, in the present invention, only two commands of a data write command and an erase command for the memory cell 10 will be described. The check code is also called a BCC (Block Check Character), and is given a value obtained by exclusive ORing the instruction code and each data immediately before that, that is, an even horizontal parity.

The command decoder 4 is a circuit that outputs a command detection signal according to the content of the instruction code from the reader / writer 1, that is, each command, and is latched and output by the command latch circuit 5. The BCC detection circuit 6 is composed of EX-OR circuits of the number of data bits, that is, 8 bits. When the BCC is received, if the instruction code up to that point or the content of each data is correct, all the EX-ORs will be in a coincident state and coincidence detection will be performed. In addition to outputting the signal, it is latched and output by the BCC latch circuit 7. The data byte number counter 8 is a circuit which operates when a write command is received and counts the number of bytes of subsequent write data. The write control circuit 9 is a circuit that writes data in the memory cell 10 of the EEP-ROM each time the write data is received. The erase end circuit 14 is a circuit that ends the data erase operation of the memory cell by the erase command by receiving the erase end code.

Now, referring to the time chart of FIG. 2, the data rewriting operation of the memory cell 10 of the EEP-ROM starting from the command transmission of the reader / writer 1 in FIG. explain.

In FIG. 2, the symbols from S1 to S14 correspond to the signals of the same numbers in FIG. 1, and indicate that the output state or output timing of each signal changes with time. S1 is a digital signal obtained by converting the signal from the reader / writer 1 by the AD converter, and is composed of any combination of an instruction code, a check code, write data, and an erase end code. S2 is a parallel signal obtained by parallel-converting the serial digital signal S1 by the serial-to-parallel converter 3, and represents the signal output timing. Here, in the figure, ERASE represents an erase command, BCC is a check code for ERASE, and NULL is an erase end code, which means that it is transmitted at the erase completion timing after a lapse of time T. WRITE is a write command, BCC1 is a check code for WRITE, DT1 to DTn are data to be written in the memory cell 10, and BCC2 is a check code for write data from the DT1 to DTn. That is, FIG. 2 shows a state in which the data is written after the memory cell 10 is erased.

First, when an erase command is received as an instruction code from the reader / writer 1, the command decoder 4 detects it through the AD converter 2 and serial-parallel converter 3, and an erase command detection signal S4 is output as a pulse. On the other hand, the input value is also held in the BCC detection circuit 6. Specifically, the EX-OR operation result of the initial value 0 of each bit in the BCC detection circuit 6 and each corresponding bit of the erase command is set. The erase command detection signal S4 is latched and output as an erase command latch signal S6 by the command latch circuit 5, and thereafter held until the completion signal S13 is input. Subsequently, the check code for the erase command, that is, BCC is received from the reader / writer 1, and the BCC detection circuit 6 performs an EX-OR operation with the existing value. If there is no abnormality such as a communication error, all bits become 0. , BCC coincidence detection signal S7 is output, and at the same time, it is latched and output as a BCC coincidence latch signal S8 by the BCC latch circuit 7, and is held until the subsequent completion signal S13 is input.

When the BCC is normally received and the BCC coincidence latch signal S8 is output, the erase signal S10 is output through the AND circuit 13 together with the erase command latch signal S6 from the command latch circuit 5, and the memory cell The erasing of the data of 10 is started. At the same time, the erasing end circuit 14 is enabled, that is, put into a state of waiting for reception of the erasing end code. Assuming that the erasing completion time of the EEP-ROM is T, the reader / writer 1 transmits NULL, which is an erasing end code, after a lapse of time T from the completion of BCC transmission. Since the erase end circuit 14 is enabled by the erase signal S10 from the AND circuit 13, it detects NULL and outputs the erase end signal S11. Here, it is clear that the NULL does not have to be a specific code that is fixed uniformly, and the code content may be anything as long as it is transmitted at the timing of the end of erasure. Therefore, the erasing end circuit 14 does not have a decoding function and is a circuit that only detects the presence or absence of reception.

When the erasing end signal S11 is output from the erasing end circuit 14, the OR circuit 11 outputs a completion signal S13, which resets the command latch circuit 5 and the BCC latch circuit 7 to the next instruction code or BCC. And the erase signal S10 goes into the non-output state and the erase of the memory cell 10 is completed.

Now, after the erase operation is completed, a write command is received as an instruction code from the reader / writer 1 this time, and a data write operation to the memory cell 10 is performed. When a write command, that is, WRITE, is received, the pulse output of the write command detection signal S3 through the AD conversion unit 2, the serial-parallel conversion unit 3 and the command decoder 4 and the writing from the command latch circuit 5 are performed as in the case of the erase command. While the command latch signal S5 is output, it is also input to the BCC detection circuit 6 and the value is held. The data byte number counter 8 starts counting the number of bytes of subsequent received data at the same time as outputting the write command latch signal S5. When the BCC1 is continuously received, the BCC coincidence detection signal S7 is output, and the BCC latch circuit 7 latches and outputs the BCC coincidence latch signal S8. The write command latch signal S5 and the write enable are given through the AND circuit 12. The signal S9 is output, the write control circuit 9 is enabled, and thereafter, the code sent from the reader / writer 1 is regarded as write data, and writing to the memory cell 10 is performed.

When the write data DT1 is received after the BCC1 is normally received, the write control circuit 9 is in the enabled state, so that the data write operation is started and the DT1 data is immediately output to the memory cell 10. , The output is maintained until the next data DT2 is received. Simultaneously with the start of writing to the memory cell 10, the data byte number counter 8 counts once. Since the data byte number counter 8 starts counting after the write command latch signal S5 is output, when the DT1 is received, the internal counter is in the counting state of 2 including BCC1.

When the next write data DT2 is received, the write control circuit 9 stops the output of the previous data, that is, DT1 to the memory cell 10, ends the writing of DT1, and newly writes the DT2 data. Start output. In addition, the data byte number counter counts once, and becomes three counting states. The time required to write 1-byte data is determined by the time from the start of writing one data to the completion of serial reception of the next data, that is, the transmission speed from the reader / writer 1, so the conventional example in FIG. The transmission speed is set so as to be equal to the count-up time of the write timer 38 described above. If the number of bytes of write data is determined between the reader / writer 1 and the data carrier 15 and is n bytes, the data write operation is repeated n times, and then the BCC 2 is received.

Upon reception of BCC2, the writing of the last data DTn is completed, and it means that all data of n bytes has been written. The internal set value of the data byte number counter 8 is set to the number of bytes including BCC1 and BCC2, that is, n +2, counts up at the time of receiving BCC2, outputs the write command end signal S12, and further OR circuit 11 Is output as a completion signal S13, the command latch circuit 5 and the BCC latch circuit 7 are reset, and the next instruction code or BCC is waited for. At the same time, the write enable signal S9 is not output to the memory cell 10. The data write operation of is completed. At this point, the writing of the last code, BCC2, to the memory cell 10 is also started. However, immediately after the writing is started, the write enable signal S9 is in a non-output state, so the write data from the write control circuit 9 The output of S14 cannot be maintained for the time required for writing, and is not stored and held in the memory cell 10.

[0023]

[Effect of the device]

 As is clear from the above description, according to the present invention, the rewriting of the data of the EEP-ROM, that is, the data erasing and writing operations are performed at the transmission timing of the erase code or the write data from the reader / writer. However, the timer groups such as the erase timer and the write timer, which have been conventionally incorporated in the EEP-ROM, are not necessary, and only the erase end circuit and the write control circuit having a small circuit scale are included. Therefore, the integrated circuit is small and inexpensive. Therefore, it is very effective in providing a compact and low-priced data carrier.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration of the present invention.

FIG. 2 is a time chart showing how the signal lines in FIG. 1 change with time.

FIG. 3 is a circuit block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1 reader / writer 9 write control circuit 14 erase end circuit 15 data carrier of the present invention

Claims (1)

[Scope of utility model registration request] A data carrier for transmitting and receiving data to and from a reader / writer by electromagnetic waves and for erasing data in the EEP-ROM by receiving an erasing end code in a data carrier for storing the received data in an internal EEP-ROM. A data carrier comprising an erasing end circuit and a write control circuit for controlling data writing to the EEP-ROM.