JPH0520888A - Active analog memory - Google Patents

Abstract

PURPOSE:To solve the problem of charge leak and to downsize the scale of the circuit in an analog memory employing a capacitor element. CONSTITUTION:An integrating means 11 integrates pulse voltage sequentially and outputs an analog integrated voltage. When the integrated voltage of the integrating means 11 exceeds an analog accumulated voltage of a capacitor element Cmem, a comparing means 12 applies the integrated voltage of the integrating means 11 onto the capacitor element Cmem with respect to a switching means 13 and then clears the integrated voltage. The comparing means 12 executes the series of operations within a time shorter than a time during which the accumulated voltage of the capacitor element Cmem decreases by an amount corresponding to the pulse voltage. Alternatively, a plurality of sets of the capacitor element Cmem and the switching means 13 may be connected in parallel with the integrating means 11 and the comparing means 12 so that time division operation takes place. According to the constitution, an active analog memory can be realized with a very simple circuitry.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog memory using a capacitor element useful as a constituent circuit of a neural network or the like.

[0002]

2. Description of the Related Art In recent years,
Hardware development of neural networks is in progress. In a neural network, one neuron is connected to a number of synapses, which are a kind of input terminals,
Signals from many other neurons are input. Then, each synapse input is weighted independently and then added. Such an input form is called synaptic connection. Then, the output of one neuron is determined as the output obtained by converting the weighted addition output by a predetermined function.

When the neuron is made into hardware, a memory circuit for storing each connection weight value in each synapse connection is required. In a neural network, data processing in many neurons must be performed in parallel and in real time. Also in the above-mentioned memory circuit, a large number of memory elements are required for one neuron. Moreover, since a neural network is constructed by combining a large number of such neurons, a huge number of memory elements are required in the entire network. Due to such a fact, a technique for converting a memory element into VLSI is indispensable.

As a first conventional example of the above memory device,
There is a digital memory device. This element has an advantage that a highly integrated element can be easily realized by the recent development of digital circuit technology.

However, the digital memory device basically has a complicated circuit structure such as a decoder circuit, a read circuit, a write circuit, etc., and an A / D for converting input data into a digital value. Since a converter is also required, the circuit scale increases. In particular, when this element is applied to a circuit in which neurons are complicatedly and dynamically synapse-coupled like a neural network,
It has a problem that it is difficult to integrate it to a certain extent.

A second conventional example of the memory device is a floating gate device. This element is a general MOS
It has a structure similar to the shape of a transistor, and by applying a pulse to an internal floating gate, it is possible to store electric charge, which is stored data, for a long period of time.

However, since the floating gate element requires a high voltage pulse for writing and erasing the electric charge which is stored data, a dedicated drive circuit for generating the high voltage pulse is required. Further, the charge writing characteristic is non-linear. From these facts, there is a problem that the circuit scale becomes large when the floating gate element is applied to a neural network or the like.

As a third conventional example of the memory element, there is a capacitor element. This element is an element that stores a charge, which is stored data, as a capacitance of a capacitor. Since this element can read and write continuous values (analog values) in continuous time, it is called an analog memory together with the floating gate element described above. In particular, an analog memory using a capacitor element is promising as a memory circuit that constitutes each synapse connection of a neural network, since no special peripheral circuit is required.

However, in the capacitor element, leakage of electric charge becomes a problem when data is stored for a long time. Therefore, it is desired to realize an analog memory that compensates for such a leak of electric charge and can always refresh stored data. Hereinafter, the analog memory having such a refresh function will be referred to as an active analog memory.

A configuration generally considered as an active analog memory is shown in FIG. The active analog memory of FIG. 9 includes an A / D converter 91, a D / A converter 92, a capacitor C _mem for storing a voltage value as data, and switches S ₁ and S ₂ .

_Assuming that the voltage value is stored in advance in the capacitor C _mem , the switch S ₁ is turned on and S ₂ is turned on.
Is turned off, the voltage value stored in the capacitor C _mem is converted into a digital value by the A / D converter 91.

Next, when the switch S ₂ is turned on and S ₁ is turned off, the digital value output from the A / D converter 91 is converted into an analog value again by the D / A converter 92, and the capacitor C _It is written back to _mem .

At this time, the above-mentioned two consecutive operations are
The voltage value stored in the capacitor C _mem is the A / D converter 9
It is performed within a time period shorter than the time period for which the voltage value corresponding to one quantization step in 1 is decreased. And A /
The D converter 91 converts the input analog voltage value into a digital value corresponding to the quantized voltage value immediately above the voltage value.

With the above configuration, the D / A converter 92 always outputs the same voltage value as the voltage value initially held in the capacitor C _mem , and this voltage value causes the storage voltage in the capacitor C _mem . Can be refreshed.

Based on the configuration of the active analog memory as shown in FIG. 9, an active analog memory capable of simultaneously storing a plurality of analog voltage values can be constructed. The structure is shown in FIG. The circuit configuration of switch S _{2 -capacitor} C _{mem -switch} S ₁ similar to that of FIG.
It has a configuration of being connected in parallel as indicated by 1, # 2, # 3, .... Then, by operating these circuit components in a time-division manner, different voltage values are stored in each capacitor C _mem while the refresh operation is independently performed.

However, in the active analog memory shown in FIG. 9 or 10, the A / D converter 91 and the D / A converter are used.
As the converter 92, a multi-bit circuit is used. Therefore, in order to increase the accuracy (step width) of the storage voltage value, a circuit having a large number of quantization bits is required, which causes a problem that the circuit scale becomes large.

Further, as the number of quantization bits increases, it becomes more difficult to operate at high speed, and the number of capacitors C _mem that can be operated in time division is limited as shown in FIG. There are also problems.

An object of the present invention is to solve the problem of electric charge leakage and to reduce the circuit scale in an analog memory using a capacitor element.

[0019]

FIG. 1 is a block diagram of the first principle of the present invention. The present invention is premised on an analog memory that stores analog stored data in the capacitor element C _mem as charges.

First, there is an integrating means 11 for sequentially integrating the input pulse voltages and outputting the integrated voltage as an analog integrated voltage. Next, MO that selectively applies the integrated voltage from the integrating means 11 to the capacitor element C _mem.
It has a switch means 13 composed of an S-transistor switch or the like.

Further, it has a comparison means 12 for executing the following series of operations. That is, the comparison means 12 first
The integrated voltage from the integrating means 11 is compared with the analog accumulated voltage corresponding to the charges accumulated in the capacitor element C _mem . When the integrated voltage exceeds the accumulated voltage, the comparison means 12 causes the switch means 13 to apply the integrated voltage from the integration means 11 to the capacitor element C _mem and clears the integrated voltage in the integration means 11. .

If the comparing means 12 does not clear the integrated voltage but sets the integrated voltage to the accumulated voltage before the updating of the capacitor element C _mem , the time required for completing the above series of operations next time. Can be shortened.

Here, the comparison means 12 executes the series of operations described above within a time period shorter than the time period during which the accumulated voltage in the capacitor C _mem is reduced by the above-mentioned pulse voltage value.

Next, FIG. 2 is a block diagram of the second principle of the present invention. This configuration is based on the configuration of FIG. 1 and is composed of a capacitor element C _mem and a switch means # 1 to # 1.
A plurality of sets of #N components are connected in parallel to the integrating means 11 and the comparing means 12.

Then, the comparison means 12 performs the series of operations described above by comparing the comparison means 12 and the integration means 11 with # 1 to #N.
The connection with each component is sequentially switched in a time division manner. Specifically, each capacitor element C _mem of # 1 to #N
A switch means 14 constituted by a MOS transistor switch or the like is provided between each of them and the comparison means 12. Then, the comparison means 12 uses the switch means 1
4 and the switching means 13 described above are switched in a time division manner, and the series of operations described above, that is, the refresh operation for each capacitor element C _mem , is executed for each of the above-mentioned components # 1 to #N.

[0026]

1 or 2, the integrating means 11 corresponds to the D / A converter 92 in the conventional example of FIG. 9 or 10.
The comparing means 12 corresponds to the A / D converter 91, but the integrating means 11 and the comparing means 12 are very simple circuits as compared with the multi-bit D / A converter 92 and the A / D converter 91. It can be realized with a configuration. Therefore, an active analog memory can be configured with a small circuit scale.

In particular, by adopting a circuit configuration that operates in a time-sharing manner as shown in FIG. 2, an active analog memory capable of simultaneously storing a plurality of analog voltage values can be configured, and for example, each synapse connection of a neural network is configured. It can be realized as a memory circuit.
In this case, one set of integrating means 11 and comparing means 12 may be prepared for each of the plurality of capacitor elements C _{mem of} # 1 to #N, and therefore integration is easy.

Further, in order to increase the accuracy (step width) of the storage voltage value of the capacitor element C _mem , it is necessary to reduce the value of the pulse voltage and increase the integration speed of the integrating means 11, but the capacitor element C _Since the charge leakage speed of _mem is about one day to several days even at room temperature, even if the time-divisional configuration shown in FIG. 2 is adopted, a simple circuit configuration is sufficient.

Conversely, according to the present invention, the capacitor element C which is refreshed in parallel by the time division processing is used.
The number of _mem can be increased to a considerably large number, and it can be applied to large-scale neural networks.

[0030]

Embodiments of the present invention will now be described in detail with reference to the drawings. First Embodiment FIG. 3 is a configuration diagram of a first embodiment of the present invention. The present embodiment corresponds to the first principle of the present invention in FIG. 1 and has a circuit configuration when the number of time divisions is one.

In the figure, a portion surrounded by a broken line 31 roughly corresponds to the integrating means 11 in FIG. 1 and is constituted by an analog circuit. Further, a portion surrounded by a broken line 32 roughly corresponds to the comparing means 12 of FIG. 1, and is configured by a digital circuit as a center. The capacitor C _mem stores target analog data (voltage value) as in FIG. 1.

First, in the integrating circuit of the broken line portion 31, the constant current I from the constant current source 33 is supplied to the capacitor C by the clock Φ.
is supplied to _int , and as a result, an integrated voltage V _int is obtained at the terminal side of the capacitor C _int opposite to the ground terminal.

Here, when the voltage value of the integrated voltage V _int is V, the capacitance of the capacitor C _int is C, the accumulated charge is Q, and the unit current is i,

[0034]

[Equation 1] V = Q / C

[0035]

[Equation 2] Q = ∫idt Can be expressed as

[0036]

[Equation 3] V = (1 / C) · ∫idt Can be expressed as

Since I is a constant current, assuming that the integrated voltage V _int changes by the step voltage width ΔV during the minute time Δt, the following formula 3 is obtained.

[0038]

[Expression 4] ΔV = (I / C) · Δt That is, the voltage value V of the integrated voltage V _int during the minute time Δt when the clock Φ turns on the switch S _P.
Changes by the step voltage width ΔV as shown in FIG.

Now, _assuming that an arbitrary storage voltage V _mem is stored in advance in the capacitor C _mem and no charge is _initially stored in the capacitor C _int , the clock Φ as shown in FIG. As a result of the switch S _P being periodically turned on / off based on this, the integrated voltage V _int increases stepwise from the ground level by a step voltage width ΔV in synchronization with the clock Φ, as shown in FIG. Do it.

Here, as described above, the electric charge accumulated in the capacitor C _mem leaks based on a predetermined time constant, and accordingly, the accumulated voltage V _mem is shown in FIG.
It gradually decreases like.

In such a state, when the integrated voltage V _int exceeds the accumulated voltage V _mem at a certain time t ₁ , if the integrated voltage V _int exceeds the accumulated voltage V _mem , as shown in FIG.
The comparison output C _out of the comparator 34 becomes the high level as shown in FIG.

This comparison output C _out is latched at the timing when the clock Φ changes from the high level to the low level.
Held at 5. The latch 35 then outputs the comparison output C
At the same time as holding _out, the switch S _H is turned on as shown in FIG. As a result, a voltage value obtained by increasing the integrated voltage V _int by one step voltage width ΔV by the adder 36 is applied to the capacitor C _mem , and the accumulated voltage V _mem falls within the error range of the step voltage width ΔV. The initially stored voltage value is retained.

Further, the latch 35 turns off the switch S _H and turns on the switch S _R at a timing delayed by a half cycle of the clock Φ from the timing at which the comparison output C _out is held, as shown in FIG. . As a result, the electric charge accumulated in the capacitor C _int is discharged through the switch S _R , the integrated voltage V _int is returned to the ground level and cleared as shown in FIG. 5, and the comparison output C _out is also changed from the high level to the low level. Return to.

[0044] By the above operation is repeated, the accumulated voltage V _mem in the capacitor C _mem is maintained. In order to accumulate voltage V _mem it is held at a voltage value when stored in the first capacitor C _mem is reserved voltage V _mem is divided by the shorter time to decrease the time step voltage range ΔV In addition, the integrated voltage V _int needs to exceed the accumulated voltage V _mem . Therefore, the speed of the clock Φ, that is, the integration speed is experimentally determined so that such a condition is satisfied.

FIG. 6 is a circuit diagram of the constant current source 33 shown in FIG. This circuit is composed of an operational amplifier OP and three transistors Q ₁ , Q ₂ and Q ₃ , and two PNP transistors Q ₂ and Q ₃ form a current mirror circuit. With this configuration, a discharge type current source is realized. Second Embodiment Next, FIG. 7 is a configuration diagram of a second embodiment of the present invention.
The present embodiment corresponds to the second principle of the present invention in FIG. 2 and has a circuit configuration when the number of time divisions is 10.

In FIG. 7, the parts with the same numbers as in FIG. 3 have the same functions. First, the portion surrounded by the broken line 32 is shown more specifically than in the case of FIG. That is,
A portion corresponding to the latch 35 in FIG. 3 is a Schmitt trigger circuit unit 72 connected in two cascades, D flip-flops FF1 and FF2 connected in two cascades, and two AND circuits AND1 and AND2.

In this portion, first, when the comparison output C _out of the comparator 34 becomes a high level, the signal is waveform-shaped by the Schmitt trigger circuit section 72, and then once held in the D flip-flop FF1, and further the clock signal is output. At the timing synchronized with the inverted clock of Φ, that is, the timing when the clock Φ changes from the high level to the low level as described in the first embodiment, the D flip-flop FF2.
Latched on.

Then, as described in the first embodiment,
The latch output of the D flip-flop FF2 is the clock Φ.
AND circuit AND that turns on in synchronization with the inverted clock of
The switch S _H is turned on for a half cycle of the clock Φ via 1 (see FIG. 5).

As described in the first embodiment, the output of the D flip-flop FF2 is turned on in synchronization with the clock Φ from the timing when the switch S _H is turned on via the AND circuit AND2. Switch S _R is clock Φ at the timing delayed by a half cycle of clock Φ.
Is turned on for half a cycle, and at the same time, D flip-flop FF
Reset 1

The operation up to this point is substantially the same as that of the first embodiment, but the configuration of the second embodiment of FIG. 7 is different from that of the first embodiment of FIG. , Capacitor C
_mem is provided with a plurality as shown in # 1 to # 10, 10 of the switch circuits and S ₁ to S ₁₀ for time division control shown by the dashed line 71 for this to work is provided It is a point.

The part indicated by the broken line 71 is a decimal counter 73,
Inverter INV and 10 AND circuits A of # 1 to # 10
It is composed of ND3. First, the decimal counter 7
The output Q _{1 of} 3 is high level, and this output is
As shown in FIG. 8, only the switch S ₁ is turned on via the # 1 AND circuit AND3. As a result, the comparator 34
, The storage voltage V of the capacitor C _mem of # 1
_mem is compared with the integrated voltage V _int that increases stepwise. Then, when the integrated voltage V _int exceeds the accumulated voltage V _mem of # 1, the switch _SH is turned on as described above, and the capacitor C _{mem of} # 1 is refreshed. Further, the integrated voltage V _int is returned to the ground level via the switch S _R. It should be noted that while the switch S _R is on, the inverter INV drives the AND circuit AND of # 1.
3 is turned off and the switch S ₁ is turned off.

At this time, the decimal counter 73 is incremented at the timing when the switch S _R is turned on, that is, when the output of the AND circuit AND2 becomes high level. Therefore, at the next timing, the output Q ₂ of the decimal counter 73 becomes high level, and this output becomes
As shown in FIG. 8, only the switch S ₂ is turned on via the AND circuit AND3 of # 2. As a result, in the comparator 34, the capacitor C _{mem of the} # 2 is similar to the above-described operation.
The integrated voltage V _mem of the integrated voltage V _mem
By comparing with _int , the refresh operation is performed on the capacitor C _mem of # 2.

As described above, the refresh operation is time-divisionally performed on the ten capacitors C _{mem of} # 1 to # 10. Other Embodiments In the above embodiments, the integrated voltage V _int is equal to the capacitor C _mem.
The integrated voltage V _int is cleared every time the accumulated voltage V _mem of the above is exceeded, but if a configuration is adopted in which the integrated voltage V _int is set to the accumulated voltage V _mem before updating, the time of each refresh operation is shortened. Can be made. For that purpose, for example, a bridge configuration for inputting the output of the capacitor C _mem to the capacitor C _int may be provided.

The portion of the integrator circuit indicated by the broken line 31 may have a configuration other than that of the constant current source. Further, the active analog memory according to the present invention is
Needless to say, the present invention can be applied to other than the memory circuit of the neural network.

[0055]

According to the present invention, an active analog memory is realized with a very simple circuit configuration as compared with the conventional circuit configuration using a multi-bit D / A converter and an A / D converter. It becomes possible to do.

In particular, by adopting a circuit configuration that operates in a time-division manner, an active analog memory capable of simultaneously storing a plurality of analog voltage values can be configured, and is applied to a memory circuit that configures each synapse connection of a neural network, for example. It becomes possible to do. In this case, one set of integrating means and comparing means may be prepared for a plurality of capacitor elements, and therefore integration is easy.

Further, in order to increase the accuracy (step width) of the storage voltage value of the capacitor element, it is necessary to reduce the value of the pulse voltage and increase the integration speed of the integration means.
Since the leak rate of charges of the capacitor element is about one day to several days even at room temperature, even if the time division structure is adopted, it is possible to sufficiently cope with the simple circuit structure.

As a result, according to the present invention, it is possible to increase the number of capacitor elements to be refresh-processed in parallel by the time-division processing to a considerably large number, and to cope with a large-scale neural network or the like. Become.

[Brief description of drawings]

FIG. 1 is a first principle block diagram of the present invention.

FIG. 2 is a second principle block diagram of the present invention.

FIG. 3 is a configuration diagram of a first embodiment of the present invention.

FIG. 4 is an explanatory diagram of an integration operation.

FIG. 5 is an operation timing chart of the first embodiment.

FIG. 6 is a circuit configuration diagram of a constant current source.

FIG. 7 is a configuration diagram of a second embodiment of the present invention.

FIG. 8 is an operation timing chart of the second embodiment.

FIG. 9 is a principle configuration diagram of a first conventional example of an active analog memory.

FIG. 10 is a principle configuration diagram of a second conventional example of an active analog memory.

[Explanation of symbols]

11 Integrating Means 12 Comparing Means 13, 14 Switching Means C _mem Capacitor

Claims (3)

[Claims] 1. An analog memory for storing analog stored data as a charge in a capacitor element (C _mem ), which sequentially integrates input pulse voltages and outputs the integrated voltage as an analog integrated voltage. (11)
A switch means (13) for selectively applying the integrated voltage from the integrating means to the capacitor element (C _mem ); and the integrated voltage from the integrating means (11) and the storage in the capacitor element (C _mem ). The integrated voltage corresponding to the stored electric charge is compared, and when the integrated voltage exceeds the accumulated voltage, the integrated voltage from the integrating means (11) is applied to the switch means (13). The voltage is applied to the capacitor element (C _mem ) and the integration means (1
Comparing means (12) for executing a series of operations for clearing the integrated voltage in 1) within a time shorter than a time in which the stored voltage in the capacitor (C _mem ) is reduced by the value of the pulse voltage. An active analog memory characterized in that. 2. An analog memory for storing analog stored data in a capacitor element (C _mem ) as electric charges, and integrating means for sequentially integrating pulse voltages that are input and outputting the integrated voltage as an analog integrated voltage. (11)
A switch means (13) for selectively applying the integrated voltage from the integrating means to the capacitor element (C _mem ); and the integrated voltage from the integrating means (11) and the storage in the capacitor element (C _mem ). The integrated voltage corresponding to the stored electric charge is compared, and when the integrated voltage exceeds the accumulated voltage, the integrated voltage from the integrating means (11) is applied to the switch means (13). The voltage is applied to the capacitor element (C _mem ) and the integration means (1
The integrated voltage in 1) is converted into the capacitor element (C _mem )
Comparing means (12) for executing a series of operations for setting the storage voltage before update of the above in a time shorter than the time when the storage voltage in the capacitor (C _mem ) decreases by the value of the pulse voltage. An active analog memory having. 3. A plurality of sets of constituent parts (# 1 to #N) composed of the capacitor element (C _mem ) and the switch means (13) for the integration means (11) and the comparison means (12). The comparison means (12) is configured to be connected in parallel, and the comparison means (12) performs the series of operations by the comparison means and the integration means (11) and the respective constituent parts (# 1 to #
N) The active analog memory is characterized in that the connection with N) is executed sequentially while switching in time division.