JP2855470B2 - Power control circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparison circuit for comparing a plurality of determination target potential levels in a time-division manner, and more particularly, to a power supply potential of a plurality of power supply servo circuits such as a copying machine. The present invention relates to a power supply control circuit that outputs a result signal after successive comparison. In particular, it relates to a case where these circuits are configured on a semiconductor integrated circuit (IC).

[Conventional technology]

Conventionally, one capacitor for sampling and holding each comparison reference potential for comparing determination potentials supplied from each level determination signal source is shared in a time-division manner.

FIG. 8 is a circuit configuration diagram of a power supply control circuit showing one embodiment of this conventional example.

In this figure, reference numeral 1 denotes an equivalent voltage source constituting a first level-determined signal source, one end of which is grounded and the other end of which is the first level-determined signal source.
Is connected to the output resistor 2 which constitutes the signal source for determining the level to be determined. The other end of the output resistor 2 is connected through a signal line 10 to one end of a capacitor 3 whose other end is grounded. 1 above
1 to 3 constitute a first level-determined signal source.

Reference numeral 4 denotes an equivalent voltage source constituting a second level-determined signal source, one end of which is grounded and the other end connected to an output resistor 5 constituting a second level-determined signal. Output resistor 5
Is connected through a signal line 11 to one end of a capacitor 6 whose other end is grounded. The above-mentioned 4 to 6 constitute a second level-determined signal source.

Reference numeral 7 denotes a D / A converter whose one end is grounded. When digital data sent from the timing generator 123 is set via the data bus 24, an analog signal corresponding to the digital data on a one-to-one basis is set on a signal line 45. Is output instantaneously. The signal line 45 is connected to one end of the resistor 8,
The other end of the resistor 8 is connected to a capacitor 9 having one end grounded.
It is connected to the. The above items 7 to 9 constitute an actual D / A conversion circuit, and the output impedance is such that the impedance in which the resistor 8 and the capacitor 9 are originally present as a distributed constant can be approximately displayed as a lumped constant. The D / A converter 7 includes first level-determined signal sources 1 to 3,
It functions as a comparison reference power supply for comparing the judgment potentials of the second level-judgment signal sources 4 to 6, and charges a capacitor circuit, which will be described later, to a reference reference potential for each power supply.

The signal line 10 is connected to the drain terminal of an N-channel MOS transistor (hereinafter referred to as N-MOS) 14 and the source terminal of a P-channel MOS transistor (hereinafter referred to as P-MOS) 15. And P-MOS15
Are connected to the signal line 13.

On the other hand, the signal line 11 is connected to the drain terminal of the
The source terminal of the N-MOS 17 and the drain terminal of the P-MOS 18 are connected to the signal line 13.

Similarly, the signal line 12 is connected to the drain terminal of the N-MOS 20 and the source terminal of the P-MOS 21, and the source terminal of the N-MOS 20 and the drain terminal of the P-MOS 21 are connected to the signal line 13. The signal line 13 is grounded to the ground through a capacitor 46, and is connected to the signal line 35 through a capacitor 47. The signal line 35 is connected to the drain terminals of the N-MOSs 31 and 36 and the source terminals of the P-MOSs 32 and 37. However, the N-MOS 31, P-MOS 32 and N-MOS 36, P-MOS 37 each constitute a switch portion of a pair of analog switches. The source terminal of the N-MOS 31 and the drain terminal of the P-MOS 32 are both connected to one end of the resistor 33. The other end of the resistor 33 is connected to the + terminal of the voltage source 34,
The negative terminal of the voltage source 34 is grounded.
The source terminal of the N-MOS 36 and the drain terminal of the P-MOS 37 are connected to the signal line 39.

Signal line 39 is connected to an input terminal of the logic determination unit 40, the L-level at its output if the small input signal potential than the voltage V _TH of the voltage source 34 of the signal line 39, and in greater than voltage V _TH If there is, an H level is output. The output line (signal line) 42 of the logic judgment unit 40 is connected to the latch 43 and the data input terminal D of the shift register 48. The Q output terminal of the latch circuit including the latch 43 is connected to the output terminal 44 that outputs the result of the comparator. Note that the timing generator 23
The terminal L1 sends a control signal to the D / A converter 7 through the data bus 24, and the N-MOS 14, P
A control signal is sent from the terminal L2 to the MOS 15 and the inverter 16 through the signal line 25, and a control signal is sent from the timing generator 23 to the transfer gate including the N-MOS 17, the P-MOSU 18 and the inverter 19 through the signal line 26 to the terminal L3. Sent out.

A control signal is sent from the timing generator 23 to the transfer gate including the N-MOS 20, the P-MOS 21, and the inverter 22 through the signal line 27 at the terminal L4.

A control signal is sent from the timing generator 23 to the transfer gate composed of the N-MOS 31, the P-MOS 32 and the inverter 41 through the signal line 28 at the terminal L5.

A control signal is sent from the timing generator 23 to the transfer gate including the N-MOS 36, the P-MOS 37, and the inverter 38 through the signal line 29 at the terminal L6.

Further, a control signal is transmitted from the timing generator 23 to the L terminal of the latch 43 through the signal line 30 from the terminal L7.
Further, the clock input terminal of the shift register 48 has a terminal
The control signal is sent from the L8 through the signal line 49 to the timing generator 23.
Sent from.

Note that the signal line 25 is connected to the gate of the N-MOS 14 and, at the same time, to the input terminal side of the inverter 16. The output terminal of the inverter 16 is connected to the gate of the P-MOS 15. The signal line 26 is connected to the gate of the N-MOS 17 and the input terminal of the inverter 19. The output terminal of the inverter 19 is connected to the gate of the P-MOS 18. Signal line 27
Is connected to the gate of the N-MOS 20 and the input terminal of the inverter 22, and the output terminal of the inverter 22 is connected to the gate of the P-MOS 21. The signal line 28 is connected to the gate of the N-MOS 31 and the input terminal of the inverter 41, and the output terminal of the inverter 41 is connected to the gate of the P-MOS 32. The signal line 29 is connected to the gate of the N-MOS 36 and the input terminal of the inverter 38, and the output terminal of the inverter 38 is connected to the P-MOS 37
Connected to the gate.

50 is an A / D conversion control circuit and its data input bus is 48-1
Are connected to n Q output terminals of an n-stage shift register 48 through the n data buses. The control data output terminal is connected to the A / D conversion control signal input terminal of the timing generator 23 through the signal bus 50-1 of 50-1. The A / D conversion start control output terminal is connected to the signal line 50.
-2 is connected to the reset terminal R of the shift register 48. The result of the A / D conversion is output to the output terminal 50-3.

 Next, the operation will be described.

D / D from the timing generator 23 as the timing control means
Digital potential data (data DATA1) corresponding to the determination potential set in the equivalent voltage source 1 serving as the first level determination signal sources 1 to 3 is supplied to the D / A converter 7 serving as A conversion means on the data bus. When input through the D / A converter 24, the D / A converter 7 charges the capacitors 46 and 47 constituting the capacitor circuit to the comparison reference potential corresponding to the determination potential set in the equivalent voltage source 1. And a timing generator at a predetermined timing.
When a switching control signal is sent to an analog switch described later from 23, the chopper type comparison means outputs a comparison result between the determination potential supplied from the equivalent voltage source 1 and the first comparison reference potential.

When the first comparison processing is completed, the next switching control signal is sent from the timing generator 23 to the multi-stage analog switch at a predetermined timing, and the second level determination for the D / A converter 7 is performed. When the next digital potential data (data DATA2) corresponding to the determination potential set in the equivalent voltage source 4 serving as the signal sources 4 to 6 is input via the data bus 24, the D / A converter 7 outputs the equivalent voltage. Capacitors 46, 4 up to the comparison reference potential with respect to the determination potential set in source 4.
Charge 7. Then, a switching control signal is transmitted from the timing generator 23 to each analog switch at a predetermined timing, and a comparison result between the determination potential supplied from the equivalent voltage source 4 and the second comparison reference potential is output from the chopper type comparing means. Let it.

Here, the operation of FIG. 8 will be described in detail with reference to FIGS. 9 to 11.

9 and 10 show examples A and B of equivalent circuit diagrams at a predetermined timing of the circuit shown in FIG. 8, and the same components as those in FIG. 8 are denoted by the same reference numerals.

FIG. 11 is a timing chart for explaining the operation of FIG.

In this figure, DATA1 and DATA2 are data, output from the terminal L1 of the timing generator 23 shown in FIG. 8 to the data bus 24, and supplied to the comparison reference signal lines generated by the D / A converter 7, respectively. You. That is, the data DATA1 indicates the set voltage value of the comparison reference signal source corresponding to the first level-determined signal source composed of the above-described 1 to 3, and the data DATA2 indicates the second voltage composed of the above 4 to 6 Of the reference signal source for comparison corresponding to the level-determined signal source of FIG.

Now, the data DATA1 is output from the terminal L1 onto the data bus 24, and after a lapse of time T1, the signal lines 26,
When the output of the terminal 29 changes from “1” to “0”, the signal lines 27 and 28 for the terminals L4 and L5 change from “0” to “1” at a time t3 when Δt has elapsed from that time.

The D / A converter 7 charges the capacitor 9 through the resistor 8 during the time T1 after DATA1 is output from the terminal L1 onto the data bus 24. At this time, if less than 1/10 of the value constant tau ₁ is for the time T1 when the indicated product of the resistor 8 and the capacitor 9, at time t2, the voltage across the capacitor 9, the digital data DATA1 The error range is ± 0.1% of the indicated voltage value. When a logical value “1” is set on the signal lines 27 and 28 corresponding to the terminals L4 and L5, a logical value “1” is added to the N-MOSs 20 and 31, and the logical values “1” are applied to the gates of the P-MOSs 21 and 32. Since the logical value “0”, which is obtained by inverting “1” by the inverters 22 and 41, respectively, is added, the N-MOSs 20, 31 and the P-MOSs 21 and 32 are all turned on, the signal line 12 is connected to the signal line 13,
One end of 33 is connected to the signal line 35. At the timing t _3, the signal lines 25 and 26 corresponding to the terminal L2, L3, L6,
Since the logical value “0” is output to 29, the N-MOS 14,
The logic value “0” is applied to the gates of 17, 36, and the P-MOS15, 1
Each of the gates 8 and 37 has a logical value "1" which is an inverted signal of a logical value "0" through inverters 16, 19 and 38, respectively, and thus is composed of 14 to 16, 17 to 19 and 36 to 38, respectively. The analog switch is turned off. Therefore, the timing
The time T3 range t ₄ from t _3, a closed circuit shown in FIG. 9 is formed, the charge is charged in the capacitor 46 and 47. now,
By charging with the total resistance of each of the resistance values 8, 51, 52, and 33, both terminal voltages of the capacitor 47 are changed from the output voltage V _{DA of the} D / A converter 7 to the voltage of the voltage source 34 within a sufficiently short time T3. Error ± 0 from the value of voltage V _T (V _DA −V _th ) obtained by subtracting V _th (logic potential).
It should reach within the range of about 5%.

Upon reaching the timing t _4, the signal at the terminal L4, L5 is changed from "1" to "0", N-MOS20,31 and P
− MOS21, 32 are all turned off and capacitors 46, 47
Is in a state not connected to any of the signal lines 13, 39, and 33. After a time δt has elapsed from the timing t _4, when it is time t _5, the data of the data bus 24 corresponding to the terminals L1 alternative from the data DATA1 to the data DATA2, at the same time the logic value to the terminals L2 and the terminal L6 "1" is output Is done. Therefore, the analog switch including the N-MOS 14, the P-MOS 15, and the inverter 16 and the analog switch including the N-MOS 36, the P-MOS 37, and the inverter 38 are turned on, and the signal line 10 is connected to the signal line 13; 35 is connected to the signal line 39.
For this reason, the D / A converter 7 applies an analog voltage corresponding to the data DATA2 (digital data) to the signal line at that timing.
45, and charging of the capacitor 9 through the resistor 8 is started. The capacitor circuit composed of the capacitors 46 and 47 is configured as shown in FIG.

That, and charges the capacitor 3 advance through the output voltage output resistor 2 and the signal line 10 of the equivalent voltage source 1, and its potential as V _1.

The signal line 10 is connected to the resistors 52, 5 of the N-MOS 14 and the P-MOS 15
3 when connected to the signal line 13 through, if about one value of 10 ³ minutes of capacity capacitance of the capacitor 3 of the capacitor 46, the capacitance of the capacitor 46 is charged to almost instantly by the capacitance of the capacitor 3, the approximate to the potentials can be V ₁ and Chaku做, the potential of the resulting signal line 35, V ₁ -V _th next, as long the input impedance of the inverter circuit of the logic decision 40 is considered to ∞ approximately The signal line 39 has the same potential as the signal line 35.

Therefore, the potential of the signal line 39 becomes V ₁ −V _DA + V _th ,
When V ₁ > V _DA , the potential of the signal line 39 is higher than the potential V _th , and when V ₁ <V _DA , the potential of the signal line 39 is lower than the potential V _th . By the way, the logic determiner 40 determines that the input voltage is
If greater than V _th, and outputs the H level signal at its output terminal, if smaller than the potential V _th, since a circuit for outputting an L level signal at its output terminal, a V _1> V _DA sometimes L level is output, it can be seen that the difference in the magnitude of the potential V ₁ and the potential V _DA is output to the output terminal of the logic determiner 40 H, the L level.

Then, upon reaching the timing t _6, the latch control input terminal L of the latch 43 from the terminal L7 timing generator 23 H
The level signal is input, and the signal on the signal line 42 is
And is output to the output terminal 44. The timing signal terminals L7 at t ₇ the signal of the signal line 42 at the moment of change from the H level to the L level is latched by the latch 43, the potential V ₁ and the potential V _DA magnitude comparison result of the voltage of the timing t
_{At 18} , the signal is output to the output terminal 44 until the H level signal is input again to the terminal L7. Minute time from the timing t ₇ δt
When (5n~100nsec) has elapsed, the signal terminal L2 and the terminal L6 is changed from H level to L level, the voltage comparison cycle of the potential V ₁ and the potential V _DA is completed.

In this way, a comparison of the timing t ₃ ~t ₈ by a pair of the level decision signal source and the comparison reference signal source is completed once. The voltage and the voltage of the comparison reference signal source to it in the same operation timing t ₉ ~t second of the level decision signal source at _14, i.e. comparison a similar analog voltage representing the digital data of the data DATA2 It is executed in a timing sequence. However, the this period, different from the first operation in the period of time t ₃ ~t ₈ is a connection operation of the level judgment signal source. That is, the timing t ₃ ~t ₈
Timing t ₁₁ in the period of time t ₃ ~t ₁₄ to terminal L2 during the period corresponds to the timing t ₅ ~t ₈ is H level
~t ₁₄ in terminal L3 becomes H level, the second voltage source consists of the 4-5 is connected to the signal line 13. And
Second operation different as the period of the timing t ₃ ~t ₈ is latching, timing t ₉ ~t ₁₄ shift register 4,
8 is used as a latch circuit. That is, when reaching the timing t _12, H-level signal from the terminal L8 of the timing generator 23 to the clock input terminal of the shift register 48 is inputted, the signal of the signal line 42 is incorporated into the first stage register of the shift register 48, The data output to the data bus 48-1 connected to the Q output terminal of the shift register 48 and previously input to the shift register 48 are shifted one bit at a time to the most significant bit (MSB) side.
Then, the data output to the Q output terminals Q _{0 to} Q _n of the shift register 48 is the result of the magnitude comparison between the voltage V ₂ and the voltage of the potential V _DA , and the H level is again applied to the clock input terminal at timing t _24. Until a signal is input and taken into the shift register 48, it is output in the same state on the data bus 48-1. The third different as the period of the timing t ₃ ~t ₈
The operation of is based on the data on the data bus 24,
In between t ₉ timing t _14, from the timing t ₉ to the timing t ₁₁ is set data DATA2, from the timing t ₁₁ to the timing t ₁₄ data DATA1 is set. For other basic comparison operation, and duration of the timing t ₃ ~t _8, are the same between the timing t ₉ ~t _14, in each timing t ₃ time t _9, the timing t ₄ is a timing t ₁₀ , the timing t ₅ the timing _11, the timing t ₆ is a timing t _12, the timing t ₇ is the timing _13, the timing t ₈ is a timing t ₁₄
Corresponding to Furthermore, we table again to the timing t ₃ ~t ₈ operation and the same operation timing t ₁₅ ~t ₂₀ period, the timing
t ₉ The same operations as in the period of ~t ₁₄ is a timing t ₂₁ ~t ₂₅
Again, the comparator alternates between the two comparisons.

It should be noted that the equivalent voltage source 1 can be considered as an arbitrary controlled circuit portion whose voltage increases when the data on the output terminal 44 is "0" and decreases when the data on the output terminal 44 is "1".

On the other hand, the equivalent voltage source 4 is a voltage source to be subjected to A / D conversion. The A / D conversion is performed by the timing generator 23,
This is performed by controlling the shift register 48. That is, the A / D conversion control circuit 50 sends a start signal on the signal line 50-2 at the start of the A / D conversion, and
A / D conversion control digital data is transmitted to the timing generator 23 through the bus line 50-1 at the same time as the resetting of 48. Timing generator 23 puts this data on terminal L1.
Output as DATA2. The A / D conversion control circuit 50 compares the comparison result between the voltage source 4 to be A / D converted and the voltage value indicated by the A / D conversion control digital data with the Q value of the shift register 48.
Recognize based on the output data, and if the comparison result is greater than the voltage value of the voltage source 4 to be A / D converted from the A / D conversion control digital data value, DATA2 is output at the next comparison. A / D conversion control digital data that is set as DATA2 at the next comparison if the magnitude of the comparison result is the opposite. Is operated so that the value of the A / D conversion control digital data gradually approaches the voltage value of the voltage source 1-1 to be A / D converted. This operation is performed when the number of stages n of the shift register 48 is one.
The number of times required for A / D conversion operation, and each time A / D conversion ends
At the same time that the data of the A / D conversion result is output to the A / D conversion result output terminal 50-3, the signal of the next A / D conversion start is output to the signal line 50-2 and the shift register 48 is reset. .

[Problems to be solved by the invention]

The prior art has only one sample-hold capacitor, and thus has the following disadvantages.

(1) Even if the timing is devised for high-speed operation, control is performed in a time-division manner, so that the control target increases in proportion to the increase of the control target, and the D / A converter samples the comparison reference potential for increasing each control target. As a result of reducing the time for charging the hold capacitor, control requiring a certain level of accuracy or higher becomes impossible.

(2) Even if an attempt is made to execute high-precision control at a specific timing and the time for charging the sample-and-hold capacitor by the comparison reference power supply is increased in the time division, one time for another control is correspondingly increased. As a result of having to shorten the charging time of the sample and hold capacitor by the comparison reference voltage source in the comparison, there is a disadvantage that the accuracy required for the control required in the comparison cannot be obtained.

(3) In the time-division control using one sample-hold capacitor, all the information based on the sample-held charge of the previous comparison is erased every time the comparison is performed, and the comparison is always performed. It is necessary to start recharging the voltage from the comparison reference potential of the other servo control circuit one time before. In charging the voltage of the least significant bit (LSB) during A / D conversion, control is performed in a time-division manner. As the number of controlled objects increases, the charging time for the sample-and-hold capacitor decreases, and the accuracy of A / D conversion decreases due to the change in the comparison reference voltage caused by the change in the charge start voltage.

(4) If the density of the number of comparisons is increased to improve the control accuracy of a specific feedback control circuit, the control accuracy of another feedback control circuit may be reduced, or the feedback control circuit may be increased to a certain number or more. Can not be increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems of the conventional example, and has as its object to provide a power supply control circuit capable of performing high-accuracy control.

[Means for solving the problem]

Therefore, in the present invention, the determination potentials of the plurality of level determination signal sources are compared with the respective comparison reference potentials respectively corresponding to the determination potentials, and the determination potentials of the respective level determination signal sources are determined by the respective predetermined potentials. A plurality of capacitor circuits that sample and hold each of the comparison reference potentials for comparing a determination potential supplied from each of the level-determined signal sources,
A chopper type comparing means comprising a multi-stage analog switch for comparing the respective reference potentials held in the capacitor circuit and the determination potentials of the respective level determination signal sources while sequentially switching the digital potential data; D / to charge the capacitor circuit to each comparison reference potential set to each of the level determination signal sources based on
A power supply control circuit comprising: A conversion means; and timing control means for controlling switching of the multi-stage analog switches based on a transmission state of each digital data.

The plurality of capacitor circuits include at least one of an A / D conversion circuit capacitor circuit, a high-precision feedback control capacitor circuit, and a switching control capacitor circuit for switching signals of a plurality of level determination signal sources in a time-division manner. It is characterized by including.

In addition, one of the plurality of capacitor circuits is used for switching control for switching the signals of the plurality of level-determined signal sources and the control signal of the A / D conversion circuit in a time-division manner, and the other one is an independent high-level signal. It is characterized in that it is used for accuracy feedback control.

Further, the capacitor circuit used for high-precision feedback control is characterized in that the number of comparisons is set to two or more with respect to the number of times of charging.

In the case of control having a plurality of capacitor circuits used for high-precision feedback control and having no charging timing immediately before comparison, one uses the charging timing of normal comparison control, and the other uses the charging timing of comparison. It is characterized by using timing.

The switching control is characterized in that one of the flag switching and the IC mask switching is selected and changed.

The comparison timing is used exclusively for the high-accuracy feedback control.

In addition, the insertion timing of the high-precision feedback control using two capacitors is characterized in that it is at the time of charging the circuit that requires the most high-precision control among the feedback control circuits using one capacitor in time division. I do.

A plurality of capacitor circuits, a chopper type comparison unit, a D / A conversion unit, a timing control unit, and a central control unit for changing the timing of the timing control unit are provided on a one-chip microprocessor. It is an object of the present invention to achieve the above object by providing a power supply control circuit characterized in that:

[Action]

With the above-described configuration, the power supply control circuit of the present invention switches the multi-stage analog switches by the timing control means in order to compare it with the determination potential supplied from each level determination signal source, and at the same time, switches each of the plurality of analog switches. Each digital potential data corresponding to the level determination signal source is input to the D / A conversion means. The D / A conversion means sets a predetermined capacitor in a capacitor circuit composed of a plurality of capacitors up to each comparison reference potential set corresponding to each level determination signal source based on the input digital potential data. Charge and sample hold. Then, when the switching control signal of the analog switch is sent out by the timing control means at a predetermined timing, the chopper type comparison means compares the first determination potential with the first comparison reference potential, and further performs the same as above. The comparison result is output while sequentially switching the second, third, and fourth potentials, and the power supply is controlled based on the comparison result.

In particular, since the power supply control circuit of the present invention includes a plurality of the sample and hold capacitor circuits, an independent sample and hold capacitor circuit dedicated to a feedback control circuit that requires A / D conversion high-precision control can be assigned, A / D conversion and feedback control with high accuracy are possible.

The multiple capacitor circuits to be sampled and held are used in the A / D converter circuit capacitor circuit for sampling and holding the comparison reference potential for high-precision control, and the rest are used in a time-sharing manner to control multiple feedback control circuits. .

In addition, one of the plurality of capacitor circuits uses A / D conversion and control of a plurality of feedback control circuits in a time sharing manner,
The other one is used independently for sample and hold of a comparison reference potential dedicated to a control circuit requiring high precision control.

Further, the control of the capacitor circuit applied to the high-precision feedback control is performed by setting the number of comparisons to 2 for the number of times of charging.
The ratio is not less than times.

In the comparison control having no charging timing immediately before the comparison, one of the capacitor circuits applied to the high-precision feedback control is used at the charging timing of the normal comparison control, and the other is used at the timing of the comparison. .

Further, the switching control of the circuit can be changed by switching the flag or switching the mask of the IC.

The comparison timing of the capacitor control is used exclusively for high-precision feedback control so that comparison of other control circuits or charging operation is not performed during that time.

The timing at which a plurality of capacitor control timings are inserted is used at the timing of charging a circuit that requires the most accurate control among feedback control circuits that use one capacitor in a time-division manner.

Then, the plurality of capacitor circuits, the chopper type comparing means, the D / A converting means, the timing control means, and the central control device of the power supply control circuit according to the present invention are formed by a one-chip microprocessor, Power can be reduced in size.

〔Example〕

 Hereinafter, the present invention will be described based on examples.

(First Embodiment) FIG. 1 is a circuit diagram of a power supply control circuit according to a first embodiment of the present invention, FIG. 2 is an explanatory diagram of some analog switch circuit symbols in the first embodiment, and FIG. FIG. 1 is a driving time chart of FIG. 1 of one embodiment, FIG. 4 is a circuit diagram when a conventional example for explanation is extended to four equivalent voltage sources, and FIG. 5 is a driving time chart of FIG.

Note that the same (corresponding) components as those in the conventional example shown in FIGS. 8, 9, 10, and 11 are denoted by the same reference numerals, and redundant description will be omitted.

In FIG. 1, reference numeral 51 denotes an equivalent voltage source constituting a third level-determined signal source, one end of which is grounded, and
Is connected to the output resistor 52 constituting the signal source for determining the level. The other end of the output resistor 52 is connected through a signal line 65 to one end of a capacitor 53 whose other end is grounded. 51 above
53 constitute a third level-determined signal source.

An equivalent voltage source 79 constitutes a fourth level-determined signal source. One end is grounded, and the other end is connected to an output resistor 78 constituting a fourth level-determined signal source. Output resistor
The other end of 78 is connected to one end of a capacitor 80 whose other end is grounded through a signal line 77. The above 77 to 80 constitute a fourth level determination signal source.

The D / A converter 7 compares the determination potentials of the first to-be-determined signal sources 1 to 3, the second to-be-determined signal sources 4 to 6, and the third to-be-determined signal sources 51 to 53. , And charges a capacitor to be described later to a reference potential for each power supply.

Reference numerals 54, 55, 60 to 64, 71, 75 denote analog switches, which in the conventional example are switch sections composed of an N-MOS, a P-MOS and an inverter, and are indicated by symbols for simplicity.

Incidentally, the elements constituting the analog switch of FIG. 8
20, 21, and 22 are replaced with the analog switch 60 of FIG.
Similarly, elements 31, 32, and 41 in FIG. 8 are analog switches 61 in FIG. 1, and similarly, elements 36, 37, and 38 are analog switches 62 in FIG.
In addition, the elements 14, 15, 16 are connected to the analog switch 63, and the elements 17, 18,
19 is replaced by an analog switch 64 to constitute a multi-stage analog switch. FIG. 2 shows a connection example of the terminals.

In the capacitor circuit composed of the conventional capacitors 46 and 47 shown in FIG. 8, the capacity of the capacitor 46 can be omitted as compared with the capacity of the capacitor 47 in FIG. 8, and only the capacitor 47 will be considered. The capacitors 56 and 73 shown in FIG. 1 have the same function as the capacitor 47.

The control gates of the transfer gates 54, 55, 75, 71 are connected to terminals L10, L11, L13, L14 of the timing generator 23 through signal lines 70, 68, 76, 72, respectively. 58,
Reference numeral 82 denotes a latch circuit for latching the comparison results for the second and third control circuits.
Connected to 9,81. The data input terminal I is connected to the signal line 42, and the latch signal input terminal
Latch 58 is connected to signal terminal L9 of timing generator 23 and signal line 57.
Latch 82 is connected to the timing generator
It is connected to 23 signal terminals L12 via signal lines 83.

 Next, the operation will be described.

Regarding the timing, in the conventional example using one capacitor, consider the case where it is extended to control four equivalent voltage sources (one of which is the equivalent voltage source as an A / D conversion target), and understand by comparing with it. First, the case will be described.

FIG. 4 shows a circuit diagram when the conventional example for explanation is extended to four equivalent voltage sources. To consider this circuit in the circuit shown in FIG. 1, the signal lines 66 and 74 and the signal line 13 should be short-circuited, and the analog switch 55, the capacitor 56, the analog switch 71 and the capacitor 73 should be deleted. This will be described with reference to FIG. On the terminal L1, digital values DATA3 and DATA4 corresponding to the voltages of the comparison reference signal sources with respect to the third and fourth equivalent voltage sources correspond to the voltages of the comparison reference signal sources with respect to the first and second equivalent voltage sources. Digital value DATA
1, is added to DATA2, DATA1, DATA2, DATA3, it shall be output in sequential time intervals for each T ₄ in the order of DATA4.

Voltage and digital data of level-determined signal sources 1-3
T ₃ ~t comparison with the analog voltage is performed DATA1 is shown
And _8, t ₉ ~t ₁₄ which compares the analog voltage indicating the voltage and the digital data DATA2 of the level judgment signal source 4-6 is performed
The signal at the period of the switching timing of which is identical to the timing chart of the conventional example except the data on the terminals L1 between t ₁₁ ~t ₁₄ shown in FIG. 11. The same operations are performed at timings t _{15 to} t ₂₀ by the third level-determined signal sources 51 and 5.
The comparison between the voltage of No. 3 and the voltage of the reference signal source for comparison, that is, the analog voltage indicated by the digital data of the data DATA3 is executed in the same timing sequence.
However, the this period, different from the first operation in the period of time t ₃ ~t ₈ is a connection operation of the level judgment signal source. That is, the timing t ₁₅ to the terminal L2 in the period of time t ₃ ~t ₈ corresponds to the timing t ₅ ~t ₈ is H level
Timing t ₁₇ ~t ₂₀ in terminal L10 becomes H level during the period ~t _20, third voltage source consists of 51 to 53 is connected to the signal line 13. Then, a second operation different from the period of the timing t ₃ ~t ₈ is latching, timing t
₁₅ ~t ₂₀ the latch 58 is used. That is, when reaching the timing t _18, H-level signal from the terminal L9 timing generator 23 to the latch control input terminal L of the latch 58 is inputted, the signal of the signal line 42 as it is passed through the latch 58, the output terminal is output to the 59, the terminal L9 at the timing t ₁₉
The moment the signal changes from H level to L level, the signal of the signal line 42 is latched in the latch 58, the voltage V ₂ and the potential V _DA
The digital data DATA3 is set again on L1 and the H level signal is again input to the terminal L9. A period is different third operation timing t ₃ ~t duration and timing t ₉ of ₈ ~t ₁₄ period and the timing t ₁₅ ~t _20, the data present on data bus 24, i.e., the timing generator in data output on terminal L1 of 23, between the timing t ₉ of the timing t _14, from the timing t ₉ to the timing t ₁₁ are set data DATA2, the data from the timing t ₁₁ to the timing t ₁₄ DATA3 is set.

Timing between the timing t ₁₅ in the timing t ₂₀
From t ₁₅ to the timing t ₁₇ is set data DATA3, from the timing t ₁₇ to the timing t ₂₀ DATA4
Is set.

Voltage and digital data of level-determined signal sources 1-3
DATA1 is the same operation as the switching signal in the period of t ₃ ~t ₈ which compares the analog voltage is carried out indicated, timing
voltage and the voltage of the comparison reference signal line to it for t ₂₁ ~t the ₂₆ fourth object level determination signal source 78-80, i.e. data
The comparison with the analog voltage indicated by the digital data of DATA4 is executed in a similar timing sequence. However,
And this period, different from the first operation in the period of time t ₃ ~t ₈ is a connection operation of the level judgment signal source. That is, the timing t ₂₃ ~t ₂₆ in terminal L13 in a period of time t ₂₁ ~t ₂₆ to terminal L2 in the period of time t ₃ ~t ₈ corresponds to the timing t ₅ ~t ₈ is H level, the H level, A fourth voltage source composed of 78 to 80 is connected to the signal line 13. Then, a second operation different from the period of the timing t ₃ ~t ₈ is latching, the latch 82 at the timing t ₂₁ ~t ₂₆ is used. That is, when reaching the timing t _18, H-level signal is input from terminal L12 of the timing generator 23 to the latch control input terminal L of the latch 82,
Signal of the signal line 42 as it is passed through the latch 82 is output to the output terminal 81, Fukyoku terminal L12 at the timing t ₂₅ is H
At the moment of change from the level to the L level, the signal of the signal line 42 is latched in the latch 82, the magnitude comparison result between the voltage potential V ₃ and the potential V _DA is again digital data DATA on terminal L1
The signal is continuously output to the output terminal 81 until 4 is set and the H level signal is input again to the terminal L12. Also, the timing
t ₃ is different third operation and duration of the period and the timing t ₂₁ ~t ₂₆ periods ~t ₈ and the timing t ₉ ~t _14, the data present on the data bus 2, i.e., the terminal of the timing generator 23 data to be output on L1, in between time t ₉ the timing t _14, from the timing t ₉ to the timing t ₁₁ are set data DATA2, from the timing t ₁₁ to the timing t ₁₄ is set data DATA3 ing.

Further, from the timing t ₂₁ from the timing t ₂₁ in between the timing t ₂₆ to the timing t ₂₃ are set data DATA4, from the timing t ₂₃ to the timing t ₂₆ is
DATA1 is set.

With respect to the other basic comparison operation, timing t ₉ ~
Comparative results t ₁₄ is the period from the timing t ₃ ~t ₈ except that it is stored in place of the latch in the shift register 48, timing t ₉ ~t ₁₄ and the timing t ₁₅ ~t ₂₀ and the timing t ₂₁ ~t Same between ₂₆ , each timing
t ₃ is a timing t ₉ and the timing t _15, the timing t ₂₁
In addition, timing t ₄ is timing ₁₀ and timing t ₁₆ ,
to t _22, timing t ₅ timing t ₁₁ and timing
to t _17, t _23, the timing t ₆ is a timing t ₁₂ and timing t _8, t _24, the timing t ₇ is a timing t ₁₃ and timing t _19, t _25, timing t ₈ is a timing t ₁₄ and timing t ₂₀ , corresponding to the t _26. Also, the timing t
₃ The same operations as in the period of ~t ₂₆ is assumed to operate repeatedly in the same manner after the timing t _27.

The equivalent voltage source 1, the equivalent voltage source 3, and the equivalent voltage source 4
From the controlled circuit part which operates so that the voltage changes from decreasing to increasing when the data on the output terminals 44, 59 and 81 is "0", and changes from increasing to decreasing when the data is "1". Can be considered as the feedback voltage. The equivalent voltage source 2 is an equivalent voltage to be subjected to A / D conversion.

On the other hand, in the present embodiment, a dedicated sample-hole capacitor 56 is provided in order to control the voltage of the level determination signal source, which requires high control accuracy.
The feature is that a capacitor 73 dedicated to A / D conversion is provided. FIG. 3 shows a timing chart of the operation. For simplicity of explanation, a case where there are four level-determined signal sources is taken as an example, and a comparison is made with a circuit when the conventional example for explanation shown in FIG. 4 is extended to the case of 4-equivalent voltage source control. The operation will be described.

The operation of this embodiment differs from that of the conventional example in that the second equivalent voltage source is considered to be the A / D target power supply in the conventional example, but here the fourth equivalent voltage source is considered to be the A / D target power supply. The operation of the D conversion control circuit is also changed to one that matches the timing. Conventionally, the voltage of the comparison reference signal source with respect to the third equivalent voltage sources 51 and 53 is made conductive by the transfer gate 60, and D /
This is realized by charging the capacitor 47 by the A converter 7, but in this embodiment, the analog switch 55 is turned on instead of the analog switch 60 at the same timing, and the capacitor 56 is connected to the capacitor 56 by the D / A converter 7. It is realized by charging.

Similarly, in the conventional example, the voltage of the comparison reference signal source for the fourth equivalent voltage sources 78 to 80 is realized by turning on the transfer gate of the analog switch 60 and charging the capacitor 47 by the D / A converter 7. However, in this embodiment, this is realized by turning on the analog switch 71 instead of the analog switch 60 at the same timing and charging the capacitor 73 by the D / A converter 7.

If you mentioned in terms of FIG. 5 and the time chart of FIG. 3, in a time t ₁₆ from the timing t ₁₁ to the digital data DATA3 on terminal L1 shown in FIG. 5, if the prior is the output terminal 1 in L4, analog switch 60
There on (ON), and the timing t ₁₅ ~t ₁₆ to charge the capacitor 47 by the D / A converter 7, 1 stood on terminal L11 shown in FIG. 3, it analog switch 55 through a signal line 68
, Which is turned on (ON). During that period, the terminal L4 remains 0 and the gate of the analog switch 60 remains off (OFF), and the D / A converter 7 turns off the capacitor 56. It is configured to charge.

Further, if the conventional example, 1 Gatachi analog switch 60 to the terminal L4 within time t ₂₂ from the timing t ₁₇ to digital data DATA4 on terminal L1 is output on (ON) next D / A converter in t ₂₂ from the timing t ₂₁ to charge the capacitor 47 in the vessel 7, 1 stood on terminal L14, the signal line 72
Is transmitted to the control gate of the analog switch 71, and it is turned on (ON).
On the contrary, L4 remains 0, the gate of the analog switch 60 remains off (OFF), and the D / A converter 7 charges the capacitor 73.

For this reason, the capacitor 56 is always charged to the potential of the comparison reference signal source used for the third level determination signal sources 51 to 53 corresponding to the digital data DATA3, and is switched to another comparison reference signal source to be charged. Therefore, the capacitor 56 is always charged to the potential of the comparison reference signal source corresponding to the digital data DATA3. For this reason, if this method is used, compared to the case where the same capacitor is charged and discharged to different voltage levels during multi-time division, it is easy to use for circuits that require high-accuracy control that is faithful to digital data. Can be realized.

Similarly, the digital data DATA is always stored in the capacitor 73.
4.In other words, since the A / D converter is charged to the A / D conversion comparison reference voltage and is not switched to another comparison reference signal source to be charged, in the case of this method of performing the successive approximation A / D conversion, the comparison reference It is possible to control the change in voltage to be smaller as the number of bits requiring the A / D conversion accuracy becomes smaller, so that even if the charging time to the capacitor 73 becomes shorter, high-precision A / D conversion can be easily performed. Can be realized.

The capacitor 47 is connected to the third level-determined signal source.
High precision control is not required as much as 51 to 53 and the comparison reference voltage for A / D conversion, that is, time division is used for comparison between the first and second level-determined signal sources 1 to 3, and 4 to 5 which require low precision control. It is controlled by charging and discharging time-divisionally.

Second Embodiment FIG. 6 is a circuit diagram of a power supply control circuit according to a second embodiment, and FIG.
The drawing is the drive time chart of FIG. 6 of the second embodiment. The conventional examples shown in FIGS. 8 to 11 and FIGS.
The same (corresponding) components as those of the first embodiment shown in FIG. 5 are denoted by the same reference numerals, and redundant description will be omitted.

FIG. 6 is a circuit diagram showing a second embodiment, in which a flag of a latch 84 and a CPU (central control unit) 85 for changing the timing of the timing generator 23 are different from those of the first embodiment.
Is added. In response to an instruction from the CPU 85, 1 or 0 is set in the flag of the latch 84, that is, the Q output of the latch 84, and an operation is performed such that the timing generated by the timing generator 23 changes according to the value. When the Q output of the flag of the latch 84 becomes 1, the timing generated by the timing generator 23 changes from the basic cycle shown in FIG. 3 to the timing shown in FIG. The basic cycle shown in FIG. 3 is a cycle obtained by repeating the cycle from Ta ₁ to Ta ₂ in FIG.
The conversion data is equivalent except that the converted data changes from DATA2 to DATA1 and the timing is changed accordingly.

The timing shown in FIG. 7 starts from Ta ₂ and starts in the next basic cycle (T
characterized in that the repetition of the a ₁ of Ta ₂ cycles) is the timing that TADD between timing Ta ₃ to start. Among TADD, Ta ₂₁ of Ta ₂ are the same except that the data on the timing and the terminal L1 of the comparison of t ₁₉ from t ₁₇ is DATA2, Ta ₃ from Ta ₂₂ is a timing t ₂₆ from t ₂₃ It is the same except that the data on the terminal L1 is DATA2. Note that between Ta ₂₁ and Ta ₂₂ , δt is considered as T ₁ = T _3. Think of it as a time of size.

Timing from Ta ₂ ta ₂₁ is a charging timing of the original DATA2, timing ta ₃ from ta _22, in the first embodiment is a timing comparison corresponding to the data of DATA3, the second embodiment , The timing of charging the capacitor 47 in the first embodiment is replaced by the comparison.

Thus, the sample and hold capacitors 47,5
The fact that charging and discharging to 6,73 had to be repeated in a time-division manner for each input signal, the timing for charging by using independent capacitors to compare each input signal for high precision control. By omitting and inserting the timing of comparison instead of the timing of charging,
The number of feedback control circuits that perform comparison and determination in a time-sharing manner increases, and it is possible to suppress a decrease in accuracy due to a longer time from the comparison and determination of each feedback control circuit to the next determination.

In this embodiment, it is possible to switch the timing of a necessary application by considering the latch 84 as a latch with set and reset and selecting and fixing one of the set and reset at the time of mask replacement. In addition, by setting the data of the control circuit and the comparison timing of DATA2 and its comparison timing, although the change of the comparison level is large for comparison, the normal 3
The data set time of the D / A converter can be twice as long, which is particularly effective when the basic timing of the time division operation is shorter than the settling time of the D / A conversion.

Further, if the power supply control circuit described in the above embodiment is formed in a CMOS structure on a one-chip microprocessor, a small power supply control device with low power consumption can be obtained.

〔The invention's effect〕

As described above, according to the present invention, a single comparator can easily execute a plurality of feedback controls and A / D conversion with high accuracy. In particular, since there are multiple sample and hold capacitor circuits even if the number of feedback control circuits to be controlled increases, allocate an independent sample and hold capacitor circuit exclusively for the feedback control circuit that requires A / D conversion and high-precision control. Can be
High-precision A / D conversion and feedback control can be easily realized.

If a capacitor circuit for sample hold dedicated to A / D conversion is prepared, there is an advantage that an A / D conversion speed and accuracy higher than in the past can be obtained.

Also, in the capacitor circuit used as the sample and hold,
High accuracy is achieved by using one A / D converter and multiple feedback controls in a time-sharing manner, and using the other one as a sample-and-hold for a comparison reference potential dedicated to a control circuit that requires independent high-precision control. By using an independent capacitor circuit for control, the timing of charging can be omitted.

Further, by inserting a comparison timing instead of a charging timing, it is possible to suppress a decrease in accuracy due to a longer time from the comparison determination of each feedback control circuit to the next determination.

It should be noted that high precision can be maintained by distributing the sample-and-hold capacitor circuit applied to high-precision feedback control to charging timing and comparison timing.

Also, if necessary, the circuit switching control can be performed by switching the flag or by switching the IC mask for the dedicated feedback control that requires high-precision control of the sample-and-hold capacitor circuit, or when performing A / D conversion and multiple feedback control circuits. If division control can be performed, the degree of freedom of system expansion is increased.

Further, the comparison timing of the plurality of capacitor controls is such that the feedback control circuit uses one capacitor in a time-sharing manner to prevent the comparison of other control circuits or the charging operation from being performed during the time, or the timing at which the capacitor control timing is inserted. Among them, by using the circuit at the charging timing of the circuit requiring the highest precision control, the charging time for the high precision comparison can be omitted to a considerable extent, and the high precision control can be realized by a large number of control circuits and time division control.

Then, by configuring together with the CPU on the one-touch IC, it is possible to easily realize inexpensive high-performance multi-power supply control.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a power supply control circuit according to a first embodiment of the present invention, FIG. 2 is an explanatory diagram of an analog switch circuit symbol, and FIG. FIG. 1 is a driving time chart of FIG. 1, FIG. 4 is a circuit diagram when the conventional example for explanation is extended to four equivalent voltage sources, FIG. 5 is a driving time chart of FIG. 4, and FIG. FIG. 7 is a circuit diagram of a power supply control circuit of the embodiment, FIG. 7 is a drive time chart of FIG. 6 of the second embodiment, FIG. 8 is a circuit diagram of a conventional power supply control circuit, and FIG. 9 is a comparator of FIG. FIG. 10 is an equivalent circuit diagram example B of the operation of the comparator of FIG. 8, and FIG. 11 is a driving time chart of FIG. 8 of the conventional example. In the drawings, the same reference numerals indicate the same (corresponding) components. 1,4,51,79… Equivalent voltage source 7… D / A converter 23… Timing generator 40… Logic decision unit 48… Shift register 43,58,82,84… Latch 50 …… A / D conversion control circuit 47,56,73 …… Capacitor circuit 85 …… Central control unit (CPU)

Claims (9)

(57) [Claims] 1. A determination potential of a plurality of level-determined signal sources is compared with respective comparison reference potentials corresponding to the determination potentials, and the determination potential of each of the level-determined signal sources is reduced to a predetermined potential. In a multi-stage power supply control circuit to be followed, a plurality of capacitor circuits that sample and hold each of the comparison reference potentials for comparing determination potentials supplied from each of the level determination signal sources, and the plurality of capacitor circuits that are held by the capacitor circuits. A chopper type comparing means comprising a multi-stage analog switch for sequentially switching and comparing each comparison reference potential with the judgment potential of each of the level judgment signal sources, and each of the level judgments based on each input digital potential data. D / A conversion means for charging the capacitor circuit to each comparison reference potential set in the signal source; Power supply control circuit, characterized in that it includes a timing control means for controlling the switching of the analog switch of the multiple stages based on the output state. 2. A capacitor circuit for an A / D conversion circuit, a capacitor circuit for high-precision feedback control, and a capacitor circuit for switching control for switching signals of a plurality of level-determined signal sources in a time-division manner. 2. The power supply control circuit according to claim 1, comprising one. 3. One of the plurality of capacitor circuits is used for switching control for switching a signal of a plurality of level-determined signal sources and a control signal of an A / D conversion circuit in a time-division manner, and the other one is used for each. 2. The power supply control circuit according to claim 1, wherein the power supply control circuit is used for independent high-precision feedback control. 4. The power supply control circuit according to claim 3, wherein the capacitor circuit used for high-precision feedback control has two or more comparisons with respect to one charge. 5. A control having a plurality of capacitor circuits used for high-precision feedback control and having no charging timing immediately before comparison, one of which uses the charging timing of normal comparison control, and the other uses one. 5. The power supply control circuit according to claim 4, wherein a comparison timing is used. 6. The power supply control circuit according to claim 2, wherein the switching control selects and changes one of a flag switching and an IC mask switching. 7. The power supply control circuit according to claim 5, wherein the comparison timing is used exclusively for said high-accuracy feedback control. 8. The timing of inserting the high-precision feedback control using a plurality of capacitors should be the time of charging a circuit that requires the most high-precision control among the feedback control circuits using one capacitor in a time-sharing manner. The power supply control circuit according to claim 4, wherein: 9. A plurality of capacitor circuits according to claim 1, a chopper type comparison means, a D / A conversion means, a timing control means, and a central control device for changing the timing of the timing control means. A power supply control circuit provided on a chip microprocessor.