JPH0447418A - Power source control circuit - Google Patents

Abstract

PURPOSE:To miniaturize the power source control circuits by small electric power by forming this circuit of plural capacitor circuits, a chopper type compar ing means, a D/A converting means, and a timing control means. CONSTITUTION:In order to compare the decided potentials supplied from each level decided signal sources 1, 4, 51 and 79, a multistage analog switch is switched by a timing control means 23, and simultaneously, each digital potential data corresponding to each level decided signal source is inputted to a D/A converting means 7. The means 7 charges a prescribed capacitor to each compar ison reference potential corresponding to each level decided signal source, based on potential data and sample-holds it. Subsequently, when a switching control signal of the analog switch is sent out by the means 23 at a prescribed timing, a chopper type comparing omeans compares a first decided potential and a first comparison reference potential, and also, outputs a result of comparison, while switching successively second, third and fourth potentials in the same way, and controls the power source, based thereon. In such a way, the A/D conversion and the feedback control can be executed with high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a comparison circuit that time-divisionally compares a plurality of potential levels to be determined, and particularly relates to a comparison circuit that compares a plurality of potential levels to be judged in a time-division manner, and particularly relates to a comparison circuit that compares a plurality of potential levels to be determined in a time-division manner, and particularly relates to a comparison circuit that compares a plurality of potential levels to be determined in a time-division manner. The present invention relates to a power supply control circuit that performs successive comparison and outputs a result signal. This particularly relates to the case where these circuits are configured on a semiconductor integrated circuit (IC).

[Conventional technology]

Conventionally, one capacitor for sampling and holding each comparison reference potential for comparing the judgment potentials supplied from each level judgment signal source was shared in a time-division manner.

FIG. 8 is a circuit configuration diagram of a power supply control circuit showing an example of this conventional example.

In this figure, 1 is an equivalent voltage source constituting the first level determination signal source, the - terminal is grounded, and the other end is connected to the output resistor 2 constituting the first level determination signal source. . The other end of the output resistor 2 is connected through a signal line 10 to one end of a capacitor 3 whose other end is grounded. Above 1
.about.3 constitute a first level determination signal source.

Reference numeral 4 designates an equivalent voltage source constituting a second level determination signal source, with one end connected to ground, and the other end connected to an output resistor 5 constituting a second level determination signal source. Output resistor 5
The other end is connected through a signal line 11 to one end of a capacitor 6 whose other end is grounded. The above 4 to 6 constitute a second level determination signal source.

7 is a D/A converter whose one end is grounded, and the data bus 24
When digital data sent from the timing generator 23 is set through the signal line 45, an analog signal corresponding to the digital data on a one-to-one basis is instantaneously output to the signal line 45.

The signal 1IA45 is connected to one end of a resistor 8, and the other end of this resistor 8 is connected to a capacitor 9 whose one end is grounded. Items 7 to 9 above originally constitute an actual D/A conversion circuit, and the resistor 8 and capacitor 9 are output impedances in which the impedance that originally exists as a distributed constant can be approximately expressed as a lumped constant. do. In addition, D
/A converter 7 converts the first level-determined signal sources 1 to 3 . It functions as a comparison reference power supply for comparing the determination potentials of the second level determination signal sources 4 to 6, and charges a capacitor circuit, which will be described later, to the comparison reference potential for each power supply.

The signal line 10 connects the drain terminal of an N-channel MOS transistor (hereinafter referred to as N-MO5) 14 and a P-channel type MOS transistor (hereinafter referred to as P-MOS).
The source terminal of the N-MOS 14 and the drain terminal of the P-MOS 15 are connected to the signal line 13.

On the other hand, the signal line 11 is connected to the train terminal of N-MOS 17 and the source terminal of P-MOS 18.
A source terminal of the OS 17 and a train terminal of the P-MOS 18 are connected to the signal line 13.

Similarly, the signal line 12 is connected to the drain terminal of the N-MOS 20 and the source terminal of the P-MOS 21.
The source terminal of S20 and the drain terminal of P-MOS21 are connected to signal line 13. The signal line 13 is grounded through a capacitor 46 and connected to the signal line 35 through a capacitor 47. Signal line 3
5 is the drain terminal of N-MOS31.36 and P-M
Connected to the source terminal of OS32.37. However, N-MOS31. P-MOS32 and N-MOS3
6. P-MOS37Lt-T-2'L and t'L form the switch portion of a pair of analog switches. N-M
The source terminal of OS31 and the drain terminal of 2MO532 are both connected to one end of resistor 33. Note that the other end of the resistor 33 is connected to a child terminal of a voltage source 34, and the negative terminal of the voltage source 34 is grounded. In addition, the source terminal of N-MOS36 and P-MOS37
The drain terminal of is connected to the signal line 39.

The signal line 39 is connected to the input terminal of the logic determiner 40,
If the human input signal potential of the signal M39 is lower than the voltage V7H of the voltage R34, an L level is outputted, and if it is higher than the voltage V7H, an H1 level is outputted. An output line (signal line) 42 of the logic determiner 40 is connected to a latch 43 and a data input terminal of a shift register 48. latch 4
The Q output terminal of the latch circuit consisting of 3 is connected to the output terminal 44 which outputs the result of this comparator.

Note that the timing generator 23 has a terminal L1 that sends a control signal to the D/A converter 7 through the data bus 24, and is an N-MOS 14 that constitutes a transfer gate. P-M
OS 15. Signal line 2 is connected to inverter 16 from terminal L2.
5, and sends a control signal through N-MOS17. P-MO
S18. A control signal is sent from the timing generator 23 to the transfer gate composed of the inverter 19 through the terminal L3 or the signal line 26.

N-MOS20. P-MOS21. Inverter 22
Terminal L4 is the signal line 2 to the transfer case consisting of
A control signal is sent out from the timing generator 23 through 7.

N-MOS31. P-MOS32. The terminal L5 is connected to the signal line 28 to the transfer gate consisting of the inverter 41.
A control signal is sent from the timing generator 23 through.

N-MOS36. P-MOS37. Invar';13
A control signal or a timing generator 23 sends a terminal L6 to the transfer gate 8 through a signal line 29.

In addition, the L# child of the latch 43 is connected to the signal line 3 from the terminal L7.
A control signal is sent from the timing generator 23 through 0. Further, a control signal is sent from the timing generator 23 to the clock input terminal of the shift register 48 through a signal line 49 from a terminal L8.

Note that the signal line 25 is connected to the gate of the N-MOS 14, and at the same time the input terminal Ill! of the inverter 16! 11. The output terminal of inverter 16 is P-MOS
It is connected to 15 gates. The signal line 26 is N-M
It is connected to the gate of the OS 17 and the input terminal of the inverter 19. The output terminal of inverter 19 is P-MOS
It is connected to 18 gates. Signal line 27 is N-M
The output terminal of the inverter 22 is connected to the gate of the OS 20 and the input terminal of the inverter 22.
Connected to the Kate. Signal line 28 is N-MOS3
1 and the input terminal of the inverter 41, and the output terminal of the inverter 41 is connected to the gate of the P-MOS 32. The signal line 29 is connected to the gate of the N-MOS 36 and the input terminal of the inverter 38, and the output terminal of the inverter 38 is connected to the gate of the P-MOS 37.

50 is an A/D conversion control circuit and its data input cover or 48
-1, respectively, to n Q output terminals of a one-stage shift register 48 through an n-tree data bus. Its control data output terminal is connected to the A/D conversion control signal input terminal of the timing generator 23 through a signal bus 50-1 of 50-1. Further, an output terminal for A/D conversion start control is connected to a reset terminal R of the shift register 48 through a signal line 50-2. Further, the result of A/D conversion is output to the output terminal 50-3.

Next, the operation will be explained.

D from the timing generator 23 serving as timing control means
Digital potential data (data DA
When TA 1 ) is input via the data bus 24,
The D/A converter 7 charges the capacitors 46 and 47 forming the capacitor circuit to a comparison reference potential corresponding to the determination potential set in the equal voltage source 1. Then, when a switching control signal is sent from the timing generator 23 to an analog switch (to be described later) at a predetermined timing, the chopper-type comparison means compares the judgment potential supplied from the equal voltage source 1 with the first comparison reference potential. is output.

When the first comparison process is completed, the next switching control signal is sent from the timing generator 23 to the multi-stage analog switch at a predetermined timing, and the second level determination signal is sent to the D/A converter 7. The next digital potential data (data DATA2) corresponding to the judgment potential set to the equal voltage source 4 serving as the signal sources 4 to 6 is transferred to the data bus 2.
4, the D/A converter 7 charges the capacitors 46 and 47 to a comparison reference potential with respect to the judgment potential set in the equal voltage source 4. Then, the timing generator 23 sends a switching control signal to each analog switch at a predetermined timing, and the chopper-type comparison means compares the judgment potential supplied from the equal voltage source 4 with the second comparison reference potential. Output.

Here, the operation shown in FIG. 8 will be explained in detail with reference to FIGS. 9 to 11.

9 and 10 are equivalent circuit rotations A and Example B of the circuit shown in FIG. 8 at predetermined timings, and the same parts as in FIG. 8 are given the same reference numerals.

FIG. 11 is a timing chart explaining the operation of FIG. 8.

In this figure, DATAI and DATA2 are data,
The signals are output from the terminal L1 of the timing generator 23 shown in FIG. 8 to the data bus 24, and supplied to the reference signal sources for comparison generated by the D/A converter 7, respectively. That is, data DATA 1 indicates the set voltage value of the comparison reference signal source corresponding to the first level-determined signal source composed of the above-mentioned 1 to 3, and DATA 2 indicates the set voltage value of the comparison reference signal source corresponding to the first level-determined signal source composed of the above-mentioned 4 to 6. The set voltage value of the reference signal source for comparison corresponding to the level determination signal source No. 2 is shown.

Now, data DATAI is transferred from terminal L1 onto data bus 24.
is output, and after time T1 has elapsed, terminal L3. When the output of the signal line 26.29 to L6 changes from "1" to "0", at time t3 when δ has passed from that time,
Terminal L4. The signal line 27.28 for L5 changes from "0" to "1".

The D/A converter 7 charges the capacitor 9 through the resistor 8 during a time T1 after DATA1 is output from the terminal L1 onto the data bus 24.

At this time, if the time constant indicated by the product of resistor 8 and capacitor 9 is set to 1 or 1/10 or less with respect to time T1, then at time t2, the voltage across capacitor 9 will be the data D
±0.1 of the voltage value indicated by the digital data of ATA 1
The error range is %. Terminal L4. When the logic value "1" is set on the signal line 27.28 corresponding to L5, the N-MOS 20.
Logic value "1" is added to 31, and P-MOS21.32
(7) Since the logic value "0" whose logic value "1" is inverted by the inverter 22, 41 is added to the gate, the N-MOS 20, 31. The P-MOS 21 and 32 are now in the on state, and the signal line 12 is connected to the signal line 13 and one end of the resistor 33 is connected to the signal line 35. At timing t3, terminal L2. L3. L6
Since the logic value rQJ is output to the signal J lines 25, 26.29 corresponding to
8.37 gates each have invar 316.19.
Since the logical value "1" which is the inverted signal of the logical value rQJ is added through 38, the values are 14 to 16, 17 to 19, respectively.
The analog switches 36 to 38 are turned off. Therefore, during the time T3 range τ from timing t3 to t4, a closed circuit shown in FIG. 9 is formed, and the capacitors 46 and 47 are charged. Now each resistor 8,5
By charging with a total resistance of 1,52.33, the voltage across both terminals of the capacitor 470 or the D/A voltage increases within a sufficiently short time T3.
From the output voltage VDA of the converter 7 to the voltage Vth of the voltage source 34
(Logic potential) minus voltage VT (VDA-Vt
It is assumed that the error is within about 0.5% from the value of h).

When timing t4 is reached, terminal L4. When the L5 signal changes from "1" to "0", N-MOS20, 31
and P-MOS21.32 are all turned off,
Capacitors 46, 47 are connected to signal lines 13, 39. and resistance 3
It is in a state where it is not connected to any of 3. After time δ has elapsed from timing t4, at timing t6,
The data on the data bus 24 corresponding to the terminal L1 is data D.
At the same time, a logic value "1" is output from ATAI to terminal L2 and terminal L6 instead of data DATA2.

For this reason, N-MOS14. P-MOS 15. An analog switch consisting of an inverter 16 and an N-MOS 36.
P-MOS37. The analog switch consisting of the inverter 38 is turned off, the signal 5ilo is connected to the signal line 13, and the signal line 35 is connected to the signal line 39. Therefore, the D/A converter 7 outputs an analog voltage corresponding to the data DATA2 (digital data) to the signal line 45 at that timing, and starts charging the capacitor 9 through the resistor 8. Also, capacitor 46.47
The capacitor circuit is constructed as shown in FIG.

That is, the output voltage of the equivalent voltage source 1 is pre-charging the capacitor 3 through the output resistor 2 and the signal line 1o, and its potential is set to vl.

The signal line 1o is connected to the N-MOS 14. P-MOS15
When the capacitor 46 is connected to the signal line 13 through the resistors 52 and 53, the capacitance of the capacitor 46 becomes 103 of the capacitance of the capacitor 3.
If the value is about 1/2, the capacitance of the capacitor 46 is charged almost instantaneously by the capacitance of the capacitor 3, and its potential can be approximately regarded as V, and as a result, the signal line 3
If the input impedance of the inverter circuit of the logic determiner 40 is approximately ω, the potential of the signal line 39 is the same as that of the signal line 35.

Therefore, the potential of the signal line 39 is V, -V. A+■th
When V,>VDA(7), the potential of the signal line 39 is greater than the potential Vth, and when V,<VDA, the potential of the signal line 39 is smaller than the potential vth.

By the way, the input voltage of the logic determiner 40 is the potential Vth.
If the voltage is higher than that, the circuit outputs an H level signal to its output terminal, and if it is lower than the potential vth, it outputs an L level signal to its output terminal, so when Vl>vDA, the circuit outputs an L level signal to its output terminal. is output.

Logically determine whether there is a difference in magnitude between potential V and potential VDA! ! It can be seen that H and L signals are output to the output terminal of 40.

When timing t6 is reached, the latch control input terminal of the latch 43 is connected to the terminal L7 of the timing generator 23.
An H level signal is input from the signal line 42, and the signal on the signal line 42 passes through the latch 43.

It is output to the output terminal 44. Then, at the moment when the signal at the terminal L7 changes from the H level to the L level in the timing mower, the signal @42 is latched by the latch 43, and the potential V
, and the voltage magnitude comparison result of the potential VDA is at timing t1.
At step 8, the signal is output to the output terminal 44 until an H level signal is manually applied to the terminal L7 again. When a minute time δt (5n to 100nsec) has elapsed from timing t7, terminal L2
and the signal at terminal L6 changes from H level to L level, and the potential V. The voltage comparison cycle of A ends.

In this way, one comparison between a set of level determination signal sources and the reference signal source for comparison is completed at timings t3 to t8. Then, the same operation as above occurs at timings t9 to t1.
4, a comparison between the voltage of the second level-determined signal source and the voltage of the reference signal source for comparison therewith, that is, the analog voltage representing the digital data of the data DATA2, is performed in the same timing sequence. However, this period and the period from timing t3 to t6 are different'! The operation of J1 is the operation of connecting the level-determined signal source. That is, timing 1.corresponds to timing ts to t6 when the terminal L2 is at H level in the period from timing t3 to t6. ~
At timing tll-t□4 in the period t14, the terminal L3 becomes H level, and the second
A voltage source is connected to the signal line 13. A second operation that is different during the period from timing t3 to t8 is a latch operation, and the shift register 48 is used as a latch circuit from timing t9 to t14. That is, when timing t1□ is reached, an H level signal is input from the terminal L8 of the timing generator 23 to the clock input terminal of the shift register 48, and the signal on the signal line 42 is taken into the first stage register of the shift register 48. Data bus 48-1 connected to the Q output terminal of the shift register 48
The data that was previously input to the shift register 48 is transferred one bit at a time to the highest digit bit (MS).
B) shifted to the side. Then, the data output to the Q output terminals Q0 to Q of the shift register 48 is the result of a comparison between the voltage of the potential v2 and the voltage of the potential voA, or
Until the H level signal is input to the clock input terminal again at timing t24 and taken into the shift register 48,
It continues to be output on the data bus 48-1 in the same state. Further, the third operation that occurs during the period from timing t3 to t8 is the data on the data bus 24, and the third operation occurs at timing t3.
9 to timing t14, data DATA2 is set from timing 1g to timing t11, and data DATAI is set from timing t to timing t14. Other basic comparison operations are the same between timings t3 to t8 and timings t9 to t14, respectively, at timing t3 or t9, timing t4 at timing tlo, timing t5 at timing 1++,
Timing t6 becomes timing t12, timing t7
corresponds to timing t13, and timings t and l correspond to timing t14. In addition, the same operation as that in the period from timing t3 to ta appears again at timing tlls to t2°, and the same operation as that for the period from timing t9 to t14 appears again at timing t21 to t2s, and the comparator Take turns comparing species.

Note that the data on the output terminal 44 of the equivalent voltage source 1 is now “0”.
It can be considered as any controlled circuit portion whose voltage increases when it is ``1'' and decreases when it is ``1''.

On the other hand, the equivalent voltage source 4 is a voltage source to be subjected to A/D conversion. For the comparison operation that operates as described above, the A/D conversion control circuit 50 uses the timing generator 23 . This is done by controlling the shift register 48. That is, the A/D conversion control circuit 50
When starting the conversion, a start signal is sent to the signal line 50-2 to reset the shift register 48, and at the same time an A/A signal is sent to the timing generator 23 through the pass line 50-1.
Sends D conversion control digital data. Timing generator 23 outputs this data on terminal Ll as DATA2. The A/D conversion control circuit 50 outputs the comparison result between the voltage source 4 to be A/D converted and the voltage value indicated by the A/D conversion control digital data to the Q of the shift register 48.
It is recognized based on the output data, and if the comparison result is greater than the A/D conversion control digital data value than the voltage value of the voltage source 4 to be A/D converted, DATA2 is If the magnitude relationship of the comparison results is the opposite, the A/D conversion control digital data to be set as DATA2 at the next comparison. , and the value of the A/D conversion control digital data approaches the voltage value of the voltage source 1-1 to be A/D converted.

This operation is performed when the number of stages n of the shift register 48 is one A/D.
Each time the A/D conversion is completed, the data of the A/D conversion result is output to the A/D conversion result output terminals 50-3, and at the same time the data of the next A/D conversion is output to the signal line 50-2. A D conversion start signal is output and the shift register 4
8 is reset.

(Problems to be Solved by the Invention) The prior art had only one sample-hold capacitor, and had the following drawbacks.

(1) Even if the timing is devised to increase speed, the number of control targets increases as the number of control targets increases due to time-division control, and the D/A converter samples and holds the comparison reference potential for each control target. As a result, the time required to charge the capacitor is reduced, making it impossible to perform control that requires accuracy above a certain level.

(2) Even if you try to perform high-precision control at a specific timing and increase the time to charge the sample-and-hold capacitor using the comparison reference power supply in that time division, the amount of time required for other controls will be increased by that amount. As a result of having to shorten the charging time of the sample-and-hold capacitor by the comparison reference voltage source in the comparison, there is a drawback that the accuracy required for the control required in these comparisons cannot be obtained.

(3) In time-division control using one sample-and-hold capacitor, every time a comparison is made, all information from the sample-and-held charge during the previous comparison is erased, and the comparison standard is always It becomes necessary to start recharging the voltage from the comparison reference potential of another servo control circuit one time before, and the lowest digit bit (LSB) is used during A/D conversion.
When charging the voltage, as the number of control objects to be controlled in a time-sharing manner increases, the charging time for the sample-and-hold capacitor decreases, and the change in the comparison reference voltage caused by the change in the charging start voltage reduces the accuracy of A/D conversion. There were drawbacks to the decline.

(4) If the density of the number of comparisons is increased in order to improve the control accuracy of a particular feedback control circuit, this may lead to a decrease in the control accuracy of other feedback control circuits, or if the number of feedback control circuits exceeds a certain level, cannot be increased.

The present invention has been made in order to solve the problems of the conventional example as described above, and aims to provide a power supply control circuit capable of high controllability.

[Means to solve the problem]

Therefore, in the present invention, the judgment potentials of the plurality of level judgment signal sources are compared with respective comparison reference potentials corresponding to the judgment potentials, and the judgment potential of each of the level judgment signal sources is adjusted to each predetermined value. In a multi-stage power supply control circuit that follows a potential, a plurality of capacitor circuits sample and hold each of the comparison reference potentials for comparing the judgment potentials supplied from each of the level judgment signal sources; chopper-type comparing means comprising a multi-stage analog switch for sequentially switching and comparing each comparison reference potential and the judgment potential of each level judgment signal source; A D/D that charges the capacitor circuit to each comparison reference potential set to the signal source to be level judged.
A power supply control circuit characterized in that it comprises A conversion means and timing control means for controlling switching of the multi-stage analog switches based on the transmission state of each digital data.

The plurality of capacitor circuits include at least one of a capacitor circuit for an A/D conversion circuit, a capacitor circuit for high-precision feedback control, and a capacitor circuit for switching control that switches signals of a plurality of level determination signal sources in a time-sharing manner. It is characterized by containing.

Further, one of the plurality of capacitor circuits is used for switching control for time-divisionally switching the signals of the plurality of level judgment signal sources and the control signal of the A/D conversion circuit, and the other one is used for switching control for switching between the signals of the plurality of level judgment signal sources and the control signal of the A/D conversion circuit, and the other It is characterized by being used for accuracy feedback control.

Furthermore, the capacitor circuit used for high-precision feedback control is characterized in that the number of times of comparison is two or more for each number of times of charging.

In addition, when multiple capacitor circuits are used for high-precision feedback control and the control does not have charging timing immediately before comparison, one uses the charging timing of normal comparison control, and the other one uses the charging timing of normal comparison control. It is characterized by the use of timing.

The switching control is characterized in that one of flag switching and IC mask switching is selected and changed.

Further, the comparison timing is used exclusively for the high-precision feedback control.

In addition, the timing for inserting the high-precision feedback control using two capacitors is set at the time of charging the circuit that requires the most high-precision control among the feedback control circuits using one capacitor in time division. do.

A one-chip microprocessor is provided with a plurality of capacitor circuits, a chopper type comparison means, a D/A conversion means, a timing control means, and a central control device for changing the timing of the timing control means. It is an object of the present invention to achieve the above object by providing a power supply control circuit characterized by the following characteristics.

[Effect]

With the above configuration, the power supply control circuit of the present invention uses the timing control means to switch the multi-stage analog switches and at the same time to compare the judgment potential supplied from each level judgment signal source. Each digital potential data corresponding to the level determination signal source is input to the D/A conversion means. The D/A conversion means converts a predetermined capacitor in a capacitor circuit consisting of a plurality of capacitors to each comparison reference potential set corresponding to each level determination signal source based on each input digital potential data. After charging and sample-holding, when the timing-J control means sends out a switching control signal for the analog switch at a predetermined timing, the chopper-type comparison means
Comparing the judgment potential with the first comparison reference potential,
Furthermore, in the same manner as described above, the second, third, and fourth potentials are sequentially switched, the comparison result is output, and the power supply is controlled based on the comparison result.

In particular, since the power supply control circuit of the present invention includes a plurality of sample and hold capacitor circuits, an independent sample and hold capacitor circuit can be allocated exclusively to a feedback control circuit that requires high precision A/D conversion control. Highly accurate A/D conversion and feedback control are possible.

Note that the multiple capacitor circuit for sample and hold is
The capacitor circuit for the A/D conversion circuit is used for sampling and holding a comparison reference potential for high-precision control, and the rest is used for controlling a plurality of feedback control circuits in a time-sharing manner.

Also, among the multiple capacitor circuits, one uses A/D conversion and control of multiple feedback control circuits in a time-sharing manner.
The other one is used for sampling and holding comparison reference potentials exclusively for control circuits that require high-precision control.

Furthermore, in the control of the capacitor circuit applied to high-precision feedback control, the number of comparisons is set at a ratio of two or more times to the number of charging times of one.

In addition, in comparison control that does not have charging timing immediately before comparison, one of the capacitor circuits applied to high-precision feedback control is normally used at the charging timing of comparison control, and the other is used at the comparison timing. .

Furthermore, circuit switching control can be changed by switching flags or IC masks.

Furthermore, the comparison timing for capacitor control is such that no comparison or charging operation of other control circuits is performed during that time, and is used exclusively for high-precision feedback control.

Furthermore, the timing at which a plurality of capacitor control timing circuits are inserted is used at the charging timing of the circuit that requires the most highly accurate control among the feedback control circuits that use one capacitor in time division.

The plurality of capacitor circuits, the chopper-type comparison means, the D/A conversion means, the timing control means, and the central control device 5 of the power supply control circuit according to the present invention are formed by a one-chip microprocessor, and a small It can be made smaller using electricity.

〔Example〕

The present invention will be explained below based on examples.

(First Embodiment) FIG. 1 is a circuit diagram of a power supply control circuit according to a first embodiment of the present invention, FIG. 2 is an explanatory diagram of some analog switch circuit symbols same as above, and FIG. FIG. 4 is a circuit diagram of the conventional example expanded to four equivalent voltage sources, and FIG. 5 is a drive time chart of FIG. 4 for the first embodiment.

Note that the same (equivalent) components as in the conventional example shown in FIG. 8, FIG. 9, FIG. 10, and FIG. 11 are represented by the same reference numerals, and redundant explanation will be omitted.

In FIG. 1, reference numeral 51 denotes an equivalent voltage source constituting the third level determination signal source;
The output resistor 52 is connected to an output resistor 52 that constitutes a signal source for level determination. The other end of the output resistor 52 is connected through a signal line 65 to one end of a capacitor 53 whose other end is grounded. The above 51 to 53 constitute a third level determination signal source.

Reference numeral 79 denotes an equivalent voltage source constituting a fourth level determination signal source, with one end connected to ground, and the other end connected to an output resistor 78 constituting a fourth level determination signal source. The other end of the output resistor 78 is connected to one end of a capacitor 80 which is connected to the signal line 77 and whose other end is grounded. 77-80 above
A fourth level determination signal source is configured.

The D/A converter 7 receives the first level determination signal sources 1 to 3 .
Second level determination signal sources 4 to 6° function as comparison reference power supplies for comparing the determination potentials of the third level determination signal sources 51 to 53, and charge capacitors (to be described later) up to comparison reference potentials for each power supply. Charge.

Reference numerals 54, 55, 60 to 64, and 71.75 are analog switches, and in the conventional example, the switch portion is composed of an N-MOS, a P-MOS, and an inverter, and is shown by a symbol because it is only 1wR.

By the way, element 2 constituting the analog switch in Figure 8
0, 21.22 are replaced with analog switches 60&: of FIG. 1, and elements 31.32.41 of FIG.
Similarly, elements 36 and 3 are added to the analog switch 61 in the figure.
7.38 is the analog switch 62, elements 14, 15 .
16 is the analog switch 63, elements 17, 18, 19
are respectively replaced with analog switches 64, forming a multi-stage analog switch. An example of terminal connection is shown in Figure 2.

A capacitor circuit composed of conventional capacitors 46 and 47 shown in FIG.
It is assumed that the capacitance of the capacitor 47 can be omitted compared to the capacitance of the capacitor 47, and only the capacitor 47 is considered. Note that the capacitors 56 and 73 shown in FIG. 1 have the same function as the capacitor 47.

The control gates of transfer gates 54.55 and 75.71 have a fidget signal 1170°68.76.7
2 to the terminals LIO, Lll of the timing generator 23
, L13. Connected to L14. 58.82 is the second
．． This is a latch circuit for latching the comparison result for the third control circuit, and its Q output terminal is the output terminal 59.8.
Connected to 1. In addition, the data input terminal is connected to the signal line 42, and the latch signal input terminal is connected to the signal line 42.
The latch 58 is connected to the signal terminal L9 of the timing generator 23 via a signal M57, and the latch 82 is connected to the signal terminal L12 of the timing generator $23 via a signal line 83.

Next, the operation will be explained.

Regarding the timing, consider the case where the conventional example using one capacitor is extended to control four equivalent voltage sources (one of which is an equivalent voltage source as an A/D conversion target), and compare it with that. Since it will be easier to understand, that case will be explained first.

FIG. 4 shows a circuit diagram of a conventional example expanded to include four equivalent voltage sources for purposes of explanation. To consider this circuit as the circuit shown in Fig. 1, short-circuit the signal lines 66 and 74 and the signal line 13,
Analog switch 55° capacitor 56. Analog switch 71. The capacitor 73 may be deleted, and the timing will be explained first with reference to FIG. 1J5. Terminal L
3rd on top. Digital value DATA3゜DATA corresponding to the voltage of the comparison reference signal source with respect to the fourth equal voltage source
4 is the first. Digital values DATAI and DATA2 corresponding to the voltage of the comparison reference signal source with respect to the second equal voltage source
DATA1, DATA2. DATA3. D
It is assumed that the signals are sequentially outputted in the order of ATA4 at time intervals of T4.

Voltage of level judgment signal sources 1 to 3 and digital data D
From t3 onwards, a comparison is made with the analog voltage indicated by ATAI.
The signal switching timing during the period t8 and the period t9 to t14, in which the voltages of the level determination signal sources 4 to 6 and the analog voltage indicated by the digital data DATA2 are compared, is between tl l""t14 shown in FIG. 11. terminal L
This is completely the same as the timing chart of the conventional example except for the data above. Operations similar to these are performed at timing t1-.
~t2°, a comparison between the voltage of the third level determination signal source 51.53 and the voltage of the reference signal source for comparison thereto, that is, the analog voltage indicated by the digital data of data DATA3, is performed in the same timing sequence. .

However, the first operation that differs between this period and the period from timing t3 to t8 is the connection operation of the level-determined signal source. That is, during the period from timing t3 to t8, the terminal L
Timing t1 in the period from timing t's to t20 corresponding to timings 5 to 78 when 2 is at H level.
From 7 to t2°, the terminal LIO becomes H level, and from 51 to 5
A third voltage source consisting of 3 is connected to the signal line 13. The second operation different from the period from timing t3 to t8 is a latch operation, and the latch 58 is used from timing t15 to t20. That is, timing t1
6, an H level signal is input from the terminal L9 of the timing generator 23 to the latch control input terminal of the latch 58, and the signal on the signal line 42 passes through the latch 58 as it is and is output to the output terminal 59. , timing t19
At the moment when the signal at the terminal L9 changes from H level to L level, the signal on the signal line 42 is latched by the latch 58, and the result of the comparison between the potential v2 and the voltage at the potential ■DA is transferred to L1 again as digital data. DATA3 is set and terminal L
until the H level signal is input to the output terminal 59 again.
continues to be output.

Also, the period from timing t3 to t8 and the timing t
The third operation in which the period from 9 to t14 is different from the period from timing t15 to t20 is the data on the data bus 24, that is, the data output to the terminal L1 of the timing generator 23, from timing t9 to timing t20. t14
Between, data DATA2 is set from timing t9 to timing tl+, and data DATA2 is set from timing t1 to timing t1+.
Data DATA3 is set from 1 to timing t14.

Between timing t15 and timing t20, data is DATA from timing t15 to timing t17.
3 is set, and DATA4 is set from timing t17 to timing t20.

Voltage of level judgment signal sources 1 to 3 and digital data D
From t3 to t, the analog voltage indicated by ATAI is compared.
The same operation as the signal switching in the period 8 is performed at the fourth level determination signal source 7 at timings t21 to t2g.
A comparison between the voltages 8 to 80 and the voltage of the reference signal line for comparison thereto, that is, the analog voltage indicated by the digital data of data DATA4, is performed in the same timing sequence. However, this period and the timing t3 to t
The first operation that differs from the period No. 8 is the operation of connecting the level-determined signal source. That is, in the period from timing t3 to 70, the terminal L2 is at H level, and at timings t23 to t28 in the period from timing t21 to t2g, which corresponds to timings 5 to 70, the terminal L13 is at H level, and the terminal L13 is made up of 78 to 80. The fourth voltage source connected to the signal line 13
connected to. The second operation that is different from the period from timing t3 to t♂ is a latch operation, and the second operation is a latch operation, which is performed at timing t2.
1 to t2g, the latch 82 is used. That is, when the timing tea is reached, the signal from the terminal L12 of the timing generator 23 to the latch control input terminal of the latch 82 is
level signal is input, the signal on the signal line 42 passes through the latch 82 and is output to the output terminal 81, and at the moment when the signal on the terminal L12 changes from H level to L level at timing t2s, the signal on the signal line 42 passes through the latch 82 and is output to the output terminal 81. The signal of latch 82
The result of the comparison between the voltage of the potential V3 and the voltage of the potential VDA is transferred to the terminal Ll again as digital data DATA.
4 is set and the signal continues to be output to the output terminal 81 until an H level signal is input again to the terminal L12. Also, the period from timing t3 to t6 and the period from timing t9 to t14
The third operation in which the period t2+''t2G differs is the data on the data bus 24, that is, the data output on the terminal Ll of the timing generator 23, from timing t9 to timing t14. In between, from timing t9 to timing tl+, data D
ATA2 is set, and data DATA3 is set from timing tll to timing t14.

Further, between timing t21 and timing t211, data DATA4 is set from timing t21 to timing t23, and DATAI is set from timing t23 to timing t28.

Regarding other basic comparison operations, timing t9~
At t14, the comparison result is transferred to shift register 4 instead of latch.
8, except for the period of timing t, ~t8, timing t9-t14, and timing tI.
g"" is the same between t20 and timings t21 to t28, and timing t3 is the same as timing t9 and timing 15. At timing t2+, timing t4 is the timing. and timing t16
．． At t2°, timing t5 is at timing tl+ and timing t17+t23, timing t6 is at timing t12 and timing t16+t24, and timing t7 is at timing t13 and timing t1.
9+ At t25, timing t8 becomes timing t14
and timings t2° and t26. Also,
It is assumed that the same operation as in the period from timing t3 to t26 is repeated from timing t27 onwards.

Note that the equivalent voltage source 11, the equivalent voltage source 3, and the equivalent voltage source 4
The data on the output terminals 44, 59, and 81 are “0” respectively.
'', the voltage changes from decreasing to increasing, and when it is ``1'', it can be considered as a feedback voltage from an arbitrary controlled circuit portion that operates so as to change from increasing to decreasing. Further, the equivalent voltage source 2 is an equivalent voltage to be subjected to A/D conversion.

On the other hand, in this embodiment, in order to control the voltage of the signal source to be level judged, which requires high control precision, in contrast to the conventional example, a dedicated sample hole capacitor 56 and a dedicated A/D conversion capacitor are used. 73 is its feature.

FIG. 3 shows a timing chart of the operation.

To simplify the explanation, we will take as an example the case where there are four signal sources to be level determined, and compare it with the circuit when the conventional example shown in Fig. 4 is extended to the case of four equivalent voltage source control. Let's explain its operation.

The difference in operation between this embodiment and the conventional example is that in the conventional example, the second
The equivalent voltage source was considered to be the A/D target power supply, but here we consider the fourth equivalent voltage source as that source, and naturally the operation of the A/D conversion control circuit is changed to match the timing. Ru. Conventionally, this was achieved by making the transfer gate 60 conductive and charging the capacitor 47 with the D/A converter 7, to provide the voltage of the comparison reference signal source for the third equal voltage source 51, 53, but this embodiment Then, at the same timing, the analog switch 55 is made conductive instead of the analog switch 6o, and the D/A conversion l! This is achieved by charging the capacitor 56 with I7.

Similarly, in the conventional example, the voltage of the comparison reference signal source for the fourth equivalent voltage sources 78 to 80 is realized by turning on the transfer gate of the analog switch 60 and charging the capacitor 47 with the D/A converter 7. However, in this embodiment, analog switch 71 is made conductive instead of analog switch 60 at the same timing, and capacitor 73 is charged by D/A converter 7.

In terms of the time charts in Figures 5 and 3,
Conventionally, from timing t11 when digital data DATA3 is output on terminal L1 shown in FIG.
16, the terminal L4 is set to 1, the analog switch 60 is turned ON, and the D/A converter 7 charges the capacitor 47 at the timing t's~til+
Then, 1 is applied to the terminal Lll shown in FIG. 3, which is transmitted through the signal line 68 to the control gate of the analog switch 55, which turns it on (ON). Conversely, during that period, the terminal L4 remains 0 and the analog switch is turned on. The gate of the switch 60 remains OFF, and the D/A converter 7 charges the capacitor 56.

In addition, in the conventional example, during the time period t2□ from timing t17 when digital data of DATA4 is output on terminal Ll, 1 is applied to terminal L4, analog switch 60 is turned ON, and D/A conversion is performed. From timing t21 to t22 when the capacitor 47 is charged by the device 7,
1 is applied to the terminal L14, which is transmitted to the control gate of the analog switch 71 through the signal line 72, turning it on (ON), and during that period, the terminal L4 remains 0 and the gate of the analog switch 60 is turned OFF (OFF). )
The D/A converter 7 is configured to charge the capacitor 73.

For this reason, the capacitor 56 always has the third level determination signal source 51 corresponding to the digital data DATA3.
Since the capacitor 56 is charged to the potential of the comparison reference signal source used in 53 and is not switched to and charged to another comparison reference signal source, the capacitor 56 is always connected to the digital data DATA3.
is charged to the potential of the comparison reference signal source corresponding to . Therefore, if this method is used, compared to charging and discharging the same capacitor to different voltage levels during multiple time divisions,
This can be easily achieved for circuits that require high-precision control that is faithful to digital data.

Similarly, the capacitor 73 always contains digital data DA.
TA4, that is, is charged to the comparison reference voltage for A/D conversion, and is not switched to another comparison reference signal source and charged. It is possible to control the reference voltage so that the change in the reference voltage is reduced as the bits require A/D conversion accuracy, and even if the charging time to the capacitor 73 is shortened, high-precision A/D conversion can be easily achieved. It becomes possible to realize the conversion.

Note that the capacitor 47 is connected to the third level determination signal sources 51 to 53 and the comparison reference voltage for A/D conversion, which do not require high precision control, that is, the first and second level targets may be controlled with low precision. It is used for comparison of the determination signal sources 1 to 3 and 4 to 6 in a time-division manner, and is controlled by being charged and discharged in a time-division manner.

(Second Embodiment) FIG. 6 is a circuit diagram of a power supply control circuit of a second embodiment, and FIG. 7 is a drive time chart of FIG. 6 of the second embodiment.

Components that are the same (equivalent) as those of the conventional example shown in FIGS. 8 to 11 and the first embodiment shown in FIGS. 1 to 5 are denoted by the same reference numerals, and redundant explanation will be omitted.

FIG. 6 is a circuit diagram showing a second embodiment, in which a latch 84 flag and a CPLI (central control unit) 85 for changing the timing of the timing generator 23 are added compared to the first embodiment. ing.

In response to an instruction from the CPU 85, the flag of the latch 84, that is, the Q output of the latch 84, is set to 1 or 0, and the timing generator 23 operates to change the timing generated according to the value.

When the Q output of the flag of the latch 84 becomes 1, the timing generated by the timing generator 23 changes from the basic cycle shown in FIG. 3 to the timing shown in FIG. 7. The basic cycle in Figure 3 is the repetition of the cycle from Ta+ to Ta2 in Figure 7, and the D/A conversion data is DATA.
2 becomes DATAI, and the timing is also changed accordingly.

The timing in Figure 7 is from Ta2 to the next basic cycle (
It is characterized in that there is a timing TADD between the timing Ta3 at which the repetition of the cycle from Ta to Ta2 starts. In TADD, from Ta2 to T
a, , is the comparison timing from tI7 to tI9 and the terminal L
They are the same except that the data on terminal L1 is DATA2, and Ta, □ to Ta3 are the same except for the timing from t23 to t26 and the data on terminal Ll is DATA2. Note that Ta2. and Ta22, δt is δ
tI TI: Considering T3, 1≦---cut size time and T,
100 Think.

The timing from Ta2 to Ta is originally the charging timing of DATA2, and the timing from Ta,2 to Ta3 is the comparison timing corresponding to the data of DATA3 in the first embodiment. In this example, the timing of charging the capacitor 47 in the first embodiment is replaced with the comparison.

In this way, the sample and hold capacitor 47,
The charging and discharging of the 56.73 had to be repeated in a time-sharing manner for each input signal, but the charging and discharging of the 56.73 is now possible by using an independent capacitor to compare each input signal for high precision control. By omitting the timing and inserting the comparison timing instead of the charging timing, the number of feedback control circuits that perform time-sharing comparison judgments is increased, and the time from the comparison judgment of each feedback control circuit to the next judgment is reduced. It is possible to suppress the decrease in accuracy due to the length.

In this example, latch 84 is set.

By thinking of it as a latch with a reset and selecting and fixing either set or reset when replacing the mask, it is possible to switch the timing of the required application. In addition, by setting the control circuit data and comparison timing to DATA2 and its comparison timing, which have a large change in comparison level each time a comparison is made, it is possible to take three times as much data setting time for the D/A converter as usual. This method is particularly effective when the basic timing of time-sharing operations is short compared to the settling time of D/A conversion.

Further, if the power supply control circuit described in the above embodiment is formed in a CMO3 structure on a one-chip microprocessor, a power supply control device that is small and consumes less power can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, a single comparator can easily perform a plurality of feedback controls and A/D conversions with high precision. Especially l! 1Jtj4
Even if the number of feedback control circuits required increases, the A/D
An independent sample-and-hold capacitor circuit can be assigned exclusively to a feedback control circuit that requires conversion and high-precision control, making it easy to achieve high-precision A/D conversion and feedback control.

Note that preparing a sample-hold capacitor circuit dedicated to A/D conversion has the advantage that higher A/D conversion speed and accuracy can be obtained than in the past.

In addition, among the sample-and-hold capacitor circuits, one capacitor uses A/D conversion and multiple feedback controls in a time-sharing manner, and the other capacitor circuit is used as a comparison reference potential exclusively for control circuits that require independent high-precision control. By using the capacitor for sample and hold, the timing for charging can be omitted by using an independent capacitor circuit for high-precision control.

Furthermore, by inserting the comparison timing instead of the charging timing, it is possible to suppress the decrease in accuracy due to the lengthening of the m interval from the comparison judgment of each feedback control circuit to the next judgment.

Note that high balance can be maintained by distributing the simple hold capacitor circuit applied to high-precision feedback control to charging timing and comparison timing.

In addition, if necessary, circuit switching control can be performed by switching flags or IC masks to dedicate the sample and hold capacitor circuit to high-precision control and essential feedback control, or to switch between A/D conversion and multiple feedback control circuits. By enabling time-division control of the system, the degree of freedom in system expansion will increase.

In addition, the comparison timing of multiple capacitor controls can be adjusted so that comparisons of other control circuits or charging operations do not occur in between, and the timing at which capacitor control timing is inserted is determined by a feedback control circuit that uses one capacitor in time division. By using it at the charging timing of the circuit that requires the most precise control, a considerable amount of charging time can be omitted during high-precision comparison, and high-precision control can be achieved using multiple control circuits and time-sharing control.

By configuring it together with a CPU on a single-chip IC, it is possible to easily realize inexpensive, high-performance multi-power supply control.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a power supply control circuit according to a first embodiment of the present invention, Fig. 2 is an explanatory diagram of an analog switch circuit symbol, and Fig. 3 is a drive time chart of Fig. 1 of the first embodiment. , FIG. 4 is a circuit diagram when the conventional example is expanded to four equivalent voltage sources for explanation, FIG. 5 is a drive time chart of FIG. 4, and FIG. 6 is a diagram of the power supply control circuit of the second embodiment. Circuit diagram, 7th
The diagrams are the drive time chart of FIG. 6 and the drive time chart of FIG. 8 of the second embodiment.
The figure is a circuit diagram of a conventional power supply control circuit, Figure 9 is an equivalent circuit rotation A of the comparator operation in Figure 8, Figure 10 is an equivalent circuit rotation B of the comparator operation in Figure 8, and Figure 11 is a circuit diagram of a conventional power supply control circuit. is the drive time chart of FIG. 8 of the conventional example. Note that in each figure, the same reference numerals indicate the same (equivalent) 411I components. 1.4, 51.79---Equivalent voltage source 7------
D/A converter 23--timing generator 40-one-wheel fill determiner 48-one shift register 43.5B, 82.84--latch 5O---A/D conversion control circuit 47.56.73-m - Capacitor circuit 85 - Central control unit 1 (CPU)

Claims (9)

[Claims] (1) The judgment potentials of the plurality of level judgment signal sources are compared with respective comparison reference potentials corresponding to the judgment potentials, and the judgment potential of each level judgment signal source is made to follow each predetermined potential. In a multi-stage power supply control circuit, a plurality of capacitor circuits sample and hold each of the comparison reference potentials for comparing judgment potentials supplied from each of the level judgment signal sources, and each of the comparisons held in the capacitor circuit. chopper-type comparing means comprising a multi-stage analog switch for sequentially switching and comparing the reference potential and the determination potential of each of the level determination signal sources; and each of the level determination signal sources based on each input digital potential data. and a timing control means for controlling the switching of the multi-stage analog switches based on the transmission state of each digital data. Features a power supply control circuit. (2) The plurality of capacitor circuits are at least one of a capacitor circuit for an A/D conversion circuit, a capacitor circuit for high-precision feedback control, and a capacitor circuit for switching control that switches signals of a plurality of level determination signal sources in a time-sharing manner. The power supply control circuit according to claim 1, characterized in that it includes: (3) One of the plurality of capacitor circuits is used for switching control to time-divisionally switch between the signals of the plurality of level judgment signal sources and the control signal of the A/D conversion circuit, and the other capacitor circuits are each used independently. The power supply control circuit according to claim 1, wherein the power supply control circuit is used for high precision feedback control. (4) The power supply control circuit according to claim 3, wherein the capacitor circuit used for high-precision feedback control performs comparison twice or more for every one charge. (5) When there are multiple capacitor circuits used for high-precision feedback control, and when the control does not have charging timing just before comparison, one uses the charging timing of normal comparison control, and the other one uses the charging timing for comparison. 5. The power supply control circuit according to claim 4, wherein a timing of . (6) The power supply control circuit according to claim 2, wherein the switching control selects and changes one of flag switching and IC mask switching. (7) The power supply control circuit according to claim 5, wherein the comparison timing is used exclusively for the high-precision feedback control. (8) The insertion timing of the high-precision feedback control using multiple capacitors is set at the time of charging the circuit that requires the most high-precision control among the feedback control circuits using one capacitor in a time-sharing manner. Claim 4
Power control circuit as described. (9) The plurality of capacitor circuits described in item 1, the chopper-type comparison means, the D/A conversion means, the timing control means, and the central control device for changing the timing of the timing control means are integrated into a single chip microprocessor. A power supply control circuit comprising a processor.