JPH04363917A - A/d converter - Google Patents

Abstract

PURPOSE:To shorten the long term for an A/D conversion time and to reduce the sampling of an erroneous input voltage by providing an initial setting means on an A/D converter. CONSTITUTION:The A/D converter is provided with a comparing means 3 comparing an analog input signal latched by a sample-and-hold means 2 with the input signal and generating an output signal, control means 4, 5 generating a digital signal based in the output signal of the comparing means 3, a D/A converting means 9 converting a digital signal generated by the control means 4, 5 into an analog signal and applying the analog signal to the comparator means 3 as the input signal and an initial setting means 7 initializing the input signal outputted from the D/A converting means 9 into a reference voltage.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is an analog-to-digital converter (hereinafter abbreviated as an A/D converter), in particular, a sample-and-hold circuit is used to hold an input voltage, and then the input voltage is compared with a predetermined voltage. The present invention relates to an A/D converter of a type that performs the following, such as a successive approximation type A/D converter.

0002

2. Description of the Related Art The configuration of a conventional successive approximation type A/D converter is shown in FIG. In the figure, A1 to An are analog input signals, for example those input from multiple input channels, 1 is a multiplexer, and channel selection signal C
The HS selects one analog input signal from among the analog input signals A1 to An. 2 is a sample-and-hold circuit (hereinafter abbreviated as S/H circuit), which selects one analog input signal from the multiplexer 1. One that samples the voltage at a point in time and holds that voltage, 3
is a comparison circuit, which converts the voltage AN1 held in the S/H circuit 2 into a digital-to-analog converter (hereinafter referred to as D).
4 is a control circuit that compares whether the analog output voltage AN2 from the A/A converter is large or small, and is held in the S/H circuit 2 based on the comparison result from the comparison circuit 3. Digital signal B1 corresponding to voltage AN1
〜Bm is generated, 5 is a successive approximation register,
Digital signal B1 output from control circuit 4
~ Bm is temporarily held, 6 is an output storage register that holds the final result of the contents of the successive approximation register 5 (digital signals B1 to Bm), and 9 is a D/A conversion circuit that sequentially Analog output voltage AN corresponding to digital signals B1 to Bm held in comparison register 5
2.

As a more detailed configuration of the successive approximation type A/D converter shown in FIG. 25, the configuration shown in FIG. 26 can be considered. In FIG. 26, the same parts as in FIG. 25 are given the same reference numerals.

The successive approximation type A/D converter shown in FIG. 26 has three input channels ch1 to ch3 and is configured to output 6-bit digital signals B1 to B6 in response to an analog input voltage. The D/A conversion circuit 9 includes a digital input section 14 that charges and discharges charges to one electrodes X1 to X6 of the capacitors C1 to C6 based on a digital control signal, and a digital input section 14 that charges and discharges charges to one electrode X1 to X6 of the capacitors C1 to C6, and capacitors C1 to C6, C6 (C1,
The capacitance portions 12 have capacitance values of C2, C3, C4, and C5 that are 25 times, 24 times, 23 times, 22 times, and 21 times the capacitance value of C6, respectively. The S/H 2 is configured by sharing the switch 15 and the capacitor section 12 of the D/A conversion circuit 9. The comparator 13 includes an inverter I
A one-stage comparison circuit COM composed of VI and a transistor N7 for shorting the input and output of the inverter IVI.
1 is connected to three stages (COM2
, COM3) are connected in series to obtain high amplification.

Next, the operation of the successive approximation type A/D converter shown in FIG. 26 will be explained step by step using the waveform diagram shown in FIG.

(1) Sampling of analog input voltage to be compared and holding of that input voltage.

[1] During the sampling period M1 (period in which the sampling pulse is at "H" level), the multiplexer 1 controls the switches SW1 to SW3 based on the channel selection signal CHS, and selects the input channels ch1 to
For example, select ch2 from ch3. The analog input signal input to the input channel ch2 is 5V during the sampling period M1 as shown in FIG. During the sampling period M1, switch S1
~S6 is closed, so the capacitor C1 of the capacitive part 12
A charge corresponding to the voltage of the analog input signal is stored in one of the electrodes X1 to X6 of C6. Figure 27(C) shows the electrode
1 to X6 are shown.

[2] After that, at any point in time (here,
At the end of the sampling period M1), the switches S1 to S
6 is opened, and charges corresponding to the voltage of the analog input signal are held in one of the electrodes X1 to X6. At this time, the digital input control unit 17 outputs digital control signals (“H” level for D1a to D6a,
However, since the transistors P1 to P6 and N1 to N6 of the digital input section 14 are all turned off, one electrode X1 to X6 is not electrically connected to the digital input section 14. separated into On the other hand, since the transistors N7 to N9 of the comparator 13 are turned on during the sampling period M1, the other electrodes Y1 to Y6 also store electric charges equivalent to the amount of electric charge of one of the electrodes X1 to X6. At this time, since the input terminal and the output terminal of the inverter IVI are short-circuited by the transistor N7, the logic threshold voltage of the inverter IVI is approximately equal to that of the inverter IVI (for example, the logic threshold voltage is 2.5V). Then, at an arbitrary time point, negative charges are sampled and held on the other electrodes Y1 to Y6 by an amount of charge equivalent to the amount of charge on one of the electrodes X1 to X6. (2) First comparison between the digital value of the successive approximation register and the analog input voltage. [3] When the successive approximation period m1 (period in which the sampling pulse φSMP is at “L” level) in FIG.
It enters the comparison operation state. The control circuit 4 sets only the most significant bit B1 to "1" (1/2 voltage of the minimum-maximum voltage of the analog signal output by this D/A conversion circuit 9).
Successive approximation register 5 receives digital signals B1 to B6 (“1
00000"). The successive approximation register 5 converts the digital signals B1 to B6 into the digital control signals D1a,
D2a to D6a, so that D1b is at “H” level.
D2b to D6b are applied to the digital input section 14 so that they are at "L" level. In the digital input section 14, based on the digital control signal, the transistors P1 to P6, N1
~N6, one electrode X of capacitors C1 to C6
A positive charge is stored only in X2 to X6, and the charge is discharged by grounding X2 to X6. As a result, a negative charge equivalent to the amount of charge stored in one electrode X1 is stored in the other electrode Y1, but at the time of sampling in [2] above, The total amount of charge stored in Y1 to Y6 is one of the electrodes X1 to X6.
Since it is larger than the amount of charge stored in the other electrode Y6
The voltage changes to become lower. The gate voltage of the inverter IVI of the comparator 13 becomes lower than the logic threshold value during the sampling period M1, and the transistor P10 is turned on to output the comparison result REFS of "1" to the control circuit 4.

[4] Second comparison operation.

When the comparison result REFS in [2] is "1", the control circuit 4 sets the second bit B2 from the most significant of the digital signal to "1" (the analog signal output from the D/A conversion circuit 9). The digital signals B1 to B6 (“110000”) are input to the successive approximation register unit 5 as 3/4 voltage (minimum-maximum voltage). On the other hand, when the comparison result REFS in [2] is "0", the most significant bit B1 of the digital signal is "0" and the second bit B2 is "1" (D/A
Digital signals B1 to B6 (“0
10000") is input to the successive approximation register section 5. The digital signals B1 to B6 correspond to the digital signals B1 to B6 from the successive approximation register section 5 to one of the electrodes X1 to X6 via the digital input section 14. By this, one electrode X1,
If a negative charge equivalent to the amount of charge stored in X2 is stored,
The total amount of charge stored in each of the other electrodes Y1 to Y6 changes so that the voltage of the other electrode becomes higher or lower depending on the relationship with the amount of charge stored in one of the electrodes X1 to X6. let The comparator 13 then outputs a comparison result REFS to the control circuit 4 based on the level relationship between the voltage of the other electrode and the logical threshold of the inverter IVI.

[5] Third to sixth comparison operations.

Hereinafter, similarly to the operations [3] and [4] above, based on the comparison result REFS of the comparator 13, 3 bits and 4 bits are
Repeated comparisons are made for bits, ..., up to 6 bits. When the six comparisons up to the least significant bit are completed, the control circuit 4 stores the digital signal at the end of the comparison in the output storage register 6 via the successive approximation register 5. The digital signal is used, for example, as data for a microcomputer.

[6] Then, in the next A/D conversion cycle, continuous A/D conversion is performed by repeating the operations [1] to [5] above.

[0014]

[Problems to be Solved by the Invention] Such a successive approximation type A/D converter is integrated into one chip together with, for example, a microprocessor, and performs processing such as temperature control and flow rate control.
It is sometimes used to convert analog signals from various sensors such as temperature sensors and flow rate sensors into digital signals. As shown in FIG. 26, the sensor 10 detects changes in temperature and flow rate from the outside and outputs the results as an analog signal, but this analog signal contains a small noise component in addition to the necessary signal. In order to remove the noise, a filter in which a capacitor CS and a resistor RS are connected in parallel is used in the sensor 10 itself or as an external device to the sensor 10 to remove the noise. In the illustrated example, the filter is connected to the internal circuit 11 of the sensor 10.

However, when using a sensor with relatively large noise components, the capacitance of the capacitor CS and the resistance RS
Both resistors are made large to eliminate noise. For example, a filter may be used in which the capacitance of the capacitor CS is 10 μF and the resistance value of the resistor RS is 10 kΩ.

When attempting to perform continuous A/D conversion of the analog signal from such a sensor 10 using a successive approximation type A/D converter, at a certain arbitrary A/D conversion,
That is, at the transition of the N+1st A/D conversion cycle, due to the large voltage difference between the voltage held in the S/H circuit at the Nth time and the voltage held at the N+1th time, the S/H circuit at the Nth time is
The charge held in the H circuit may not be quickly switched to the amount of charge corresponding to the analog input voltage value that should be held the N+1 time.

The problem will be explained below using FIG. 27.

Regarding the Nth A/D conversion cycle (sampling period M1, successive approximation period m1), FIG.
), the analog input voltage is, for example, this successive approximation type A.
The maximum value of the input signal of the /D converter is 5V, and if the charge corresponding to the 5V voltage is held in the capacitor 13 during the sampling period M1 (operation [2] described above), the result will be as shown in FIG.
As shown in (C), the other electrode Y1~ of the capacitors C1~C6
Equivalent charge is also held in Y6. The charge held is
During the successive approximation time m1, a digital signal corresponding to the analog input signal 5V is generated by the operations [3] to [5] described above. During the successive approximation time m1, at the end of the operation [5] (at the end of the sixth comparison operation), the capacitor C is
One of the electrodes X1 to X6 of the electrodes X1 to C6 holds a charge approximately equal to the voltage of 5V held by the capacitor section 12.

As shown in FIG. 27A, in the next N-th A/D conversion cycle (sampling period M2, successive approximation period m2), the analog input signal is converted into, for example, this successive approximation type A/D conversion cycle.
Assuming that the minimum value of the input signal to the D converter is 0V, the digital input section 14 is electrically isolated from the capacitors C1 to C6 during the sampling period M2, and the switches S1 to S6 are closed, so that One electrode X1
Although the charges of ~X6 try to discharge toward the sensor 10 side, the discharge is suppressed because the capacitance of the capacitor CS and the resistance of the resistor RS are large.

Therefore, if the sampling period M2 in FIG. 27(C) is short, the sampling period M2 ends before the input signal drops sufficiently to 0V, and an incorrect voltage that is higher than the input signal 0V by φV is held. It ends up. This means that the analog input signal becomes 0 at the Nth A/D conversion cycle.
The same is true when the analog input signal is 5V in the N+1th A/D conversion cycle, and in that case, the sampling period M2 ends before the voltage rises to 5V in the sampling period M2.

On the other hand, the sampling period M1,...,Mn
If φV is made long enough, φV will gradually be discharged through the capacitor CS resistor RS and approach approximately 0V over time. However, this requires a longer A/D conversion cycle, making it difficult to perform high-speed A/D conversion. becomes difficult to do.

Therefore, in the present invention, the A/D conversion caused by suppressing the discharge or charging of the charge held in the S/H circuit to the input terminal at the time of each A/D conversion switch is achieved.
An object of the present invention is to provide an A/D converter that reduces conversion time and erroneous input voltage sampling.

[0023]

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention, and the same parts as in FIG. 25 are given the same reference numerals, and the explanation thereof will be omitted.

In FIG. 1, an initial setting circuit 7 is provided in addition to the elements shown in FIG. 25, and this initial setting circuit 7 is connected to the S/H circuit 2. The initial setting circuit 7 sets the voltage by forcibly charging and discharging the charge held in the S/H circuit 2 to a reference voltage before the N-th A/D conversion.

[0025]

[Operation] Even if the analog input voltage is held in the S/H circuit 2 before the N-th A/D conversion, the initial setting circuit 7 forcibly and instantly converts the held analog input voltage into approximately the reference voltage. Perform initialization. Therefore, when performing continuous A/D conversion, the A
The analog input voltage held during /D conversion is the maximum allowable input voltage (or minimum input voltage) of the A/D converter,
Even if there is a large voltage difference such that the analog input voltage input the N+1st time is the minimum allowable input voltage (or maximum input voltage) of the A/D converter, the analog input voltage held the Nth time will be the default setting. Since the circuit 7 instantaneously changes the input voltage to approximately the reference voltage, it is only necessary to reach the minimum input voltage from the approximately reference voltage by the N+1th predetermined time. In other words, the voltage difference between the analog input voltage inputted the N+1st time and the approximate reference voltage is smaller than in the above case, so the transition from the voltage held at the Nth time to the analog input voltage inputted the N+1th time is Even if it is similarly suppressed, it can be made faster than before. Therefore, it is possible to shorten the A/D conversion cycle without holding an incorrect analog input voltage.

[0026] This makes it possible to operate the A/D converter at high speed, reduce erroneous sampling of analog signal voltages, and improve the performance of the A/D converter.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows a first embodiment of an A/D converter according to the present invention, and the same parts as those in FIG. 26 are denoted by the same reference numerals, and the explanation thereof will be omitted. In this embodiment, the present invention is applied to a successive approximation type A/D converter, and the initial setting circuit 7 is connected to the digital input section 14 via the switch 18.

The initial setting circuit 7 performs an A/D conversion cycle (
One of the capacitor electrodes X1 to X6 is initialized before the sampling period (sampling period and successive approximation period), that is, before the operation [1] as described in the prior art. This initialization temporarily sets one of the electrodes X1 to X6 to approximately the reference voltage. Note that this reference voltage is within the maximum and minimum values of the input analog input voltage, or within the A/D
This is a predetermined voltage within the input permissible voltage of the converter.

In the embodiment, specifically, the initial setting circuit 7 controls the transistors P1 to P6, N1 to N6 of the digital input section 14, which determine the potential state of each of the capacitor electrodes X1 to X6. Digital control signals D1a to D6a, D1b to D given to each gate electrode of
6b. On the other hand, the initial setting circuit 7 also initializes the other electrodes Y1 to Y6 in order to quickly move the charge of one of the electrodes X1 to X6 during the initialization. Specifically, at the time of initialization, the initial setting circuit 7 generates comparison unit control signals g1 to g3 and applies them to the gate electrodes of the transistors N7 to N9 of the comparison unit 13 to open them, and to open the other of the capacitors. The electrodes Y1 to Y6 are connected to the transistor N7,
Then, the CMOS transistor P1 of the inverter IVI
0 and N10 to the power supply lines VCC and GND. Note that since the CMOS transistors P10 and N10 are formed so that their mutual inductance gm is relatively small, the charges stored in the other electrodes Y1 to Y6 are quickly charged and discharged.

The switch 18 receives the digital control signal D output from the comparison register section 5 in the A/D conversion cycle.
1a to D6a, D1b to D6b to the digital input section 14
The successive approximation register section 5 and the digital input section 14 are connected so as to convey the following information. On the other hand, at the time of initialization performed between each A/D conversion operation, the initial setting circuit 7 and the digital It is connected to the input section 14.

Next, the operation of the A/D converter shown in FIG. 2 will be explained using FIG. 3. Components similar to those in FIG. 27 are given the same reference numerals.

Note that, similarly to FIG. 26, the A/D of this embodiment
The converter has three input channels ch1 to ch3,
6-bit digital signal B for analog input voltage
It is configured to output 1 to B6. Also, D/A
The converter 9 includes a digital input section 14 that supplies charge to one electrode of the capacitors C1 to C6 based on a digital control signal, and a digital input section 14 that supplies charge to one electrode of the capacitors C1 to C6, C6 (C1
, C2, C3, C4, and C5 are respectively 25, 24, 23, 22, and 21 times the capacitance of C6). Power supply voltage V
CC is 5V, and the other power supply voltage is connected and 0V. Further, it is assumed that the input voltage range of the analog input voltage input to this successive approximation type A/D converter is 0 to 5V.

(The operation of this embodiment will be explained step by step.) (1) The initialization setting circuit 7 initializes the charges held in the S/H circuit 2 to a reference voltage.

[1] The initialization period pulse DR shown in FIG. 3(C) is temporarily set to "H" level. The “H” level period R1 of this initialization pulse DR is an initialization period of the S/H circuit 2. In response to the rise of the “H” level of the initialization period pulse DR, the switch 18 switches the connection between the digital input section 14 and the successive approximation register section 5 to the connection between the digital input section 14 and the initial setting circuit 7 side. . As a result, digital control signals d1a to d6a and d1b to d6b output from the initial setting circuit 7 are input to the digital input section 14. For example, since the analog input voltage range is 0 to 5V, even when the input analog input voltage changes the most (transition from 0 to 5V, 5 to 0V), it is possible to change from any analog input voltage state to the reference voltage. The reference voltage is set to 1/2 of the analog input voltage range in order to ensure that the transitions are uniform and the same.
Assuming the voltage (here, 2.5V), d1a, d1b
is input to the transistors P1 and N1 at "L" level, otherwise d2a to d6a are set to "H" level and input to P2 to P6, respectively, and d2b to d6b are set to "H" level and input to N2 to N6, respectively.

Therefore, the transistor P1 is turned on and the transistor N1 is turned off, a power supply voltage of 5V is applied to one electrode X1, and a predetermined amount of charge is stored. The other electrodes X2 to X6 are all grounded to discharge the stored charges.

On the other hand, the transistors N7 to N7 of the comparator 13
Comparison section control signals g1~ are also applied to the gate electrodes G1~G3 of N9.
“H” level is applied to g3, and transistor N
7 to N9 are turned on. As a result, the other electrode Y1~
The charge held in Y6 is transferred to transistors N7 to N9.
and CMOS transistor P10 of inverter IVI,
It is discharged or charged via N10 so that the amount of charge becomes the same as the amount of charge stored only in one electrode X1.

[2] At the end of the initialization period, the switch 18 is switched to connect the digital input section 14 and the successive approximation register section 5. The successive approximation register unit 5 sends digital control signals D1a to D6a, D1 to the digital input unit 14 so that all transistors P1 to P6, N1 to N6 of the digital input unit 14 are turned off.
b, D6b are input. However, the transistors N7 to N9 of the comparator 13 are kept on until the next sampling period.

As a result, the electrodes X1 to X6 are in a kind of floating state during the period r1, and the initialization period consists of the period R1 and this period r1.

(2) Setting of A/D conversion operation.

The switch 18 is switched so that the successive approximation register section 5 and the digital input section 14 are connected.

(3) Sampling the analog input voltage to be compared and holding that input voltage.

[3] Sampling period M1 (
During the period in which the sampling pulse φSMP is at the "H" level in FIG. 3(B), the input channel ch2 is selected by the multiplexer 1 based on the channel selection signal CHS. An analog input voltage of 5V is input to the input channel ch2 as shown in Fig. 3(A), and the switch S for 6 bits is input.
Commonly given to S1 to S6.

[4] Then, the switches S1 to S6 are closed, and positive charges corresponding to the analog input voltage are stored in one electrodes X1 to X6 of the capacitors C1 to C6 of the capacitive section 12. On the other hand, in the other electrodes Y1 to Y6, the transistors N7 to N9 of the comparison section 13 are turned on, and negative charges of an amount equivalent to that of the one electrodes X1 to X6 are stored. At this point, the digital control signals (D1a~
“H” level for D6a, “L” for DF1b to D6b
Since the transistors P1 to P6 and N1 to N6 of the digital input section 14 are all turned off, the digital input section 14 is electrically isolated from one of the electrodes X1 to X6.

[5] After that, the sampling period M1
At an arbitrary point in time (in this case, at the end of the sampling period M1), the switches S1 to S6 are opened, so that positive charges corresponding to the analog input voltage immediately before the arbitrary point in time are held in one of the electrodes X1 to X6. The other electrode Y1 to Y6
, a negative charge of the same amount as that of one of the electrodes X1 to X6 appears.

(4) Successive comparison between the analog input voltage and the digital value of the successive approximation register 5.

[6] Successive approximation period m1 (FIG. 3(B)
During the period in which the sampling pulse φSMP is at the "L" level), the switching to the successive approximation period m1 occurs, and the transistors N7 to N9 of the comparator 13 are turned off, making comparison possible.

[7] The control circuit 4 sets only the most significant bit B1 to "1" (1/2 voltage of the minimum to maximum voltage of the analog signal output by this D/A conversion circuit 9, that is, 2
．． 5V), and digital signals B1 to B6 ("100000") are set in the successive approximation register 5. Based on the digital signals B1 to B6, the successive approximation register 5 sets the digital control signals D1a and D1b at "H" level and outputs D2a to D6a and D2b to D6b at "L" level to the digital input section 14. The digital input section 14 controls the transistors P1 to P6 and N1 to N6 based on the digital control signal. Since D1a and F1b are at the "H" level, a power supply voltage of 5V is applied from the power line to only one electrode X1 of the capacitors C1 to C6, and the other electrodes X2 to X6 are grounded to discharge the charge. By doing so, charges corresponding to the analog signal voltage of 2.5V output by the D/A conversion circuit 9 are stored.

[8] Negative charges equivalent to the amount of charge stored in one electrode X1 are stored in the other electrode Y1, but at the time of sampling, the other electrodes Y1 to Y6 of each of all capacitors C1 to C6 are Since the total amount of charges stored in the electrodes is larger than the amount of charges stored in one of the electrodes X1 to X6, the voltage of the other electrode Y6 changes to become lower. The gate voltage of the inverter IVI of the comparator 13 becomes lower than the logic threshold value during the sampling period M1, and the transistor P10 is turned on to output the comparison result REFS of "1" to the control circuit 4.

[0049]

[9] Second successive approximation operation.

When the comparison result REFS in [8] is "0", the control circuit 4 sets the second most significant bit B2 of the digital signal to "1" (the minimum value of the analog signal output by the D/A converter). - 3/4 voltage of the maximum voltage, i.e. 3.7
5V), digital signals B1 to B6 (“1100
00”) is input to the successive approximation register section 5. On the other hand, [
8] When the comparison result REFS is “1”, the most significant bit B1 of the digital signal is set to “0”, and the second bit B2 is set to “0”.
The digital signals B1 to B6 ("010000") are input to the successive approximation register section 5 as "1" (1/4 voltage of the minimum-maximum voltage of the analog signal output by the D/A converter, that is, 1.25 V). .

[10] The digital signals B1 to B6 are sent to one of the electrodes X1 to X6 via the digital input section 14.
A voltage corresponding to the digital signals B1 to B6 is applied to the terminals. As a result, one electrode X1 is connected to the other electrode Y1.
, X2, and the total amount of charge stored in each of the other electrodes Y1 to Y6 is the amount of charge stored in one of the electrodes X1 to X6. The voltage of the other electrode is changed to become higher or lower depending on the relationship between the two electrodes. The comparator 13 then outputs a comparison result REFS to the control circuit 4 based on the level relationship between the voltage of the other electrode and the logical threshold of the inverter IVI.

[11] Third to sixth successive approximation operations.

[0053] Hereinafter, similar to the operations [7] to [8] above,
Based on the comparison result REFS of the comparator 13, 3 bits,
Repeated comparisons are made up to 4 bits, ..., 6 bits. When the six comparisons up to the least significant bit are completed, the control circuit 4 stores the digital signal at the end of the comparison in the output storage register 6 via the successive approximation register 5. In addition,
The digital signal stored in the output storage register 6 is used, for example, as data for a microcomputer (not shown).

(5) The operations (1) to (4) above are performed in one A/D conversion cycle consisting of an initialization period and an A/D conversion cycle.
This is D conversion. After the operation (4), the initialization (1) is started again, and continuous A/D conversion is performed.

As described above, one A/D conversion is performed, but by providing an initialization operation such as (1) in one A/D conversion, consecutive A/D conversions can be performed. When the input analog input voltage changes the most (transition from 0 to 5 V, 5 to 0 V), it is possible to make the transition quickly. This will be explained using FIG.

During the sampling period M1, FIG.
), the analog input voltage is 5V, and at the end of the compiling period M1, the analog input voltage of 5V is held at one of the electrodes X1 to X6. Thereafter, in the successive approximation period m1, the held analog input voltage 5V is successively compared. During the sampling period M1, the analog input voltage applied to channel ch2 changes to the 0V side.

Conventionally, the next sampling period M2 is started at the end of the successive approximation period m1, and the charge corresponding to the analog input voltage held at the end of the successive approximation period m1 is inputted by the analog input voltage 0V. This is the discharge path and is suppressed on the sensor 10 side as shown in FIG. 27(C).
It is discharged as follows.

However, in this embodiment, an initialization period R1 is provided before the sampling period, and the charges held in one of the electrodes X1 to X6 are forcibly charged and discharged to the reference voltage (2.5V) and transferred. I'm letting you do it. Therefore, as shown in FIG. 3(D), the charges held in one of the electrodes X1 to X6 instantly transfer to the reference voltage, so that the next sampling period M2
Then, the analog input voltage only needs to shift by a potential difference of 2.5V from the reference voltage to 0V. At this time, during the sampling period M2, the analog input voltage is 0V and one electrode
This means that it takes only a short time for the potential difference (φV shown in FIG. 27C) with the voltage corresponding to the amount of charge held in 1 to X6 to reach approximately 0V. After that, in the successive approximation period m2, the analog input voltage applied to channel ch2 changes to the 2.5V side. During the initialization period R2, the initial setting circuit 7 selects one electrode X1.
~X6, the other electrodes Y1 to Y6 are initialized to a reference voltage of 2.5V. In the sampling period M3, Fig. 3 (D
), the voltage of one electrode X1 to X6 is 2.5V, which is the same as the reference voltage and the analog input voltage of channel ch2.

FIGS. 4 and 5 show embodiments of the initial setting circuit 7, respectively.

In FIG. 4, six flip-flops (
The 6-bit shift register consisting of F/F) RE1 to RE6 receives initial value data DATA clock CLK instructed by a microcomputer (not shown), for example. Initial value data DATA is any “0”
” or “1” digital signal, and the voltage range (0 to 5 V) of the input analog input voltage is 1/1.
2 voltage (2.5V), the shift register has “1”.
00000" is input, and 1/2 voltage (1.2
5V), “01000” is input to the shift register. Selectors SE1 to SE6 receive output values corresponding to F/FRE1 to RE6 of the shift register, and output digital control signals (d1a, d1b) to (d6).
a, d6b) pair signals are generated. For example, when the content of F/FRE1 of the shift register is "1", the digital control signals d1a and d1b are both output at "L" level, and when the content is "0", the digital control signal d1a
, d1b are both output at "H" level. This digital control signal is input to switch 18 in FIG. Note that the levels of the digital control signals generated by the selectors SE1 to SE6 can be changed as appropriate depending on the configuration of the digital input section 14.

In this way, when a digital control signal is generated using the shift register and selectors SE1 to SE6, when it is integrated into one chip with a microcomputer, it is possible to generate a digital control signal within the voltage range of the input voltage of the A/D converter. Even if the voltage range of the analog input voltage from the outside is arbitrary, the voltage range of the analog input voltage from the outside is 1/1
It can be set to two voltages. In other words, A/D
When a converter is built into one chip, if the voltage range of the analog input voltage input to the A/D converter is set to 0 to 5V and the reference voltage is set to 2.5V, it will not be connected externally. The voltage range of the analog voltage output from the sensor, etc.
~3V, the reference voltage cannot be set to 1.5V, which is half the voltage. However, by using a shift register and changing its contents according to instructions from a microcomputer, the reference voltage can be set arbitrarily.
It can provide versatility.

In the embodiment of FIG. 5, selectors SE1 to SE
6 itself to generate a fixed digital control signal to be output corresponding to the reference voltage. That is, although the reference voltage value is not variable, the digital control signal is generated within the selector by being connected to either the power supply voltage VCC or the ground potential GND. In this case, the circuit configuration can be simplified.

In the initial setting circuit 7 shown in FIG. 4, the circuit for providing a digital control signal to the digital input section 14 is provided with a shift register and a selector for each bit, but it is assumed that only any bit can be set. Good too. This is because the allowable input voltage range of the A/D converter itself is, for example, 0 to 5 V, and the analog voltage value range input to the A/D converter is, for example, 0 to 2.5 V. 1.25V is sufficient as the reference voltage for the initialization, so when configuring the initialization setting circuit as shown in Figure 4, only the lower 3 bits of shift registers RE3 to RE6 need to be provided, so the number of bits in the shift register can be reduced. Ru.

As described above, in this embodiment, an initialization period R1 is provided after the successive approximation, and the charges held in one of the electrodes X1 to X6 are forcibly charged and discharged to the reference voltage (2.5V). I am migrating it. Therefore, in the next sampling period M2, only the potential difference from the reference voltage to the analog input voltage needs to be shifted. The reference voltage may be any voltage, but by setting it to 1/2 the voltage of the input analog input voltage range, the reference voltage can be set to 1/2 of the input analog input voltage range.
With respect to changes in the analog input voltage or vice versa, the transition to the reference voltage is performed in the same way without bias in any case, so the initialization period R1 can be shortened.

Furthermore, in this embodiment, the initialization period (operation (1) above) is immediately before the sampling period;
It may be performed immediately after one A/D conversion (operation (4) above). However, in this case, the charges held in the S/H circuit cannot be initialized when performing the first A/D conversion.

Furthermore, this embodiment is applicable to, for example, Japanese Patent Publication No. 2-25
When applied to successive approximation type A/D conversion using the successive approximation type A/D conversion method proposed in Japanese Patent No. 295, setting of the initial setting circuit becomes easy. In other words, in the method described in the above publication, if a dedicated register is newly provided for preliminary comparison with the register SAR, the dedicated register is controlled so that it can be used as an initial setting circuit during the initialization period of this embodiment. Furthermore, if the upper two bits of the digital signal for preliminary comparison are "1", it is only necessary to control the second bit from the above to change "1" to "0".

Next, a second embodiment of the A/D converter according to the present invention will be described with reference to FIG. In the figure, the same parts as in FIG. 2 are denoted by the same reference numerals, and the explanation thereof will be omitted.

In FIG. 6, the A/D converter is shown on the right side of the dashed line, and this A/D converter is connected to the central processing unit (hereinafter referred to as CPU) via the data bus 52 and address bus 53.
) 50. For example, the A/D converter and CPU 50 are provided on a single LSI chip. The A/D converter has a decoder 51, and this decoder 5
1 has a read signal RD and a write signal W from the CPU 50.
R, an address signal, and a clock CLK are supplied. Based on these signals, the decoder 51 performs the
) The start clock φAD and read clock φR shown in
D and a write clock φWR are generated. Decoder 51
performs necessary decoding and operates a desired circuit portion of the A/D converter. Sampling pulse φSMP
is generated based on the start clock φAD. The output storage register 6 is connected to the data bus 52 via a buffer 56 so that the data stored in the output storage register 6 can be output via the data bus 52.

The sampling pulse φSMP and the initialization pulse DR may be generated from the CPU 50, the decoder 51, or a timing generator (not shown). The sampling pulse φSMP is shown in FIG. 11(B), and the initialization pulse DR is shown in FIG. 11(F).

Although the initial selection circuit 7 is composed of circuit sections 71 to 76, only the configuration of the circuit section 71 is shown in FIG. 6 for convenience. The circuit section 71 has three elements 70 connected as shown in the figure.
Consists of 0. Circuit portions 71 to 76 are capacitors C1 to
Initialization data that determines the potentials of electrodes X1 to X6 of C6 is supplied, but here this initialization data is supplied to the CPU 50.
is supplied via the data bus 52. switch 18
consists of circuit sections 181 to 186, but for convenience only the circuit configuration of circuit section 181 is illustrated. Circuit section 18
1 is two AND gates 180 connected as shown.
, two Noah gates 181 and one NAND gate 18
Consists of 2. In FIG. 6, each element 70 as shown in FIG.
0 is the four transistors Tr1 to T shown in FIG.
It has a circuit configuration consisting of r4.

FIG. 9 shows the control circuit 4 and successive approximation register 5 of FIG. 6 in more detail. The control circuit 4 consists of circuit parts 41 to 46, but for convenience, the circuit part 4
Only circuit configurations 1 and 46 are shown. Each circuit section of the control circuit 4 consists of two latch circuits 400 and one AND gate 401 connected as shown. Each latch circuit 400 basically consists of the element 70
It has the same three elements as 0. Every time one bit is compared, a high-level start clock φAD is latched by the latch circuit 400 of the circuit section 4i and sequentially shifted to the latch circuit 400 of the circuit section 4i+1 (where i=1 to 6). Therefore, six comparison results are output in response to six pulses of clock φ2.

On the other hand, the successive approximation register 5
56, but for convenience only the circuit configurations of the circuit sections 51 and 56 are shown. Each circuit section of the successive approximation register 5 is S
It consists of an R flip-flop 500. The digital control signals SAR1 to SAR6 are supplied to the circuit section 5 of the successive approximation register.
1 to 56 are output respectively. In this embodiment, the digital control signals SAR1 to SAR6 correspond to the digital control signals D1a to D6a of the second embodiment, respectively, and the digital control signals corresponding to the digital control signals D1b to D6b are not output.

[0073] The clocks φ1 and φ2 are the CPU 50,
It may be generated from the decoder 51 or a timing generator (not shown). Clocks φ1 and φ2 are shown in FIGS. 11(I) and 11(J), respectively.

FIG. 10 shows the main part of the comparing section 13 of FIG. 6 in more detail. The comparator 13 shown in FIG. 10 includes a decoder 60 and n flip-flops 61 connected as shown in the figure.
Consists of 1 to 61n. The start clock φAD is connected to the reset terminal R of each flip-flop 611 to 61n.
The system clock CLK is supplied to the first stage of n stages.
The signal is supplied to a flip-flop 611 provided in each stage. The decoder 60 includes flip-flops 611 to 61n
Decodes the output of and generates comparison unit control signals g1 to g3.
Output. These comparison unit control signals g1 to g3 are applied to the corresponding transistors N7 to N in the comparison unit 13 in FIG.
9 gate electrodes G1 to G3. Comparison unit control signals g1 to g3 are shown in FIGS. 11(C) to 11(E), respectively.

FIGS. 11(A), (B), (F) and (G)
correspond to FIGS. 3A, 3B, 3C, and 3D, respectively, and their explanation will be omitted.

Next, a third embodiment of the A/D converter according to the present invention will be described with reference to FIG. In the figure, the same parts as those in FIG. 6 are designated by the same reference numerals, and the explanation thereof will be omitted. The LSI chip shown in FIG. 12 has a data bus 52 and an address bus 5.
3, a connected A/D converter 70, C
PU50, interrupt processing unit 72, ROM73, RAM74,
Clock generator 75, timer/counter 76, serial input/output interface 77 and input/output port 7
Consists of 8. A clock generator 75 generates various clocks used within the LSI chip.

The A/D converter 70 includes a multiplexer 1, a switch 15, a digital input section 14, an initial setting circuit 7, a buffer 56, an output storage register 6, a successive approximation register 5, a control section 4, and a switch 15 connected as shown in the figure. It consists of a comparison section 13, a capacitance section 12, a latch circuit 71, and a decoder 51. The decoder 51 receives the read signal R from the CPU 50.
D. Decodes the write signal WR and address signal and generates various clocks based on these signals. The latch circuit 71 responds to the clock from the decoder 51 to
A channel selection signal from the PU 50 is latched, and the data latched by the latch circuit 71 is sent to the multiplexer 1 as a channel selection signal for selecting a desired channel.
supplied to

The initialization operation of the initial setting circuit 7 is performed for each A/D
It may be performed for each channel ch1 to chn before the conversion is performed. Further, the initialization operation may be performed immediately after the power supply VCC of the LSI chip is turned on.

The initialization operation can be performed in various ways, and each embodiment of the initialization operation will be described below.

According to the initialization operation shown in FIG.
50 selects channel chi from channels ch1 to chn by supplying channel selection data to latch circuit 71 via data bus 52 in step S1. The channel selection data is latched by the latch circuit 71 and supplied to the multiplexer 1 as a channel selection signal for selecting channel chi. In step S2, the CPU 50 reads the previous conversion data of the channel chi from the i-th area of the RAM 74 via the data bus 52. next,
The CPU 50 supplies the previous conversion data read in step S3 to the initial setting circuit 7 via the data bus 52. A/D conversion is started in step S4, and the CPU 50
reads the conversion result stored in the output storage register 6 via the buffer 56 and the data bus 52 in step S5. Further, the CPU 50 stores the conversion result in the i-th area of the RAM 74 via the data bus 52, and the process ends. The above processing is performed for any channel.

Therefore, according to the initialization operation shown in FIG. 13, the initial voltage of the power supplies X1 to X6 of the capacitors C1 to C6 is A.
/D converter is set to the average or center voltage of the voltage range of the analog input signal input to the D converter. The conversion result of the first A/D conversion is stored in the RAM 74, and this conversion result is
This is used as the initial voltage when performing the second A/D conversion. This initialization operation is effective in obtaining accurate conversion results, especially when the voltage change of the analog input signal is relatively small.

According to the initialization operation shown in FIG. 14, the average or center voltage of the voltage range of analog input signals for all channels ch1 to chn is stored in the ROM 73 in advance. Usually, the purpose of each channel is often determined by the user, and in such cases, the voltage range of the analog input signal input to each channel is known in advance. Therefore, it is possible to store in advance in the ROM 73 the average or center voltage of the voltage range of analog input signals for all channels ch to chn. In FIG. 14, steps that are the same as those in FIG. 13 are given the same reference numerals, and their explanations will be omitted.

In FIG. 14, step S6 is performed after step S1. The CPU 50 selects channel c in step S6.
The initial voltage hi is read from the i-th area of the ROM 73 via the data bus 52. Steps S3 and S4 are performed following step S6, and the process ends. The above processing is performed for any channel.

According to the initialization operation shown in FIG. 15, the average or center voltage of the voltage range of analog input signals for all channels ch1 to chn is stored in advance in the ROM 73, and the initialization operation is performed when the power supply VCC is turned on. It is carried out immediately after the In FIG. 15, steps that are the same as those in FIG. 13 are given the same reference numerals, and their explanations will be omitted.

In FIG. 15, the CPU 50 performs step S
At step 7, it is determined whether the power supply VCC is on. If the determination result in step S7 is YES, steps S6 and S
1 and S4 are performed in order. The initial voltage is the first A/D
It is supplied once to the initialization circuit 7 only at the beginning of the conversion, after which steps S1 and S4 are repeated. The above processing is performed for any channel.

The initialization operation shown in FIG. 15 is particularly effective when the analog input signal changes relatively quickly.

According to the initialization operation shown in FIG. 16, the previous conversion result is automatically supplied to the initial setting circuit 7 before A/D conversion starts. In FIG. 16, steps that are the same as those in FIG. 13 are given the same reference numerals, and their explanations will be omitted.

In FIG. 16, step S8 is performed after steps S1 and S4. At the start of A/D conversion, the data in the output storage register 6 is supplied to the initial setting circuit 7 without going through the data bus 52 and CPU 50. In other words, step S8 is performed at least during the initialization period.
The previous conversion result is automatically supplied to the initial setting circuit 7. The above processing is performed for any channel.

Next, a fourth embodiment of the A/D converter according to the present invention will be described with reference to FIG. FIG. 17 shows the main parts of the fourth embodiment, and the same parts as those in FIG. 6 are given the same reference numerals, and the description thereof will be omitted. According to this embodiment, the output storage register 6
The initial voltage can be automatically set for the desired channel based on data stored in the .

In FIG. 17, the initial setting circuit 7 is connected to the output storage register 6, and receives the channel selection signal SE.
L and the clock φsel are supplied to the initial setting circuit 7. For example, the clock φsel may be generated by the decoder 60 of the comparator 13 in FIG. FIG. 18 shows the main part of the comparison section 13 in this embodiment, and FIG. 19 shows the clock φs
The timing of el is shown together with comparison unit control signals g1 to g3 and start clock φAD.

According to this embodiment, the sampling period for the second and subsequent A/D conversions can be significantly reduced. Further, for the second and subsequent A/D conversions, the comparison of the predetermined upper bits may be omitted, and for the second and subsequent A/D conversions, only the lower bits may be compared. By repeating such operations, it becomes possible to perform more accurate comparisons. For example, in the first A/D conversion, the upper bits from the most significant bit to the 4th bit are converted to perform a rough conversion, and in the second A/D conversion, the 3rd to 10th bits are converted and the standard Conversion may be performed, and in the third A/D conversion, the 5th to 10th bits may be converted to perform fine conversion.

Next, a fifth embodiment of the A/D converter according to the present invention will be described with reference to FIG. In FIG. 20, the same parts as in FIG. 2 are denoted by the same reference numerals, and the explanation thereof will be omitted.

In this embodiment, an initial setting circuit 700 is provided between the multiplexer 1 and the switch 15. The initial setting circuit 700 includes a differential amplifier DIFF with a gain of about 1 and a transistor Tr1 connected as shown in the figure.
1 and Tr12. The transistor Tr11 is controlled by the initialization pulse DR, and the transistor Tr12 is controlled by the inverted pulse of the sampling pulse φSMP. The outputs of the transistors Tr11 and Tr12 are fed back to the inverting input terminal of the differential amplifier DIFF. The output of multiplexer 1 is supplied to the non-inverting input terminal of differential amplifier DIFF.

Next, the operation of this embodiment will be explained for channel ch1.
A case will be described in which the A/D conversion of the analog input signal received at channel ch2 ends and sampling of the analog input signal received at channel ch2 begins. In this case, the capacitors C1 to C6 of the capacitive section 12 hold the potential of the previous analog input signal received by the channel ch1.

First, the channel selection signal CHS2 for selecting the channel ch2 becomes active, and the channel selection signal CHS2 for selecting the channel ch2 becomes active.
The analog input signal received at 2 is output from multiplexer 1. Since the capacitance of the internal wiring is small, the potential of the analog input signal does not substantially change. Transistor Tr1
1 is turned on in response to the initialization pulse DR, and the charge corresponding to the analog input signal output from the multiplexer 1 is transferred to the capacitor C1 of the capacitor section 12 via the switch 15.
- held at C6. Since the gain of the differential amplifier DIFF is approximately 1, the feedback loop of the initial setting circuit 700 can compensate for the error between the output potential of the initial setting circuit 700 and the potentials at the electrodes X1 to X6 of the capacitors C1 to C6.

The potential at the electrodes X1 to X6 is determined by the initial setting circuit 7.
When the output potential becomes the same as that of 00, the transistor Tr11
turns off in response to the initialization pulse, and the transistor T
r12 is turned on in response to the inverted pulse of the sampling pulse φSMP. As a result, charges that accurately correspond to the potential of the analog input signal received at channel ch2 are held in capacitors C1 to C6 of capacitive section 12. Therefore,
The potentials at the electrodes X1 to X6 do not need to change significantly in response to the analog input signal received at channel ch2, and the analog input signal input to the A/D converter can be obtained from a circuit having high impedance. However, the sample and hold operation can be performed in a short time. That is, even if the analog input signal input to the A/D converter is obtained from a circuit with high impedance, there is no need to sample the same analog input signal multiple times.

Next, a sixth embodiment of the A/D converter according to the present invention will be described. In this embodiment, the latch circuit 7 in FIG.
By providing a shift register in addition to 1, it becomes possible to sequentially select channels. That is, in one mode, the desired channel selection signal from the CPU 50 is latched, and in the other mode, the shift register is latched to the channel selection signal from the CPU 50 (only one bit is "1" and the other bits are "0"). In response, channels are selected in sequence.

FIG. 21 shows the main part of the sixth embodiment. In this embodiment, a shift register 900 is provided in addition to the latch circuit 71 in FIG. 12, and the decoder 51 and control circuit 4 are also slightly modified compared to FIG. 12. The main parts of the latch circuit 71 and shift register 900 have a circuit configuration as shown in FIG. 21, and the clock φREP and its inverted clock are generated from the clock generator 901. Signal REPMODE is generated by selection signal generator 902. Signal FIN is generated from control circuit 4.

Latch circuit 7 connected to data bus 52
1 is the clock φWR3 generated from the decoder 51
latches channel selection data in response to As shown in FIG. 22, the clock φWR3 is generated based on the address used by the CPU 50 to operate the latch circuit 71. The circuit unit 510 that generates the start clock φAD may be a part of the decoder 51, or may be externally connected to the decoder 51 as shown in FIG. Latch circuit 7
The output of 1 is fed to multiplexer 1.

On the other hand, the output of the latch circuit 71 is clock φ
In response to the inverted clock of REP, the shift register 90
0. Clock φREP and its inverted clock indicate the end of A/D conversion in shift register mode. Data input from the CPU 50 to the latch circuit 71 is input to the latch section of the shift register 900 in accordance with these clocks φREP and its inverted clock. As a result, the value "0" is sequentially shifted through the inverter and the hatch circuit 71, and channels ch1 to
chn can be selected sequentially.

The signal REPMODE generated by the selection signal generator 902 is transmitted by the CPU 50 to the shift register 90.
The signal REPMODE, which determines whether to select a channel using the output of 0 (shift register mode) or directly select a channel using the data output from the CPU 50 (direct selection mode),
Based on the selection signal obtained via 2, the selection signal generator 902 generates the selection signal in response to the clock φWR2 from the decoder 51 of FIG.

As shown in FIG. 23, the signal FIN is applied to a circuit section 903 connected to the circuit section 46 of the control circuit 4.
generated from. In FIG. 23, the same parts as in FIG. 9 are denoted by the same reference numerals, and the explanation thereof will be omitted. This signal FIN is a start clock φ that is sequentially shifted through the latch circuit 400.
It is generated based on AD (="1") and has a constant pulse width. The clock φREP sets the output of the multi-input OR circuit of the clock generator 901 to "1" when one of the outputs of the latch circuit 71 is "1". Signal REPMO
When DE is “1” indicating shift register mode,
A clock generator 901 generates a signal F indicating the end of A/D conversion.
In response to IN, a clock φREP and its inverted clock are generated. On the other hand, when signal REPMODE is "0", direct selection mode is indicated.

Clock φREP is generated only in shift register mode. FIG. 24 shows the main signals used in this example. 24(A) is the start clock φAD, FIG. 24(B) is the clock φ1, FIG. 24(
C) shows the clock φ2, FIG. 24(D) shows the signal FIN, and FIG. 24(E) shows the clock φREP.

[0104] Although the present invention has been explained along with examples,
The present invention is not limited to these examples, and various modifications can be made in accordance with the gist of the present invention, and these are not excluded from the present invention.

[0105]

According to the present invention, the analog input signal and the digital input signal held by the sample-and-hold means
Since an initial setting means is provided to initialize the analog signal output from the analog conversion means to a reference voltage, even if the analog input signal changes from the highest value to the lowest value of the voltage range (or vice versa), Even if there is, A/D conversion can be performed at high speed, and erroneous sampling of analog signals can be reduced, making it possible to improve the performance of the A/D converter. Extremely useful.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a block diagram showing a first embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the first embodiment.

FIG. 4 is a block diagram showing an example of an initial setting circuit in the first example.

FIG. 5 is a block diagram showing another embodiment of the initial setting circuit in the first embodiment.

FIG. 6 is a block diagram showing a second embodiment of the present invention.

FIG. 7 is a diagram showing the elements in FIG. 6;

FIG. 8 is a circuit diagram of the element shown in FIG. 7.

FIG. 9 is a circuit diagram showing a control circuit and a successive approximation register in a second embodiment.

FIG. 10 is a circuit diagram showing main parts of a comparison section in a second embodiment.

FIG. 11 is a timing chart for explaining the operation of the second embodiment.

FIG. 12 is a block diagram showing a third embodiment of the present invention.

FIG. 13 is a flowchart showing an example of initialization processing according to the third example.

FIG. 14 is a flowchart showing an example of initialization processing according to the third example.

FIG. 15 is a flowchart showing an example of initialization processing according to the third example.

FIG. 16 is a flowchart showing an example of initialization processing in the third example.

FIG. 17 is a block diagram showing main parts of a fourth embodiment of the present invention.

FIG. 18 is a diagram showing main parts of a comparison section of a fourth embodiment.

FIG. 19 is a timing chart for explaining the operation of the fourth embodiment.

FIG. 20 is a block diagram showing main parts of a fifth embodiment of the present invention.

FIG. 21 is a block diagram showing main parts of a sixth embodiment of the present invention.

FIG. 22 is a diagram showing a decoder portion of a sixth embodiment.

FIG. 23 is a circuit diagram showing a control circuit and a successive approximation register in a sixth embodiment.

FIG. 24 is a timing chart for explaining the operation of the sixth embodiment.

FIG. 25 is a block diagram showing an example of a conventional A/D converter.

FIG. 26 is a block diagram showing a possible configuration of the A/D converter of FIG. 25;

27 is a timing chart for explaining the operation of the A/D converter in FIG. 26. FIG.

[Explanation of symbols]

1 Multiplexer 2 Sample and hold circuit 3 Comparison circuit 4 Control circuit 5 Successive approximation register 6 Output storage register 7 Initial setting circuit 9 A/D conversion circuit 10 Sensor 12 Capacity part 13 Comparison section 14 Digital input section 15, 18 switch

Claims (13)

[Claims] 1. Sample and hold means (2) for sampling and holding an analog input signal, and comparison means (3) for generating an output signal by comparing the analog input signal held by the sample and hold means with the input signal. ), control means (4, 5) for generating a digital signal based on the output signal of the comparison means, converting the digital signal generated by the control means into an analog signal and using the analog signal as the input signal. A digital-to-analog conversion means (9) supplied to the comparison means, an analog input signal held by the sample-and-hold means, and an initial stage for initializing the input signal output from the digital-to-analog conversion means to a reference voltage. An analog-to-digital converter comprising: setting means (7). 2. The analog-to-digital converter according to claim 1, wherein said reference voltage is selected within a voltage range of said analog input signal. 3. The analog-to-digital converter according to claim 2, wherein the reference voltage is selected to be approximately 1/2 of the maximum and minimum values of the voltage range. 4. The sample and hold means (2)
) samples and holds the analog input signal during a sampling period, and the initialization means (7) performs initialization during an initialization period before the sampling period. or 1 analog-to-digital converter. 5. The initial setting means (7) sets the reference voltage based on a digital signal generated by the control means (4, 5).
Any one of these analog-to-digital converters. 6. Any one of claims 1 to 4, wherein the initial setting means (7) sets the reference voltage in response to initialization data from a central processing unit (50). analog to digital converter. 7. Analog-to-digital converter according to claim 6, characterized in that the central processing unit (50) is provided on the same integrated circuit chip as the analog-to-digital converter. 8. The central processing unit (50) automatically reads initialization data from the memory (73, 74) at least during an initialization period in which the initialization means (7) initializes the initialization data. 8. An analog-to-digital converter according to claim 6 or 7, characterized in that the analog-to-digital converter is supplied to the means. 9. The central processing unit (50) stores the memory (73,
8. The analog-to-digital converter according to claim 7, wherein the initialization data is read from the initialization section 74) and supplied to the initialization means (7). 10. The sample and hold means (
2) consists of a sample means for sampling an analog input signal at a predetermined timing, and a hold means connected to the sample means and holding each sample voltage,
10. An analog-to-digital converter according to claim 1, wherein said sample means and said hold means perform sample and hold operations during a sampling period. 11. Further comprising input means (1) for receiving an analog input signal, during the sampling period the holding means is electrically connected to the input means via the initialization means (7), 11. The analog converter according to claim 10, characterized in that it is electrically isolated from the comparison means (3).
Digital converter. 12. During an initialization period in which the initial setting means (7) performs initialization, the holding means (7)
12. An analog-to-digital converter according to claim 11, characterized in that it is electrically isolated from the comparison means (3). 13. The comparing means (3) performs a comparison operation during a successive approximation period after the sampling period, and during the successive approximation period, the holding means
13. The analog-to-digital converter according to claim 11 or 12, wherein the analog-to-digital converter is electrically isolated from the converter and electrically connected to the comparing means.