JPH05259913A - A/d converter - Google Patents

Abstract

PURPOSE:To always secure the constant conversion characteristic and to shorten the sampling period by initializing the potential set right before the sampling of a sampling/holding circuit. CONSTITUTION:The level of the END signal outputted from a control part 1 is changed to '1' from '0', and the result of the A/D conversion is written into a storage register 38 by a control function. At the same time, the output level of an inverter 6 is changed to '0' from '1' and the output levels of the NAND circuits 7 and 9-16 are all set at '1'. Then the transfer gates 22, 25, 26, 28 and 30 are turned on by the inverting functions of the inverters 8 and 17-21. Meanwhile the gates 23, 24, 27, 29, 31 and 32 are turned off. Under such conditions, the total charge capacity Q of the capacitors 33-36 are initialized. Therefore the state is reversed in a sampling state where the subsequent A/D converting operations are continuously carried out. Thus the potential level V0 of a B line is changed to Vr/2 at a sampling start time point.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter.

[0002]

2. Description of the Related Art As an example of a conventional A / D converter, FIG. 5 shows a block diagram of a generally well-known capacitor array type successive approximation A / D converter. Here, for the sake of simplicity, a case of 4 bits will be described as an example.

In FIG. 5, the conventional A / D conversion device corresponds to an analog input terminal 105 and an analog reference power supply terminal 106, a control unit 1, a comparator 37, a storage register 38, a transfer register. The gates 66 to 76, an inverter 77, and capacitors 78 to 81 forming a capacitor array section are provided. Here, capacitors 78 (capacity C ₁ ), 79 (capacity C ₂ ), 80 (capacity C ₃ ) and 8
The relative capacity ratio of 1 (capacity C ₄ ) is set by the following equation.

C ₁ : C ₂ : C ₃ : C ₄ = 1: 1/2: 1/4: 1/4 Next, the block diagram of FIG. 5 and FIGS. 6 (a) and 6 (b),
(C), (d), (e), (f), (g), (h),
The operation of this conventional example will be described with reference to the timing diagrams of the operation signals shown in (i), (j) and (k).

First, in the sampling period T ₁ (see FIG. 6), the control signal S ₁ output from the control unit 1
The output levels of S ₃ , S ₅ , S ₇ and S ₉ become "1", the transfer gates 67, 69, 71, 73 and 75 are turned on, and the control output from the control unit 1 is performed. The output levels of the signals S ₂ , S ₄ , S ₆ and S _{8 and} the output level of the inverter 77 become “0”, the transfer gates 66, 68, 70, 72 and 74 are turned off, and the analog input terminals are turned off. The analog signal input from 105 is the transfer gate 7
The capacitors 78, 79, 80 and 81 are charged and discharged via 5, 67, 69, 71 and 73. Thereby, sampling of the analog value of the analog signal is performed.

In the next hold period T ₂ following the above sampling period, the output level of the control signals S ₁ , S ₃ , S ₅ , S ₇ and S ₉ output from the control section 1 becomes "0". Transfer gates 67, 69, 7
₁ , 73 and 75 are turned off, and the charges taken in during the sampling period T ₁ are transferred to the capacitors 78 and 7.
Holds at 9, 80 and 81. At this time, the potential V of the compare line input to the comparator 37 is
When the level of the analog voltage input to the analog input terminal 105 is V _i , it is expressed by the following equation.

V = -V_i  Next, the A / D conversion operation is started. First, the first conversion operation is performed.
In the state, in the control unit 1, the control signal S
₃Output level becomes "1", and transfer gate
67 is turned on. This allows the condenser 78
One terminal has analog reference power supply terminal 10
Reference voltage V input from 6_rApplied level
To be done. Capacitance C of capacitor 78₁Is the capacitor C₁
~ C_FourIs 1/2 of the total capacitance value of
The potential V of the compeller line input to 7 is calculated by the following equation.
Given.

V = -V _i + V _r / 2 Here, when V <0, the output level of the comparator 37 sent to the control unit 1 becomes "0", and the control signal S output from the control unit 1 The output level of ₃ is kept at "1", which causes the transfer gate 67
Remains on and the most significant bit is set to "1". When V> 0, the comparator 3
The output level of 7 becomes "1", the output level of the control signal S ₂ output from the control unit 1 is "1", the output level of the S3, becomes "0", transfer gate 66 is turned on, The transfer gate 67 is turned off and the most significant bit is set to "0". Here, in FIG. 6, the output level of S ₂ is “0”, S ₃
In the state where the output level of 1 is "1", "1" is set in the most significant bit.

Next, the second most significant bit is determined.
In the control section 1, the output level of the control signal S ₅ is set to "1" and the transfer gate 69 is turned on, whereby the potential V of the compare line input to the comparator 37 has already been set. Depending on the state of the most significant bit, the potential becomes one of the following two equations.

[0010] _{V = -V i + V r /} 2 + V r / 4 ( when the most significant bit is _{"1") V = -V i} + V r / 4 ( when the most significant bit is "0") the timing of Fig. 6 In the example shown in the figure, the most significant bit is set to "1", so the potential V of the compare line is expressed by the following equation.

V = −V _i + V _r + V _r / 4 Here, as in the case of determining the most significant bit,
When V <0 by the comparator 37 and the control unit 1, the second most significant bit is set to "1", and when V> 0, it is set to "0". Thereafter, when the least significant bit is determined by the same procedure, (11
11) to (0000). In the timing diagram of FIG. 6, finally (1
100).

Next, in the state of writing the conversion result A / D converted as described above into the register 38,
The A / D conversion result is written in the register 38 via the control unit 1. In this write state, the level of the END signal output from the control unit 1 and acting as a control signal for the storage register 38 becomes "1", and this EN
The A / D conversion result input from the control unit 1 to the register 38 is written into the storage register 38 via the D signal.
Thereafter, similarly, the A / D conversion is repeatedly executed by the operation procedure of sampling, holding, A / D conversion, and writing to the register.

[0013]

DISCLOSURE OF THE INVENTION The above-mentioned conventional A / D
The conversion device has a low analog input impedance at the time of sampling, and when performing A / D conversion continuously, the charge capacity that needs to be charged or discharged to the capacitor array section at the time of sampling is
It depends on the charge capacity sampled during the last conversion. For example, when the 4-bit A / D conversion operation is performed twice consecutively, the conversion value is (0000) → (1
111) and (1111) → (111
In the case of changing to 1), in the latter case, since the capacitor has to be fully charged from a state where it is not charged at all, an extra charge / discharge current flows through the analog input terminal 105. It becomes a state.
Therefore, in particular, when the analog input terminal 105 is connected with high impedance, the charging / discharging time for the capacitor is inversely proportional to the time constant of CR, and therefore the charging time for charging the capacitors 78 to 81 is extra. However, in order to perform A / D conversion within a limited conversion time, the sampling period is limited to within a predetermined time, and the resistance value that can be connected to the analog input terminal 105 is also limited. It

That is, when a resistor having a resistance value equal to or higher than a certain limit value is connected to the analog input terminal 105, the charging / discharging current for the capacitors 78 to 81 flows through the resistor. The voltage level of the analog input voltage actually applied to the analog input terminal 105 is shifted, and a conversion error is caused by this level down. This shifting potential level is determined by the capacitors 78-8.
It depends on the charging / discharging current for 1 but the current value of this charging / discharging current is calculated by the A / D conversion immediately before.
Up to 81 depending on the amount of charge sampled / held. Therefore, the A / D conversion result has a drawback that the same A / D conversion value cannot always be obtained because the shift amount of the potential changes depending on the previous conversion value even when the same level is input.

[0015]

The A / D converter of the present invention is an A / D converter having a sampling / holding circuit, wherein the sampling / holding circuit is provided at a timing immediately before sampling an input analog value. It is configured to include an initial value setting unit that sets the charge capacity held by the device to an arbitrary capacity value.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, this embodiment corresponds to the analog input terminal 101 and the analog reference power supply terminal 102 and controls the controller 1 and the inverters 2 to 2.
6, 8 and 17 to 21 and NAND circuits 7 and 9 to
16, transfer gates 22 to 32, capacitors 33 to 36 forming a capacitor array section, a comparator 37, and a storage register 38. Here, as in the case of the above-mentioned conventional example,
Capacitors 33 (capacity C ₁ ), 34 (capacity C ₂ ), 35
The relative capacity ratio of (capacity C ₃ ) and 36 (capacity C ₄ ) is
It is set as the following formula.

C ₁ : C ₂ : C ₃ : C ₄ = 1: 1/2: 1/4: 1/4 Further, FIGS. 2A, 2B, 2C, 2D, and 2E ),
(F), (g), (h), (i), (j) and (k)
FIG. 4 is a timing diagram showing operation signals in this embodiment.

Next, the block diagram of FIG. 1 and FIG.
(A), (b), (c), (d), (e), (f),
The operation of this embodiment will be described with reference to the timing charts (g), (h), (i), (j) and (k).

Control signals S _{1 to} S output from the control unit 1
Regarding the timing of ₉ and the END signal, the operation is the same as in the case of the above-mentioned conventional example. During the operations of sampling, holding and A / D conversion, the level of the END signal is "0", so that the output level of the inverter 6 becomes "1", and accordingly, the inverter 2
NA in the context of the inversion action of ~ 5, 8 and 21
Since the ND circuits 7 and 9 to 16 all operate as a function of an inverter, the gate control action on the transfer gates 24 to 32 is substantially controlled by the control signals S _{1 to} S ₉ output from the control unit 1. Will be done. Therefore, the series of operations up to the sampling, holding, and A / D conversion performed via the control signals S _{1 to} S ₉ are performed in the same manner as in the above-mentioned conventional example.

In the state where the A / D conversion is completed and the conversion result is written in the storage register 38, the control unit 1
The level of the output END signal is from "0" to "1"
Changes to A / via the control action by this END signal.
The D conversion result is written in the storage register 38, and
When the output level of the inverter 6 changes from "1" to "0", the output levels of the NAND circuits 7 and 9 to 16 all become "1", which causes the inverting action of the inverters 8 and 17 to 21. Through the transfer gates 22, 25, 26, 28 and 30 are all turned on, and the transfer gate 23,
All the gates of 24, 27, 29, 31 and 32 are turned off. In this case, the capacitor 33
The total charge capacity Q in ~ 36 is initialized as shown in the following equation.

Q = C₁・ V_r  Therefore, the sample in the next A / D conversion that is continuously performed
In the pulling state, the transfer
The gates of gates 22, 24, 26, 28 and 30 are
All turned off, and transfer gate 2
All gates of 3, 25, 27, 29, 31 and 32 are all
Is turned on and B at the start of sampling
Potential level V on the line_oIs given by
It

V _o = V _r · C ₁ / (C ₁ + C ₂ + C ₃ + C ₄ ) = V _r / 2 Therefore, the sampling of the analog voltage value applied to the analog input terminal 101 to the capacitors 33 to 36 is Regardless of the charge capacity being sampled / held at the time of the previous conversion, charging or discharging is always performed from the level of V _r / 2, so that analog input voltages of the same level are always processed. Constant A
The / D conversion characteristic is obtained. In addition, in the present embodiment, the maximum charge amount required to charge or discharge the capacitors 33 to 36 is in the range of 0 to V _r level in the maximum in the conventional case. , to a state interposed within the 0 to V _r / 2 or V _r / 2~V _r, it is reduced to 1/2 as a charge amount. Therefore, when the sampling period is the same as that of the conventional example, the allowable value with respect to the resistance value connected to the analog input terminal 101 can be doubled, and when the resistance value connected to the analog input terminal is the same. Can reduce the length of the sampling period to 1/2.

Next, a second embodiment of the present invention will be described.

FIG. 3 is a block diagram showing a second embodiment of the present invention. As shown in FIG. 3, the present embodiment corresponds to the analog input terminal 103 and the analog reference power supply terminal 104, the control unit 1, the inverter 6,
8, 21 and 39 and NAND circuits 7 and 40 to 6
3, transfer gates 22 to 32, capacitors 33 to 36 forming a capacitor array section, a comparator 37, a storage register 38, an initial value setting register 64, and a decoder 65. .. Here, as in the case of the first embodiment, the relative capacitance ratio of the capacitors 33 (capacitance C ₁ ), 34 (capacitance C ₂ ), 35 (capacitance C ₃ ) and 36 (capacitance C ₄ ) is calculated by the following equation. It is set like.

C ₁ : C ₂ : C ₃ : C ₄ = 1: 1/2: 1/4: 1/4 Further, FIGS. 4A, 4B, 4C, 4D, and 4E ),
(F), (g), (h), (i), (j), (k) and (l) are timing charts showing operation signals in the present embodiment.

Next, the block diagram of FIG. 3 and FIG.
(A), (b), (c), (d), (e), (f),
(G), (h), (i), (j), (k) and (l)
The operation of this embodiment will be described with reference to the timing chart of FIG.

Control signals S _{1 to} S output from the control unit 1
Regarding the timings of ₉ and END signal, they operate in the same manner as in the above-mentioned conventional example and the first embodiment. During the operations of sampling, holding, and A / D conversion, the level of the END signal is "0", and therefore the output level of the inverter 6 becomes "1". From 47, control signal S
The inverted level of the output level of 1 to S9 is output. Further, in this case, since the output level of the inverter 39 is "0", the output levels of the NAND circuits 48 to 55 are also "1" accordingly. Therefore, N
In the AND circuits 56 to 63, the NAND circuits 40 to
The output level of 47 is inverted and then output. As a result, the control signals S1 to S9 output from the control unit 1 are output.
The output level of is output as it is. Therefore,
The gate control operation for the transfer gates 24 to 31 connected to the capacitors 33 to 36 is similarly performed by the control signals S1 to S9 output from the control unit 1, as shown in the case of the above-mentioned conventional example. Further, since the gate control similar to that in the first embodiment is performed on the transfer gates 22 and 23, the series of operations from sampling to conversion are exactly the same as in the conventional example. The procedure is performed.

The difference between this embodiment and the first embodiment is that the conversion operation is completed, the conversion result is moved to the write state for the storage register 38, and the END signal output from the control unit 1 is changed. When the level changes from "0" to "1", the conversion result input from the control unit 1 to the storage register 38 is written, and the output level of the inverter 6 changes from "1" to "0". And, as a result, N
The output levels of the AND circuits 7 and 40 to 47 all become "1", and as a result, the output level of the inverter 8 changes from "1" to "0", and the output level of the inverter 39 changes from "0" to "1". By changing to
The output level of the ND circuits 48 to 55 is determined by the output of the decoder 65, that is, the set value output from the initial value setting register 64. As described above, by providing the initial value setting register 64, the capacitors 33 to 36 are
It is possible to selectively set the initial charge amount for the above, that is, the potentials of the capacitors 33 to 36 at the start of sampling by the initial value setting register 64. Note that in the example shown in FIG. 4, V _r · (5/8) is initialized. Table 1 shows the relationship between the output levels of the NANDs 56 to 63 and the initial value setting potential.

[0030]

[Table 1]

The settable initial potential is A / D
It can be arbitrarily set in the unit of the minimum width of conversion accuracy.

Therefore, the sampling of the analog input voltage at the analog input terminal 103 in the capacitors 33 to 36 is always the potential set in the initial value setting register 64, regardless of the charge capacity sampled / held at the previous conversion. Will be charged or discharged. For example, when an analog voltage obtained by multiplexing a plurality of analog inputs is input to the analog input terminal 103 and the analog inputs are continuously switched for each conversion, each analog input level change is When it is slow enough compared to the conversion cycle (the cycle from one variable for a specific analog input selected by multiplexing to the next selection by multiplexing and one conversion) Sets the value set in the initial value setting register 64 for each analog input so as to perform sampling from the conversion result level of the same analog input of the previous time, so that the capacitors 33 to 36 are charged and discharged. The charge amount can be set to the minimum necessary charge amount.
Therefore, when the sampling period is the same as the conventional one, the allowable value of the resistance that can be connected to the analog input terminal 103 can be increased, and the resistance value that is connected to the analog input terminal 103 is the same. In some cases, the sampling period can be further shortened.

In each of the first and second embodiments described above, the capacitor array type successive approximation A / D converter is described as an example, but the same effect can be obtained by using the sampling / hold circuit. The built-in A / D converter has means for performing sampling / holding via a capacitor and initializing the charge capacity of the capacitor in the sampling / holding unit when the input has a low impedance during the sampling period. It can also be realized by

[0034]

As described above, the present invention is applied to an A / D converter incorporating a sampling / holding circuit and initializes the potential just before sampling in the sampling / holding circuit to obtain a constant level. As the A / D conversion value corresponding to the analog input of, the constant conversion result can be obtained without being affected by the conversion value immediately before, and the potential immediately before sampling is always initialized to the optimum level. By converting
There is an effect that the current flowing at the time of sampling can be reduced, the external connection impedance can be increased, and the sampling period can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a timing diagram of operation signals in the first embodiment.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a timing diagram of operation signals in the second embodiment.

FIG. 5 is a block diagram showing a conventional example.

FIG. 6 is a timing chart of operation signals in a conventional example.

[Explanation of symbols]

 1 control part 2-6,8,17-21,39,77 inverter 7,9-16,40-63 NAND circuit 22-32,66-76 transfer gate 33-36,78-81 capacitor 37 comparator 38 memory Register 64 Initial value setting register 65 Decoder

Claims (1)

[Claims] 1. A having a sampling / holding circuit
The A / D conversion device is provided with an initial value setting means for setting the charge capacity held by the sampling / hold circuit to an arbitrary capacity value at a timing immediately before sampling the input analog value. / D converter.