JPH05206828A - Output buffer - Google Patents

Abstract

PURPOSE:To reduce the occurrence of noise in a power supply at the changing point of an output at the time of driving with a large amount of current and to prevent the influence of the noise which occurs in the shared power supply in a normal state at the time of high speed operation from affecting, in the output buffer of a semiconductor integrated circuit. CONSTITUTION:Auxiliary transistors P11 and N11 are provided in parallel with the transistors P10 and N10 at the final stage of the output buffer and their gate inputs are auxiliary control circuits G12 and G13. Since the auxiliary control circuits G12 and G13 control the continuity of the auxiliary transistors P11 and N11 corresponding to the level of the internal or external control signals M10 and M11 of the semiconductor integrated circuit at the change point of input signals and the switching between two kinds of control circuits detecting the voltage level of output terminals and controlling the continuity is made, the resistances between source drains of the auxiliary control circuits G12 and G13 can be changed and thus, the occurrence of the noise at the changing point of an output terminal O11 can be reduced and the influence of the noise can be prevented from affecting in the normal state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer, and more particularly to an output buffer of a semiconductor integrated circuit which operates with a large current and operates at a high speed.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing a conventional output buffer. In FIG. 5, the output buffer has an input signal I31.
Drive circuit G composed of an inverter 300 to which is applied
A P-channel MOS transistor P30 connected between a first power supply (hereinafter referred to as VDD) and an output terminal O31 via 31 and a second power supply (hereinafter referred to as GND) and the output terminal O31. N-channel MOS connected to
The transistor N30 and the transistor N30 are complementarily switched to drive the load via the signal transmission path.

MO which constitutes the final stage and the drive circuit G31
The geometrical size of the S transistor is determined so that the delay time until the level of the output terminal O31 to which the load is connected reaches a predetermined level and the current drivability satisfy the specifications according to the change of the input signal I31. ..

FIG. 6 is a circuit diagram showing a conventional output buffer used in a bidirectional input circuit such as a data bus. 6 is different from the output buffer of FIG. 5 in that it has an output control input signal E41, and this control input signal E41 causes the output terminal O41 to be either the P channel MOS transistor P40 or the N channel MOS transistor N40. Can be switched between a drive state in which the switch is in the conductive state and a high impedance state in which both are in the non-conductive state. The difference in the circuit configuration is that a NAND gate 407, a NOR gate 408, and an inverter 400 are used in the drive circuit G41, whereby the output terminal O41
The state switching of is realized.

[0005]

In the conventional output buffer of the semiconductor integrated circuit, the source of the output buffer of the semiconductor integrated circuit is adjusted by adjusting the geometrical dimensions of the MOS transistor constituting the output buffer in response to the demand for high speed operation and large current drive.・ Responding by reducing the resistance between drains.

Therefore, in the output buffer, the noise generated at the change point of the output signal gives a potential change to the common power source, and the problem of the output buffer sharing the power source having the potential change occurs. , MO in conduction
Since the source-drain resistance of the S-transistor is small, there is a problem that the semiconductor integrated circuit malfunctions due to the influence of the resistance easily generated at the output terminal.

An object of the present invention is to solve the above problems and to provide an output buffer which does not generate power supply noise and prevents the circuit from malfunctioning.

[0008]

According to the present invention, there is provided a first P-channel MOS transistor connected between a first power source and an output terminal, and a second P-channel MOS transistor connected between the second power source and the output terminal. A first N-channel MOS transistor connected to the first P-channel MOS transistor, and the first P-channel MOS transistor and the first N-channel MOS transistor are complementarily conductively controlled according to the level of an input signal, In an output buffer for driving a load connected to an output terminal, a second P-channel MOS transistor connected in parallel with the first P-channel MOS transistor between the first power supply and the output terminal. And the first N
A second N-channel MOS transistor connected in parallel with the channel MOS transistor between the second power supply and the output terminal, and further the second P-channel M
A control circuit connected to the gate of the OS transistor to be in a conductive state at a change point of the input signal according to an internal or external control signal, and to detect the voltage level of the output terminal to be in a non-conductive state. And by switching to a control circuit that is in a non-conducting state at the change point of the input signal, and that detects the voltage level of the output terminal and is in a conducting state,
A first auxiliary control unit for controlling conduction of the second P-channel MOS transistor when the output terminal changes and an internal or external control signal connected to the gate of the second N-channel MOS transistor. In response to the,
At a change point of the input signal, it becomes conductive, and at the change point of the input signal, it becomes non-conductive, and a control circuit that detects the voltage level of the output terminal and makes it non-conductive.
And a second auxiliary control for performing conduction control of the second N-channel MOS transistor when the output terminal changes by switching to a control circuit that detects the voltage level of the output terminal and makes it conductive. And a section are provided.

[0009]

1 is a circuit diagram of an output buffer according to a first embodiment of the present invention.

In FIG. 1, in the present embodiment, a P-channel MOS transistor P10 and an N-channel MO which form a first output circuit are provided between a power supply VDD and a ground GND.
The S transistor N10 is connected in series. An input signal I11 is applied to the gates of these MOS transistors P10 and N10 via a drive circuit G11 including an inverter 100, respectively.

On the other hand, a P-channel MOS transistor P11 constituting a second output circuit is connected in parallel with the P-channel MOS transistor P10 between the output terminal O11 and the power supply VDD, and the output terminal O11 and the ground GN are connected.
An N-channel MOS transistor N11 forming a second output circuit is connected in parallel with D to the N-channel MOS transistor N10.

This P channel MOS transistor P1
The control signal M11 inside or outside the semiconductor integrated circuit makes the P-channel MOS transistor P11 conductive at the gate of No. 1 only when the rising edge of the input signal I11 changes. Auxiliary drive that switches to a control circuit that turns on and a control circuit that turns off the P-channel MOS transistor P11 when the input signal I11 rises and detects the high voltage level of the output terminal Q11 to turn it on. The output of the circuit G12 is supplied.

The auxiliary drive circuit G12 is a cascade circuit 101 of two inverters for delaying the signal at the output terminal O11.
And an exclusive-OR EXOR gate 103 having its output and the control signal M11 as inputs, and a NAND gate 105 having its output and the input signal I11 as inputs.

The N-channel MOS transistor N
A control signal M10 inside or outside the semiconductor integrated circuit causes the gate of 11 to make the N-channel MOS transistor N11 conductive only when the falling edge of the input signal I11 changes, and detects the low voltage level of the output terminal Q11. A control circuit that makes the non-conduction state and a control circuit that makes the N-channel MOS transistor N11 non-conduction state when the input signal I11 falls and changes to a control circuit that detects the low voltage level of the output terminal Q11 and makes the conduction state. The output of the drive circuit G13 is supplied.

The auxiliary drive circuit G13 is a cascade circuit 102 of two inverters for delaying the signal at the output terminal O11.
And an exclusive-OR EXOR gate 104 having its output and the control signal M10 as inputs, and a NOR gate 106 having its output and the input signal I11 as inputs.

FIG. 2 is a waveform diagram showing the operation of this output buffer.

In FIG. 2, the control signals M10 and M11.
Are both set to a high level and the input signal I11 changes from the GND level to the VDD level, the gate potentials of the MOS transistors P10 and N10 are set to G via the drive circuit G11.
Since it changes to the ND level, the P-channel MOS transistor P10 is turned on and the N-channel MOS transistor N10 is turned off.

At the same time, the gate potential of the P-channel MOS transistor P11 is GN via the auxiliary drive circuit G12.
The P-channel MOS transistor P11 is turned on by changing to the D level, but as soon as the high voltage level of the output terminal Q11 is detected, the P-channel MOS transistor P11 is turned on.
Turns off.

Therefore, the P-channel MOS transistors P10 and P11 rapidly charge only when the signal transmission path rises and the output signal rises quickly.

On the other hand, when the input signal I11 changes from the VDD level to the GND level, M is output via the drive circuit G11.
The gate potential of the OS transistors P10 and N10 is VDD
Since it changes to the level, the P-channel MOS transistor P10 is turned off and the N-channel MOS transistor N1 is turned on.
0 turns on.

At the same time, the gate potential of the N-channel MOS transistor N11 is VD via the auxiliary drive circuit G13.
The N-channel MOS transistor N11 is turned on by changing to the D level, but as soon as the low voltage level of the output terminal Q11 is detected, the N-channel MOS transistor N11 is turned on.
Turns off. Therefore, the N-channel MOS transistors N10 and N11 cause rapid discharge only when the signal transmission path falls and the output signal falls rapidly.

As a result, in the steady state during high speed operation, it is possible to reduce the influence of noise generated by the shared power source.

Next, the control signals M10 and M11 are both set to low level, and the input signal I11 changes from GND level to VD.
When it changes to the D level, the MOS via the drive circuit G11
Since the gate potentials of the transistors P10 and N10 change to the GND level, the P channel MOS transistor P
10 is turned on and the N-channel MOS transistor N10 is turned off.

At this time, P via the auxiliary drive circuit G12
The gate potential of the channel MOS transistor P11 is V
The P-channel MOS transistor P11 remains off at the DD level, but the P-channel MOS transistor P11 turns on as soon as the high voltage level at the output terminal is detected. Therefore, the P-channel MOS transistor P10 is gradually charged only when the signal transmission path rises and the output signal rises slowly.

On the other hand, when the input signal I11 changes from the VDD level to the GND level, the drive circuit G11 outputs M
The gate potential of the OS transistors P10 and N10 is VDD
Since it changes to the level, the P-channel MOS transistor P10 is turned off and the N-channel MOS transistor N1 is turned on.
0 turns on.

At this time, the gate potential of the N-channel MOS transistor N11 is GN via the auxiliary drive circuit G13.
N-channel MOS transistor N with D level
Although 11 is in the off state, the N-channel MOS transistor N11 is turned on as soon as the low voltage level of the output terminal is detected. Therefore, the N-channel MOS transistor N10 gradually discharges only when the signal transmission path rises, and the output signal falls gently. As a result, it is possible to reduce the generation of noise in the power supply at the output change point during high current driving.

FIG. 3 is a circuit diagram of an output buffer according to the second embodiment of the present invention.

In FIG. 3, the basic structure of this embodiment is similar to that of the first embodiment, but in this embodiment, a drive circuit G for driving the P-channel MOS transistor P20 is used.
Reference numeral 21 denotes a drive circuit G22 configured by a NAND gate 207 and driving the N-channel MOS transistor N20.
Is composed of a NOR gate 208 and an inverter 200. The control signal E2 is supplied to these drive circuits.
1 is given.

Further, the P-channel MOS transistor P
The auxiliary drive circuit G23 for driving 21 is a 3-input NAND gate 205, an inverter and a 2-input NAND cascade circuit 2.
01, composed of EXOR gate 203, and NAN
The control signal E21 is input to the D gate 205 and the cascade circuit 201.

The auxiliary drive circuit G24 for driving the N-channel MOS transistor N21 is a 3-input NOR gate 2
06, cascade circuit 202 of inverter and 2-input NOR, E
The NOR gate 2 is formed by the XOR gate 204.
An inverted signal of the control signal E21 is input to the connection circuit 06 and the cascade circuit 202 via the inverter 200.

According to this embodiment, as shown in FIG. 4, when the control signal E21 is at the VDD level, the same operation as that of the first embodiment described above is performed, and when the control signal E21 is at the GND level. , MOS transistors P20, P21, N2
0 and N21 are all off.

[0032]

As described above, according to the present invention,
By using the control signal inside or outside of the semiconductor integrated circuit, it is possible to reduce the generation of noise to the power supply at the output change point at the time of high current drive, and to generate it by the shared power supply in the steady state during high speed operation. This has the effect of making it less susceptible to the effects of noise.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an output buffer according to a first embodiment of the present invention.

FIG. 2 is an operation waveform diagram of the output buffer according to the first embodiment of this invention.

FIG. 3 is a circuit diagram of an output buffer according to a second embodiment of the present invention.

FIG. 4 is an operation waveform diagram of the output buffer according to the second embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional output buffer.

FIG. 6 is a circuit diagram of a conventional output buffer for a bidirectional input / output circuit.

[Explanation of symbols]

100, 101, 102, 200, 201, 202, 3
00,400 Inverter 105,205,207,407 NAND gate 106,206,208,408 NOR gate 103,104,203,204 EXOR gate P10, P11, P20, P21, P30, P40
P-channel MOS transistors N10, N11, N20, N21, N30, N40
N-channel MOS transistor G11, G21, G22, G31, G41 Driving circuit G12, G13, G23, G24 Auxiliary driving circuit I11, I21, I31, I41 Input signal O11, O21, A31, O41 Output terminal E21, E41, M10, M11 , M20, M21
Control signal

Claims (1)

[Claims] 1. A first P-channel MOS transistor connected between a first power supply and an output terminal, and a first N-channel MOS transistor connected between a second power supply and the output terminal. And the first P-channel MOS transistor and the first N-channel MOS transistor.
In the output buffer, the transistor is complementarily controlled to conduct in accordance with the level of the input signal to drive the load connected to the output terminal, and the first P-channel MOS is provided.
A second P-channel MOS transistor connected in parallel with the transistor between the first power supply and the output terminal; and a second power supply and the output terminal in parallel with the first N-channel MOS transistor. A second N-channel MOS transistor connected between the two and a gate of the second P-channel MOS transistor, and at a change point of the input signal in accordance with an internal or external control signal. A control circuit that is in a conductive state and detects the voltage level of the output terminal to be in a non-conductive state, and is in a non-conductive state at a change point of the input signal, and is in a conductive state by detecting a voltage level of the output terminal. A first auxiliary control for controlling conduction of the second P-channel MOS transistor when the output terminal changes by switching to a control circuit When the second N-channel MOS
A control circuit which is connected to the gate of the transistor and is made conductive at a change point of the input signal according to an internal or external control signal, and is made non-conductive by detecting the voltage level of the output terminal; By switching to a control circuit that makes the input signal non-conducting at the change point and detects the voltage level of the output terminal to make it conductive, the second circuit is provided when the output terminal changes. N channel M
An output buffer provided with a second auxiliary control section for controlling conduction of an OS transistor.