JPH05206811A - Reset control circuit - Google Patents

Abstract

PURPOSE:To sufficiently take time till the rise-up of a reset control signal at the time of the rise-up of power supply, and on the other hand, to let the reset control signal fall in a short time at the time of the fall of the power supply so as to reset quickly a circuit. CONSTITUTION:A reset control circuit is constituted into circuit configuration in which a first and a second reset control circuit parts 221, 222 consisting respectively of a voltage detecting part 25 to detect supply voltage, a signal delaying part 27 to delay this detected signal, and a reset output part 29 to output the reset control signal by the signal after delay are connected in series. A resistor 24 is arranged between the second reset control circuit 222 and the power supply. The reset control signal outputted from the second reset control circuit 222 responds at the added value of both delay times at the time of the rise-up of the power supply, and responds at the shorter delay time at the time of the fall of the power supply.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset control circuit in which the output timing of a reset control signal used for initializing various circuits when power is turned on or off is devised.

[0002]

2. Description of the Related Art Various electronic devices are designed to initialize various circuits in the device when the power is turned on or off, and a reset control signal is used for that purpose.

FIG. 6 shows a conventionally used reset control circuit which outputs a reset control signal. The reset control circuit includes a voltage detection unit 12 that detects a power supply voltage that appears on a predetermined signal line 11. The voltage detection unit 12 compares the voltage with a specified voltage by a comparator, for example, and outputs a result signal 13 representing the result to the signal delay unit 14. The signal delay unit 14 inputs the delayed signal 15 obtained by delaying the result signal by a predetermined time to the reset output unit 16. When the delayed output signal 15 is input, the reset output unit 16 outputs a predetermined reset control signal 17 to an external circuit (not shown).

[0004]

Generally, in the reset control circuit, the delay time in the signal delay unit 14 is set to be relatively long at the time of power-on, and then the reset operation of the circuit is released. It may be necessary to remove the influence of the circuit due to the noise generated at the rise of the power supply, or to reset the circuit condition that is satisfied only after the rise of the power supply goes through a predetermined procedure. Because. However, if the delay time is increased in this way, the reset output unit 16 resets the circuit after the same delay time has elapsed when the power supply falls. Therefore, if an unnecessary signal such as noise resulting from the operation of the power switch occurs within a relatively short time after the start of the power supply fall, this cannot be prohibited by the reset control signal, The circuit may be adversely affected.

Therefore, an object of the present invention is to allow sufficient time until the reset control signal rises when the power supply rises to inhibit the detection of unnecessary signals, and to cause the reset control signal to fall in a short time when the power supply falls. It is an object of the present invention to provide a reset control circuit capable of performing a quick reset.

[0006]

According to a first aspect of the present invention, there is provided: (a) first voltage detecting means for comparing a power supply voltage with a prescribed voltage value to detect rising or rising of the voltage; and A first signal delay means for delaying the detection signal by a first delay time when the first voltage detection means detects a rising edge of the voltage, and a circuit based on the detection signal delayed by the first signal delay means. A first reset control circuit section including a first reset output section for generating a first reset control signal for performing the reset control of the power source, and (b) the above-mentioned power supply voltage and a prescribed voltage via a resistor. A second voltage detecting means for comparing a value with a value to detect a rising edge or a rising edge of the voltage; and when the second voltage detecting means detects a rising edge of the power supply voltage, this detection signal is output at the first delay time. A second signal delay means for delaying by a second delay time different from the above, and a second reset control signal for performing reset control of the circuit based on the detection signal delayed by the second signal delay means. A second reset control circuit section having a second reset output section for generating a voltage, and (c) second voltage detection means arranged at the output side of the first reset output section and at the subsequent stage of the resistor. And a line connected to the input side of the reset control circuit.

That is, according to the first aspect of the present invention, when the power supply voltage rises, the circuit is reset after a sufficient time has elapsed by the reset control signal which rises after being delayed by both the first signal delay means and the second signal delay means. When the power supply voltage falls, the circuit is reset based on the reset control signal having the shorter delay time as a reference.

According to the second aspect of the invention, (a) first voltage detecting means for comparing the power supply voltage with a prescribed voltage value to detect the rising or rising of the voltage, and the first voltage detecting means.
The first signal delay means for delaying the detection signal by the first delay time when the voltage detection means detects the rising of the voltage, and the circuit of the circuit based on the detection signal delayed by the first signal delay means. A first reset control circuit section having a first reset output section for generating a first reset control signal for performing reset control; and (b) a voltage comparing a power supply voltage with a prescribed voltage value. Rising edge or a second voltage detecting means for detecting the rising edge, and when the second voltage detecting means detects the rising edge of the power supply voltage, this detection signal is output for a second delay time different from the first delay time. Second signal delay means for delaying, and a second reset control signal for performing reset control of the circuit based on the detection signal delayed by the second signal delay means. Second with a second reset output portion
The reset control circuit section, and (c) a reset control signal output terminal for reset control signal output, which connects the output side of the first reset output section and the output side of the second reset output section. Let

That is, according to the second aspect of the present invention, when the power supply voltage rises, the reset control signal which rises after a longer delay of the first signal delaying means and the second signal delaying means causes the circuit to be activated after a sufficient time has elapsed. The reset is released, and the circuit is reset at the time of the fall of the power supply voltage based on the reset control signal of the shorter delay time.

[0010]

EXAMPLES The present invention will be described in detail below with reference to examples.

First embodiment

FIG. 1 is a block diagram of a reset according to the first embodiment of the present invention.
1 shows a schematic configuration of a control circuit. This re
The set control circuit is the signal line 21.₁Enter the voltage of the first
1 reset control circuit unit 22₁And from now on
First reset control signal 23 ₁Second reset to enter
Control circuit section 22₂It has and. Second reset system
Circuit part 22₂One end of the resistor 24 is connected to the input side of
Signal line 21 at the other end₂Connected to
It In addition, the second reset control circuit unit 22₂From the second
Reset control signal 23₂Is output
It

Here, the first reset control circuit section 22
Reference numeral ₁ denotes a first voltage detection unit 25 ₁ that detects the voltage of the signal line 21 ₁ , a first signal delay unit 27 ₁ that delays the detected first detection signal 26 _1, and a delayed _first signal detection unit 26 1. first reset control signal 23 to input the detection signal 28 ₁
And a first reset output unit 29 ₁ for outputting a _1. Similarly, the second reset control circuit unit 22 ₂ also has a second
Voltage detector 25 ₂ and the detected second detection signal 2
6 ₂ and the second signal delay unit 27 ₂ for delaying the delayed configuration second from the reset output unit 29 ₂ which second inputs detection signals 28 ₂ to output a second reset control signal 23 ₂ Has been done.

The circuit configurations of the first and second reset control circuit sections 22 ₁ and 22 ₂ may be the same. However, in the first embodiment, the first reset control circuit unit 22
Since connecting the _first output to the second input of the reset control circuit 22 _2, the second reset control circuit 22 ₂
This can be omitted by substantially replacing the resistor 32 of FIG.

FIG. 2 shows a specific circuit configuration of the reset control circuit section. The voltage detection unit 25 of the reset control circuit unit 22 is a circuit unit that compares the power supply voltage with a specified voltage value V _C1 and determines whether it is higher or lower than the specified voltage value V _C1 . The voltage detecting unit 25 includes two resistors 32 and 3 for dividing the voltage V _C of the power supply voltage measuring portion 31.
Equipped with 3. A connection point 34 of these resistors 32 and 33 having resistance values R ₁ and R ₂ , respectively, is connected to a (−) input terminal of a differential amplifier circuit 35. The internal fixed voltage V _C1 is applied to the (+) input terminal of the differential amplifier circuit 35. As a result, at the measurement point 36 on the output side of the differential amplifier circuit 35, the voltage of the power supply voltage measuring portion 31 becomes H (high) level when the voltage is higher than the specified voltage value V _C ′, and in other cases. Will output the detection signal 26 that is at the L (low) level.

The specified voltage V _C ′ can be expressed by the following equation.

[0017]

[Equation 1]

As shown in FIG. 2, the signal delay unit 27 which receives the detection signal 26 and delays it by a predetermined time has a resistor 38, a transistor 39 having one end connected to the base and an emitter installed, and a resistor 39. A differential amplifier circuit 41 having a (−) input terminal connected to the collector side of the transistor 39 is provided. To the collector side of the transistor 39, a constant current circuit 42 for supplying a current i _C and a capacitor 43 having one end installed with a capacitance C _t are also connected. The fixed voltage V _C2 is applied to the (+) input terminal of the differential amplifier circuit 41.

In such a signal delay unit 27, the detection signal 2
The set time td for delaying 6 is the constant current circuit 42
Of the current i _C , the fixed voltage V _C2 of the differential amplifier circuit 41, and the capacitance C _{t of the} capacitor 43 are expressed by the following equation.

[0020]

[Equation 2]

The detection signal 28 delayed in this way is output to the measurement point 44 on the output side of the differential amplifier circuit 41 of the signal delay unit 27.

The reset output unit 29, which receives the delayed detection signal 28 and outputs the reset control signal 23,
As shown in FIG. 2, the resistor 4 having one end connected to the measurement point 44
5 and a grounded emitter transistor 46 having a base connected to the other end of the resistor 45. The reset control signal 23 is output from the collector of the transistor 46. Thus, the reset output unit 29 is a drive circuit for outputting the reset control signal 23 to the outside, and is generally an open collector output circuit.

FIG. 3 is a diagram for explaining the operation of the reset control circuit in the first embodiment in which the two reset control circuit sections described in FIG. 2 are connected. In the description, the circuit with the subscript " ₁ " relates to the first reset control circuit unit 22 ₁ , and the circuit with the subscript " ₂ " relates to the second reset control circuit unit 22 ₂ .

First, the case where the power supply voltage rises will be described. Assume that the power supply voltage starts rising at time t ₁ as shown in FIG. When the voltage of the power supply voltage measurement portion 31 becomes higher than the specified voltage value V _C ′, the detection signal 26 ₁ (FIG. 3 (b)) output from the voltage detection unit 25 ₁ in the first reset control circuit unit 22 ₁ The signal level changes. This detection signal 26 ₁ is sent to the first signal delay unit 27 ₁
Then, the detection signal 28 ₁ (inverted waveform) delayed by the set time td _r1 (subscript “ _r ” indicates rising time) is output as shown in FIG. 3C. The output timing of the detection signal 28 ₁ is the constant current circuit 42
It is when the current i _C flowing through the capacitor 43 charges the capacitor 43 with a predetermined amount or more. Therefore, the smaller the current i _C or the larger the capacitance C _{t of the} capacitor 43, the longer the set time td _r1 . First reset output unit 29
₁ outputs a _first reset control signal 23 ₁ as shown in FIG. 7D based on this detection signal 28 ₁ .

This first reset control signal 23₁Is Figure 1
And the second voltage detector 25 shown in FIG.₂Connection point 51
Is supplied to. Second voltage detector 25₂Is the first reset
Control signal 23₁As long as is at the L level
Line 21₂The power supply voltage applied to the
Even if it is, it can be detected by the voltage drop of the resistor 24.
I can't. Therefore, as shown in FIG.
First reset control signal 23₁Changes to H level
For the first time, the voltage is detected. Then, as shown in FIG.
Detection signal 26₂Is output. Second signal delay unit 2
7₂This detection signal 26₂Set time td_r1Different from
Set time td_r2Delayed by the second detection signal
No. 28₂(FIG. 3 (g)) is output. Second reset issue
Force section 29 ₂Based on this, the second list shown in FIG.
Set control signal 23₂Will be output.

Thus, when the power supply voltage rises as shown in FIG. 3A, the first reset control circuit section 2
2 ₁ of the second reset control after both delays the detection signal 26 ₂ by detecting signal 26 _first delay and the second reset control circuit 22 ₂ has passed a relatively long time from the rising of the supply voltage acts The reset control signal 23 ₂ output from the circuit unit 22 ₂ rises. Therefore, the reset of each part of the system is not released until this point. Therefore, as shown in FIG. 3I, even when the unnecessary signal 52 such as noise is generated immediately after the start of the rise of the power supply voltage, the reset control signal 23 ₂ is released after this, so that the detection of the signal so far is not possible. It will be banned and will not harm the system.

Next, the case where the power supply voltage falls will be described. It is assumed that the fall of the power supply voltage has started at time t ₂ as shown in FIG. Shortly after this, the first voltage detection unit 25 ₁ detects that the voltage at the connection point 51 has dropped below the specified voltage value V _C ′ (FIG. 3).
(B)). Then, from this point onward, the time is delayed by the set time td _f1 (where the subscript “ _f ” indicates the falling time), and FIG.
As shown in (c), the delayed detection signal 28 ₁ (inverted waveform) is output. The detection signal 28 ₁ is output at the timing when the electric charge accumulated in the capacitor 43 is discharged by the ON resistance between the collector and the emitter due to the ON operation of the transistor 39. Therefore, in the circuit configuration of this embodiment in which the capacitance of the capacitor 43 is not particularly large, the detection signal 28 ₁ is output in a shorter time than when the power source is started up. The first reset output unit 29 ₁ outputs a first reset control signal 23 ₁ as shown in FIG. 7D based on this detection signal 28 ₁ . This first reset control signal 23 ₁ will be supplied to the connection point 51.

By the way, when the power supply voltage rises,
When the first reset control signal 23 ₁ rises, the second reset control signal 23 ₁
The voltage detection unit 25 _{2 of the above} performs the detection operation. However, when the power supply voltage falls, the connection point 5 is reduced due to the decrease in the power supply voltage applied to the signal line 21 ₂ even when the first reset control signal 23 _{1 is} still at the H level.
The potential of 1 decreases. As a result, the second voltage detector 25
₂ detects a decrease in the power supply voltage at approximately the same time as the first voltage detector 25 ₁ (FIG. 3 (e)) and outputs a detection signal 26 ₂ (FIG. 3 (f)).

The second signal delay unit 27 ₂ receives the detection signal 2
6 ₂ is delayed by a set time td _f2 different from the set time td _f1, and the delayed second detection signal 28 ₂ (see FIG. 3).
(G)) is output. Based on this, the second reset output unit 29 ₂ outputs the second reset control signal 23 ₂ shown in FIG. 3 (h).

As described above, at the fall of the power supply voltage, two
Reset control circuit section 22₁, 22 ₂At the same time
Detects the descent, and based on this, with a shorter delay time
The reset control signal 23 is output. Because
Then, as shown in Fig. 3 (i),
The unwanted signal 52 should be generated within a relatively short time from the beginning.
In such a case, the reset control signal 23 should be sent before this.₂With equipment each
Parts will be reset, which will adversely affect the system.
There is almost no catch.

In the first embodiment described above, the first
Reset control signal 23₁Supply to the connection point 51
Not the second reset control signal 23₂Another reset
It can be used as a control signal. That is, the figure
3 reset these as shown in (d) and (h)
Control signal 23₁, 23₂Rising and falling edges of
Immings are different. Therefore, the second
Reset control signal 23 ₂Reset timing than
For the preferred circuit part, this first reset
Control signal 23₁It is also possible to supply
is there.

Second embodiment

FIG. 4 shows a schematic configuration of the reset control circuit in the second embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be appropriately omitted. The reset control circuit of the second embodiment includes a first reset control circuit section 22 ₁ for inputting the voltage of the signal line 21 and a second reset control circuit section 22 ₂ for similarly inputting the voltage of the signal line 21. I have it. First
The output sides of the second reset control circuit units 22 ₁ and 22 ₂ are connected by a connection point 61, and the reset control signal output terminal 62 connected to the connection point 61 outputs a reset control signal 63. ing.

Here, the first reset control circuit section 22
Reference numeral ₁ denotes a first voltage detection unit 25 ₁ for detecting the voltage of the signal line 21, a first signal delay unit 27 ₁ for delaying the detected first detection signal 26 _1, and a delayed _first signal detection unit 27 1. The detection signal 28 ₁ is input to the first reset control signal 23 ₁
Of the first reset output unit 29 _{1 for} outputting. Similarly, the second reset control circuit unit 22 ₂ and the second voltage detection unit 25 ₂ and the detected second detection signal 26 2
₂ and ₂ a second signal delay unit 27 for delaying, consists second reset output unit 29 ₂ for outputting a ₂ second detection signal 28 ₂ enter the second reset control signal 23 which is delayed ing.

The circuit configurations of the first and second reset control circuit sections 22 ₁ and 22 ₂ are the same. Since the specific circuit configuration of them has been described in detail with reference to FIG. 2, the description thereof will be omitted.

FIG. 5 is a diagram for explaining the operation of the reset control circuit in the second embodiment. In addition,
In the description, the circuit with the subscript " ₁ " relates to the first reset control circuit unit 22 ₁ , and the circuit with the subscript " ₂ " relates to the second reset control circuit unit 22 ₂ .

First, the case where the power supply voltage rises will be described.
It As shown in FIG. 5A, time t₁Power supply voltage rises
Suppose that you have started climbing. Power of the power supply voltage measurement part 31
Pressure is the specified voltage value V_CHigher than ', the first and
2 reset control circuit section 22 ₁, 22₂Voltage detection on both sides
Output 25₁, 25₂Detection signal 26 output from₁Two
6₂The signal level in FIG. 5B changes. Detection signal
26₁Is the first signal delay unit 27₁And set time td_r1(This
Subscript "_r"Indicates the rising time.) Delayed
Detection signal 28 delayed as shown in FIG.
₁(Inverted waveform) is output. In contrast, the detection signal
26₂Is the second signal delay unit 27₂And set time td_r2(Ta
Dashi td_r1<Td_r2), And shown in FIG.
Detection signal 28 delayed as₂(Inverted waveform) is output
To be done.

Based on the delayed detection signal 28 ₁ , the first reset output unit 29 ₁ outputs a reset control signal indicating a change in the signal level at substantially the same timing,
The second reset output unit 29 ₂ has the delayed detection signal 2
Based on 8 ₂ , a reset control signal indicating a change in signal level is output at substantially the same timing as this. However, since the output sides of the first and second reset output sections 29 ₁ and 29 ₂ are commonly connected, the reset control signal 63 output from the reset control signal output terminal 62 is the same as in FIG.
As shown in (e), the signal is delayed by the longer delay time.

Thus, when the power supply voltage rises as shown in FIG. 5A, the first reset control circuit section 2
2 ₁ by the detection signal 26 _first delay and the second reset control circuit 22 ₂ reset control signal 63 after a larger time delay amount of the delay of the detection signal 26 ₂ has passed by
Then, the reset of each part of the system is released. Therefore, as shown in FIG. 5F, even when the unnecessary signal 52 such as noise is generated immediately after the start of the rise of the power supply voltage, the reset control signal 63 that rises after that releases the reset of each part of the device, It does not harm the system.

Next, the case where the power supply voltage falls will be described.
It As shown in FIG. 5A, time t₂Power supply
It is assumed that the descent has started. Shortly after this
First and second voltage detector 25₁, 25₂Is the power supply voltage
Is the specified voltage value V_CIt is detected that it is lower than
5 (b)). As a result, the detection signal 26₁Will be set
Time td_f1Delay, as shown in Fig. 5 (c).
Delayed detection signal 28 ₁(Inverted waveform) is output. Well
Detection signal 26₂Is the set time td_f2(However
td_f2<Td_f2), It is shown in Fig. 5 (d).
Detection signal 28 delayed as₂(Inverted waveform) is output
It

The first reset output unit 29 ₁ outputs a reset control signal indicating a change in signal level based on the delayed detection signal 28 ₁ at substantially the same timing as the detected signal 28 ₁ .
The second reset output unit 29 ₂ has the delayed detection signal 2
Based on 8 ₂ , a reset control signal indicating a change in signal level is output at substantially the same timing as this. However, since the output sides of the first and second reset output sections 29 ₁ and 29 ₂ are commonly connected, the actual reset control signal 63 represented at the connection point 61 is as shown in FIG. The signal is delayed by the shorter delay time.

In this way, when the power supply voltage falls as shown in FIG. 5A, the first reset control circuit section 2
2 ₁ by the detection signal 26 _first delay and the second reset control circuit 22 ₂ reset control signal 63 after a time of smaller delay amount of the delay of the detection signal 26 ₂ has passed by
Is output and is used to reset each part of the system. Therefore, even if the unnecessary signal 52 is generated within a relatively short time from the start of the fall of the power supply voltage as shown in FIG. 5F, the reset control signal 63 resets each part of the device before this. This is normally done and rarely affects the system.

[0043]

As described above, in the present invention, two sets of reset control circuit sections having different delay times are arranged in series or in parallel, and the delay times of these reset control circuit sections are made different. Therefore, when the power supply voltage falls, it is possible to obtain a reset control signal in which the power supply voltage fall is detected by the shorter delay time. As a result, even if there is an influence of a malfunction of the circuit when the power supply voltage drops or an unnecessary signal is generated, it is possible to immediately prohibit these.

Further, in the present invention, since two sets of reset control circuit parts are connected in series or in parallel to form a reset control circuit, there are many common parts of the circuit, and the circuit can be manufactured at low cost. There are advantages.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of a circuit configuration of a reset control circuit according to a first embodiment of the present invention.

FIG. 2 is a specific circuit diagram of a reset control circuit section in the first and second embodiments.

FIG. 3 is a waveform diagram showing a signal waveform of each part of the reset control circuit in the first embodiment.

FIG. 4 is a block diagram showing an outline of a circuit configuration of a reset control circuit according to a second embodiment of the present invention.

FIG. 5 is a waveform diagram showing a signal waveform of each part of the reset control circuit in the second embodiment.

FIG. 6 is a block diagram showing a conventionally used reset control circuit that outputs a reset control signal.

[Explanation of symbols]

22 ₁ 1st reset control circuit part 22 ₂ 2nd reset control circuit part 23 ₁ 1st reset control signal 23 ₂ 2nd reset control signal 24, 32, 33 resistance 25 ₁ 1st voltage detection part 25 ₂ 2nd voltage detection part 27 ₁ 1st signal delay part 27 ₂ 2nd signal delay part 29 ₁ 1st reset output part 29 ₂ 2nd reset output part 35,41 Differential amplifier circuit 39,46 Transistor 42 Constant current circuit 43 Capacitor 62 Reset control signal output terminal 63 Reset control signal

Claims (2)

[Claims] 1. A first voltage detecting means for comparing a power supply voltage with a prescribed voltage value to detect the rising or rising of the voltage, and the detection when the first voltage detecting means detects the rising of the voltage. First signal delay means for delaying a signal by a first delay time, and a first reset control signal for performing circuit reset control based on the detection signal delayed by the first signal delay means A first reset control circuit section having a first reset output section for detecting the rising or rising of the voltage by comparing the power supply voltage with a prescribed voltage value via a resistor; Second means for delaying the detection signal by a second delay time different from the first delay time when the second voltage detecting means detects the rise of the power supply voltage.
Signal delay means and a second reset output section for generating a second reset control signal for performing reset control of the circuit based on the detection signal delayed by the second signal delay means. And a line connecting the output side of the first reset output section and the input side of the second voltage detecting means arranged in the latter stage of the resistor. Reset control circuit. 2. A first voltage detecting means for detecting rising or rising of a voltage by comparing a power supply voltage with a specified voltage value, and detecting the rising of the voltage when the first voltage detecting means detects the rising of the voltage. First signal delay means for delaying a signal by a first delay time, and a first reset control signal for performing circuit reset control based on the detection signal delayed by the first signal delay means A first reset control circuit section having a first reset output section for enabling the second reset voltage, and a second voltage detecting means for comparing the power supply voltage with a prescribed voltage value to detect rising or rising of the voltage, Second signal delay means for delaying the detection signal by a second delay time different from the first delay time when the second voltage detection means detects the rise of the power supply voltage; A second reset control circuit section having a second reset output section for generating a second reset control signal for performing reset control of the circuit based on the detection signal delayed by the second signal delay means. And a reset control signal output terminal for outputting a reset control signal, which connects the output side of the first reset output section and the output side of the second reset output section.