JP2846200B2 - Capacitor discharge circuit and timing generation circuit using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a capacitor discharge circuit,
More particularly, the present invention relates to a capacitor discharging circuit used for timing setting in an electronic circuit.

[0002]

2. Description of the Related Art When an operation timing of an electronic circuit is generated, for example, a timing generation circuit utilizing charge and discharge of a capacitor is used. FIG. 4 is a circuit diagram of a conventional timing generation circuit using such a capacitor, and FIG. 5 is an operation time chart thereof.

The timing generation circuit shown in FIG. 4 is configured to generate a timing of an output signal by comparing a voltage between both ends of a capacitor C with a separately set reference potential.
That is, when the switch SW is closed, the capacitor C
, No current flows, and the voltage Vc across the terminal remains at “0” V. When the switch SW is opened, a current flows from the power supply Vcc through the resistor R1, and the electric charge is accumulated in the capacitor C. At this time, the voltage Vc of the capacitor C changes with the value shown by Vc = Vcc (1−exp (−t / CR)).

When the voltage Vc is input to the non-inverting terminal of the comparator 12 via the buffer 10 and becomes equal to or higher than the reference voltage Vr input to the inverting terminal, the output OU of the comparator 12 is output.
T transitions to a higher potential. As described above, the timing of the output OUT of “HIGH” or “LOW” occurs due to the change in the potential input to the non-inverting terminal of the comparator 12.
Therefore, the time immediately after the switch SW is opened is set to “0”.
Is represented by T = CRln (Vcc / (Vcc-Vr)).

The operation of generating the above timing is shown in the first half of the time chart of FIG.

In order to always perform this timing accurately, the initial value of the voltage across the capacitor must be "0" V when this circuit starts operation.

When this timing circuit is used for initial setting of other electronic circuits, the timing circuit starts operating when:-when the SW is operated from a closed state;-when the power supply voltage is momentarily interrupted. In this case, there are two cases in which the operation is performed from the state of “0” V. The former is a case where this circuit is operated from the reset state with consciousness, and there is no particular problem. The latter can be considered in two cases, that is, immediately after the power is turned on and when the power is momentarily interrupted. Among them, a problem occurs when the power is instantaneously interrupted.

When a momentary interruption of the power supply Vcc occurs, the electric charge stored in the capacitor C is discharged through the resistor R1. The discharge at this time can be expressed by the following equation: Vc = Vc0.exp (-t / CR). Here, Vc0 is a voltage between both ends of the capacitor immediately before the instantaneous interruption of the power supply.

The voltage Vc of the capacitor C at the time of recovery from the instantaneous interruption is determined by the duration of the instantaneous interruption and the discharge time constant. In general, a large value of the resistor R1 for determining the discharge time constant is used in order to increase the timing.

Therefore, when the instantaneous interruption time is short, the voltage across the capacitor C may not be completely "0" V. When the instantaneous interruption is recovered in such a state, the potential transition of the comparator output OUT of the timing circuit shown in FIG. 4 occurs earlier than in the case where the switch SW is opened and activated, and the timing is reduced. It will not be accurate. That is, when the instantaneous interruption is recovered in a state where the instantaneous interruption time is short and the electric charge of the capacitor C is not sufficiently discharged, FIG.
The timing T2 becomes shorter than the normal timing T1 as shown by the symbol A in FIG.

FIG. 6 is a circuit diagram of a conventional timing generating circuit in which diodes D are connected in opposite directions to both ends of a resistor R1 in order to prevent such a state from occurring. The role of the diode D is to discharge the capacitor C via the diode D when the power supply drops to a potential of “0” V due to a momentary interruption or the like, thereby completing the discharge as soon as possible. Things.

As can be seen from the VI characteristic shown in FIG. 7, the diode D exhibits a very low impedance when the voltage applied to both ends thereof is equal to or higher than a certain value. Since the time constant CR becomes short, the discharge is performed quickly.

[0013]

However, even in such a timing generation circuit using the diode D, the VI characteristic of the diode D shows the characteristic as shown in FIG.
That is, when the voltage across the capacitor C is large, the differential resistance of the diode D is very small, but when the discharge proceeds and the voltage across the both ends becomes low, the differential resistance becomes very large. It has the property that the discharge time constant does not decrease.

For this reason, even when the discharge diode D is used, the discharge does not exceed a certain value within a short time.
There is a drawback that the timing generated by the timing generation circuit is not constant, and the drawback of FIG. 4 has not been sufficiently solved. This property is exactly the same even if a transistor is used instead of the diode D.

The timing generator circuit must be completely initialized even when used to set the initial state of the circuit when the power is turned on or when the power supply is momentarily interrupted. When this occurs, there is a disadvantage that the initial setting time is not sufficiently secured, and the circuit operation becomes unstable.

The present invention solves the above-mentioned drawbacks of the prior art, and provides a highly reliable capacitor discharge circuit which ensures a sufficient predetermined initial setting time even when an instantaneous interruption or the like occurs, and a timing generation using the same. It is intended to provide a circuit.

[0017]

In order to solve the problems of the prior art, the present invention has a capacitor having one end connected to a power supply and the other end grounded, and a switch connected in parallel to the capacitor. and to charge the charge on the capacitor when the switch is turned off, the discharge circuit of the capacitor for discharging the charge of the capacitor when the on state, the input current of a predetermined input from the power supply current
A photodiode that emits light when it is higher
When the diode is not emitting light, it exhibits low resistance and emits light.
It consists of a photo MOS transistor that becomes high resistance
It has variable resistance means, and the photo MOS transistor
Connected in parallel with the
When a momentary power interruption occurs, the photo MOS transistor
The charge of the capacitor is discharged through the
doing.

Further, the present invention has a capacitor having one end connected to a power supply and the other end grounded, and a switch connected in parallel with the capacitor, and charges the capacitor when the switch is turned off. The timing generation circuit generates a timing signal by discharging the charge of this capacitor when turned on.
A flash that emits light when the input current input is higher than a predetermined current
Photo diode and photo diode do not emit light
Photo that sometimes shows low resistance and becomes high resistance when emitting light
A variable resistance means comprising a MOS transistor;
A tomos transistor is connected in parallel to the capacitor.
Of the capacitor charged and discharged by the switch
Enter the voltage change at the end and compare it to the reference voltage
Depending on the timing of either high level or low level
Switching means for generating a switching signal
If the power is interrupted during the
That the capacitor charge is discharged through the transistor.
This is a characteristic timing generation circuit.

[0019]

According to the present invention, when the switch is in the off state, the capacitor is charged, and when the switch is in the on state, the charged charge is discharged. Further, when the power supply is momentarily interrupted while the switch is off, the electric charge charged in the capacitor is discharged through the variable resistance means having reduced resistance.

Further, according to the present invention, when the switch is off, the capacitor is charged and the comparator outputs a high-level timing signal. When the switch is on, the charged charge is discharged from the capacitor and becomes low-level. A timing signal is output from the comparing means. Also, when the power supply is momentarily interrupted while the switch is off, the electric charge accumulated in the capacitor is discharged through the variable resistance means having reduced resistance.

[0021]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a discharge circuit of a capacitor according to the present invention and a timing generation circuit using the same.

FIG. 1 is a circuit diagram showing an embodiment of a timing generating circuit using a capacitor discharging circuit according to the present invention. One end of the capacitor C is connected to a power supply Vc via a resistor R1.
c, the other end is grounded. This capacitor C has
A switch SW having one end connected to the power supply Vcc via the resistor R1 and the other end grounded is connected in parallel.

The terminal on the power supply Vcc side of the capacitor C is connected to the non-inverting input terminal of the buffer 10. The buffer 10 is a buffer having a gain of “1” for accurately detecting the input terminal voltage Vc of the capacitor C by directly inputting its output to the inverting input terminal. Buffer 10
Is connected to the non-inverting input terminal of the comparator 12.

The comparator 12 outputs a high-level (HI) or low-level (LOW) timing signal OU according to the value of the voltage Vc input to the non-inverting input terminal.
This is a circuit that outputs T. That is, the comparator 12 has the inverting input terminal connected to the reference potential Vr, and sets the LOW timing when the value of the voltage Vc input to the non-inverting input terminal is lower than the reference potential Vr, and the HIGH timing when the value is higher. Output a signal.

Further, in the timing generation circuit of this embodiment, a photo MOS relay PMR is connected to the capacitor C in parallel. The photo MOS relay PMR is a variable resistance circuit that shows low resistance when the input current Id input from the power supply Vcc is lower than a predetermined current, and changes to high resistance when a current higher than this current value flows. is there. The photo MOS relay PMR is a combination of a depletion type photo MOS transistor MT and a photodiode PD, and one end (A) of the photo MOS transistor MT has a resistor R.
1 and the other end (B).
Is grounded, one end of the photodiode PD is connected to the power supply Vcc via the resistor R2, and the other end is grounded.

When the voltage of the power supply Vcc is a normal value,
It is necessary to supply a current Id large enough to emit a necessary amount of light to the light emitting diode PD of the photo MOS relay PMR. Therefore, a resistor R2 having a predetermined resistance value is interposed between the power supply Vcc and the light emitting diode PD. It should be noted that the photo MOS relay PMR shown here has an output resistance (A) of the photo MOS transistor MT in a state in which a certain or more current Id does not flow through the light emitting diode PD inside.
B) shows a very small value, and has a property that when a current Id exceeding a certain value flows and a light emitting diode emits light, the light emitting diode shows a very high resistance.

FIG. 2 is a characteristic diagram showing the characteristics of the input current Id and the output resistance Ro of the photo MOS relay PMR in this embodiment. When the photo MOS relay PMR having such characteristics is connected in the form shown in FIG. 1, when the power supply voltage Vcc is normal and a sufficient current can flow through the photodiode PD, the output resistance is reduced. Has a very large value, which is the same state that nothing is connected to both ends of the capacitor C. Therefore, power supply Vcc
When the switch SW is opened in a state where the state is normal, it becomes substantially the same as when nothing is connected,
The photo MOS relay PMR added here is a capacitor C
Has no effect on the charging process.

On the other hand, when the power supply voltage Vcc is
In a state in which a current Id sufficient to cause D to emit light is equal to or lower than a voltage, both ends of the capacitor C are always short-circuited with a low resistance value. Therefore, a momentary interruption of the power supply Vcc occurs, and when the power supply voltage Vcc decreases, the capacitor C is short-circuited with a very low resistance, and the discharge time constant becomes very small, so that the discharge is rapidly performed. .

In this case, since the resistance value of the photo MOS transistor MT is constant regardless of the current or the voltage, the discharge time depends on the discharge state of the capacitor C like a diode which has been conventionally used to speed up the discharge. The phenomenon that the constant changes does not occur. Therefore, the discharge is performed rapidly until the charge in the capacitor C becomes zero.

As described above, if the capacitor is completely discharged at the time of the instantaneous interruption of the power supply, since the state is restored to the complete initial state at the time of the instantaneous interruption recovery, the timing at the time of the instantaneous interruption recovery becomes shorter than a predetermined value. There is no such phenomenon. As described above, in the present embodiment, even when an instantaneous interruption or the like occurs, a sufficient timing T2 can be ensured as indicated by reference numeral B in FIG.

The photo MOS relay PMR having such characteristics is commercially available and easily available.

[0032]

As has been described in detail above, the use of the capacitor discharge circuit according to the present invention makes it possible to use a photo MOS transistor.
Since the relay is rapidly discharged by the relay-PMR, accurate timing can always be generated, and if used for a circuit reset function at the moment of a power interruption, a sufficient reset time can be secured in any case with high reliability. A timing generation circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a timing generating circuit to which a capacitor discharging circuit according to the present invention is applied.

FIG. 2 is a characteristic diagram showing characteristics of a photo MOS relay of the timing generation circuit of FIG.

FIG. 3 is an operation timing chart showing an operation at a momentary interruption in the timing generation circuit of FIG. 1;

FIG. 4 is a timing generation circuit using a capacitor according to the related art.

FIG. 5 is an operation timing chart of the conventional timing generation circuit shown in FIG . 4 ;

FIG. 6 is another prior art of a timing generation circuit using a capacitor.

FIG. 7 is a VI characteristic diagram of a diode in the conventional timing generation circuit shown in FIG.

[Explanation of symbols]

 10 Buffer 12 Comparator C Capacitor MT Photo MOS transistor PD Photo diode PMR Photo MOS relay R1, R2 Resistance SW switch

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03K 17/24 H03K 5/13 H03K 17/22

Claims (2)

(57) [Claims] 1. A capacitor having one end connected to a power supply and the other end grounded, and a switch connected in parallel to the capacitor. When the switch is turned off, the capacitor is charged with electric charge and turned on. In the discharge circuit of the capacitor that discharges the charge of the capacitor when the state is set, if the input current input from the power supply is higher than a predetermined current,
A photodiode that emits light when the photodiode is not emitting light, and a low resistance when the photodiode does not emit light.
Photo MOS transistor which becomes high resistance when emitting light
And a variable resistance means comprising: a photo-MOS transistor connected in parallel to the capacitor.
It has a configuration in which connection, when the switch is the instantaneous power interruption of in the off state occurs, a discharge circuit of the capacitor charge of the capacitor through the photo-MOS transistor is characterized in that it is discharged. 2. A capacitor having one end connected to a power supply and the other end grounded, and a switch connected in parallel to the capacitor. When the switch is turned off, the capacitor is charged with electric charge and turned on. In a timing generation circuit that generates a timing signal by discharging the charge of the capacitor when the state is set, when an input current input from the power supply is higher than a predetermined current,
A photodiode that emits light when the photodiode is not emitting light, and a low resistance when the photodiode does not emit light.
Photo MOS transistor which becomes high resistance when emitting light
And a variable resistance means comprising: a photo-MOS transistor connected in parallel to the capacitor.
It has a configuration that continue to enter the voltage change across the charging discharged capacitor by the switch, and comparator means for generating one of said timing signal at a high level and a low level by comparing this reference voltage A timing generation circuit, wherein when a momentary interruption of the power supply occurs while the switch is in an off state, the charge of the capacitor is discharged via the photo MOS transistor.