JPH05206673A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPH05206673A
JPH05206673A JP27868291A JP27868291A JPH05206673A JP H05206673 A JPH05206673 A JP H05206673A JP 27868291 A JP27868291 A JP 27868291A JP 27868291 A JP27868291 A JP 27868291A JP H05206673 A JPH05206673 A JP H05206673A
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit
hybrid integrated
circuit device
noise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP27868291A
Other languages
Japanese (ja)
Other versions
JP2703434B2 (en
Inventor
Katahito Kanetani
賢仁 金谷
Seiwa Ueno
聖和 上野
Kenichi Kobayashi
健一 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP27868291A priority Critical patent/JP2703434B2/en
Publication of JPH05206673A publication Critical patent/JPH05206673A/en
Application granted granted Critical
Publication of JP2703434B2 publication Critical patent/JP2703434B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

PURPOSE:To avoid the leakage of noise through gaps of the overlapping part of a shielding case by a method wherein the overlapping part of the shielding case which covers all the surfaces of a hybrid integrated circuit device except the surface on which outer leads are provided is spot-welded with a predetermined interval. CONSTITUTION:A shield case 40 covers all the surfaces of a hybrid integrated circuit device except the surface on which outer leads 30 are provided and is composed of two metal components taking the difficulty of a press process into account. Heat radiation holes 44 whose diameters are not larger than 1/10 of the wavelength of a noise in question are formed in the side surfaces of the shielding case 40 and the problems of heat radiation and the noise are resolved simultaneously. Further, the overlapping part of the shielding case 40 composed of two metal components is spot-welded 46 with an interval not larger than 1/10 of the wavelength of the noise. With this constitution, the leakage of the noise through gaps of the overlapping part of the shielding case 40 can be avoided.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はデイジタルTV用の混成
集積回路装置に関し、詳細には、その漏洩ノイズを低減
する技術に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device for a digital TV, and more particularly to a technique for reducing its leakage noise.

【0002】[0002]

【従来の技術】デイジタルTVは高画質が達成できる
点、画像の加工が容易である点、無調整で高信頼回路が
得られる点、さらには回路のIC化が容易である点でア
ナログ方式に勝っている。図8および図9を参照してデ
イジタルTVおよびデイジタルTV用の混成集積回路装
置を説明する。
2. Description of the Related Art A digital TV is an analog type because it can achieve high image quality, can easily process an image, can obtain a highly reliable circuit without adjustment, and can easily be integrated into a circuit. I'm winning A digital TV and a hybrid integrated circuit device for a digital TV will be described with reference to FIGS.

【0003】図8を参照すると、デイジタルTVは50
MHZ〜1GHZのTV電波を復調して略4.5MHZの
帯域を有する輝度信号Yと色差信号R−Y、B−Yを出
力するチューナ(50)、13.5MHZの標本化周波数で
動作する6〜10ビットのA/D変換回路(52)、画像メ
モリ(54)、演算回路(56)、D/A変換回路(58)、ビデオ
出力回路(60)およびCRT(62)から構成される。
Referring to FIG. 8, a digital TV has 50
A tuner (50) that demodulates TV radio waves of MHZ to 1 GHz and outputs a luminance signal Y and color difference signals RY and BY having a band of approximately 4.5 MHz, and operates at a sampling frequency of 13.5 MHz 6 It is composed of a 10-bit A / D conversion circuit (52), an image memory (54), an arithmetic circuit (56), a D / A conversion circuit (58), a video output circuit (60) and a CRT (62).

【0004】図9は本件出願人の提案になるデイジタル
TV用混成集積回路装置(以下、単に混成集積回路装置
と称する)を示す。この混成集積回路装置(70)は図8の
破線内のA/D変換回路(52)、画像メモリ(54)、演算回
路(56)、D/A変換回路(58)を混成集積回路化したもの
である。
FIG. 9 shows a hybrid integrated circuit device for digital TV (hereinafter simply referred to as a hybrid integrated circuit device) proposed by the present applicant. In this hybrid integrated circuit device (70), the A / D conversion circuit (52), the image memory (54), the arithmetic circuit (56), and the D / A conversion circuit (58) in the broken line of FIG. It is a thing.

【0005】図9を参照すると、二枚の絶縁金属基板(7
0)(72)には、放熱特性および加工性を考慮して、表面を
陽極酸化処理した略2mm厚のアルミニウムが使用され
る。そして、この絶縁金属基板の所定位置に捨孔を形成
した後、ポリイミド樹脂等の接着性を有する熱硬化性絶
縁樹脂と略35μm厚の銅箔とのクラッド材をホットプ
レスし、この銅箔をホトエッチングする等して、パッ
ド、導電路等が所定パターンに形成される。なお、前記
熱硬化性絶縁樹脂はホットプレス後略35μm厚の絶縁
層となる。
Referring to FIG. 9, two insulating metal substrates (7
For (0) and (72), aluminum having a thickness of about 2 mm, whose surface is anodized, is used in consideration of heat dissipation characteristics and workability. Then, after forming a dead hole at a predetermined position of this insulating metal substrate, a clad material of a thermosetting insulating resin having adhesiveness such as a polyimide resin and a copper foil having a thickness of about 35 μm is hot-pressed to remove this copper foil. By photo-etching or the like, pads, conductive paths, etc. are formed in a predetermined pattern. The thermosetting insulating resin becomes an insulating layer having a thickness of about 35 μm after hot pressing.

【0006】この後、絶縁金属基板の前記捨孔のブリッ
ジ部を切断して、二枚の絶縁金属基板(70)(72)に分割す
ることにより、ブリッジ部において相互の回路パターン
が導電路で接続された二枚の絶縁金属基板が得られる。
A/D変換回路(52)、画像メモリ(54)、演算回路(56)、
D/A変換回路(58)を構成する集積回路素子等の半導体
素子はチップ形状で所定のパッドに銀ペースト等を使用
して固着され、チップ抵抗等の異型部品は半田固着され
る(何れも図9には示されていない)。
After that, the bridge portion of the dead hole of the insulating metal substrate is cut and divided into two insulating metal substrates (70) and (72) so that mutual circuit patterns are conductive paths in the bridge portion. Two connected insulating metal substrates are obtained.
A / D conversion circuit (52), image memory (54), arithmetic circuit (56),
A semiconductor element such as an integrated circuit element constituting the D / A conversion circuit (58) is fixed in a chip shape by using silver paste or the like on a predetermined pad, and atypical parts such as a chip resistor are fixed by soldering (both are (Not shown in Figure 9).

【0007】そして、この回路素子を実装した絶縁金属
基板(70)(72)を接着性樹脂を使用して金属製のケース(7
4)および蓋(76)で封止し、さらにこれら全体構造が、樹
脂接着部を覆うような枠形状のシールドケース(78)に挿
入される。
The insulating metal substrate (70) (72) on which this circuit element is mounted is made of a metal case (7) using an adhesive resin.
4) and the lid (76) are sealed, and the entire structure is inserted into a frame-shaped shield case (78) that covers the resin adhesive portion.

【0008】[0008]

【発明が解決しようとする課題】従来のデイジタルTV
用混成集積回路装置は小型、安価にデイジタルTVを提
供できるものの、アンテナが付属するTVセット等、特
殊構造のTVセットでは画像の乱れが確認された。そし
て、本件発明者等の基礎的研究により、この原因が混成
集積回路装置内部で発生するノイズの高調波成分が外部
リードおよび絶縁金属基板とシールドケースとの僅かな
接着間隙から漏洩し、アンテナ回路に混入することに原
因することが解明された。即ち、絶縁金属基板と金属製
ケースの接着間隙、絶縁金属基板とシールドケースの間
隙は発生ノイズ、特に問題となるノイズの波長を漏洩さ
せるに充分なスパンを有していることが解明された。
[Problems to be Solved by the Invention] Conventional digital TV
Although the hybrid integrated circuit device can provide a digital TV at a small size and at a low cost, image distortion has been confirmed in a TV set with a special structure such as a TV set with an antenna. According to the basic research conducted by the inventors of the present invention, the cause is that harmonic components of noise generated inside the hybrid integrated circuit device leak from the slight gap between the external lead and the insulating metal substrate and the shield case, and the antenna circuit It has been clarified that it is caused by being mixed into the. That is, it has been clarified that the adhesive gap between the insulating metal substrate and the metal case and the gap between the insulating metal substrate and the shield case have sufficient spans for leaking the generated noise, particularly the wavelength of the noise in question.

【0009】また、面材料を箱状にプレス加工したシー
ルドケースの重畳部からノイズが漏洩することも知られ
たが、シールドケースの重畳部を連続溶接することはコ
スト上昇の問題があった。そこで、本発明の目的はシー
ルドケースの重畳部の間隙からのノイズ漏洩を防止した
安価な混成集積回路構造を提供することにある。
Further, it has been known that noise leaks from the overlapping portion of the shield case in which the surface material is pressed into a box shape, but continuous welding of the overlapping portion of the shield case causes a problem of cost increase. Therefore, an object of the present invention is to provide an inexpensive hybrid integrated circuit structure which prevents noise leakage from the gap between the overlapping portions of the shield case.

【0010】[0010]

【課題を解決するための手段】本発明は、外部リードが
設けられる面を除く全ての面を覆うシールドケースの重
畳部を所定の間隔でスポット溶接したことを主要な特徴
とする。
SUMMARY OF THE INVENTION The main feature of the present invention is that spots are welded at predetermined intervals to overlapping portions of a shield case that covers all surfaces except the surface on which external leads are provided.

【0011】[0011]

【作用】外部リードが設けられる面を除く全ての面をシ
ールドケースで覆うためシールドケースと混成集積回路
装置との間隙からのノイズ漏洩が防止される。また、シ
ールドケースの重畳部を所定の間隔でスポット溶接した
ため連続溶接に比較して低コストでシールドケースの接
合が行える。さらに、問題となるノイズを漏洩させない
間隔でスポット溶接したため重畳部からのノイズ漏洩を
充分に防止できる。
Since all the surfaces except the surface on which the external leads are provided are covered with the shield case, noise leakage from the gap between the shield case and the hybrid integrated circuit device is prevented. Further, since the overlapping portions of the shield case are spot welded at a predetermined interval, the shield case can be joined at a lower cost than in continuous welding. Furthermore, since spot welding is performed at intervals that do not leak noise, which is a problem, noise leakage from the overlapping portion can be sufficiently prevented.

【0012】[0012]

【実施例】図1乃至図7を参照して本発明のデイジタル
TV用混成集積回路装置(以下、再び混成集積回路装置
と称する)を説明する。なお、図1は本発明の一実施例
の等価回路図であり、従来例の説明に供した図8の破線
内の回路に相当するものである。また、図2は一方の集
積回路基板の斜視図、図3は一実施例の断面図、図4は
一実施例の斜視図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A hybrid integrated circuit device for a digital TV (hereinafter referred to as a hybrid integrated circuit device) of the present invention will be described with reference to FIGS. 1 is an equivalent circuit diagram of an embodiment of the present invention, and corresponds to the circuit within the broken line of FIG. 8 used in the description of the conventional example. 2 is a perspective view of one integrated circuit board, FIG. 3 is a sectional view of one embodiment, and FIG. 4 is a perspective view of one embodiment.

【0013】図1を参照すると、本実施例ではA/D変
換回路(12)、画像メモリ(14)、演算回路(16)、D/A変
換回路(18)が混成集積回路装置(10)として二枚の絶縁金
属基板上に分割形成され、その二枚の絶縁金属基板を対
向配置し、混成集積回路化した回路を外部回路から遮断
してノイズ漏洩防止が図られる。また、電源端子を除く
全ての外部リード端子と混成集積回路装置の内部回路間
にはチップ状のフェライトビーズコア(36)、あるいは抵
抗(38)が挿入され、混成集積回路装置の外部リード端子
からのノイズ漏洩防止も図られる。
Referring to FIG. 1, in this embodiment, an A / D conversion circuit (12), an image memory (14), an arithmetic circuit (16), and a D / A conversion circuit (18) are a hybrid integrated circuit device (10). As a result, it is divided and formed on two insulating metal substrates, the two insulating metal substrates are arranged to face each other, and a circuit formed into a hybrid integrated circuit is cut off from an external circuit to prevent noise leakage. In addition, a chip-shaped ferrite bead core (36) or a resistor (38) is inserted between all external lead terminals except the power supply terminal and the internal circuit of the hybrid integrated circuit device. It is also possible to prevent noise leakage.

【0014】図2および図3を参照すると、二枚の絶縁
金属基板(20)(22)には、放熱特性および加工性を考慮し
て、表面を陽極酸化処理した(酸化膜を符号24で示す)
略2mm厚のアルミニウムが使用される。そして、この
絶縁金属基板の所定位置に捨孔を形成した後、ポリイミ
ド樹脂等の接着性を有する熱硬化性絶縁樹脂と略35μ
m厚の銅箔とのクラッド材をホットプレスし、この銅箔
をホトエッチングする等してパッド(26)、導電路(28)等
が所定パターンに形成される。
Referring to FIGS. 2 and 3, the two insulating metal substrates (20) and (22) are anodized on their surfaces in consideration of heat dissipation characteristics and workability (the oxide film is denoted by reference numeral 24). Show)
Aluminum of approximately 2 mm thickness is used. Then, after forming a dead hole at a predetermined position of this insulating metal substrate, a thermosetting insulating resin having an adhesive property such as a polyimide resin is used to form approximately 35 μm.
A pad material (26), a conductive path (28), etc. are formed in a predetermined pattern by hot pressing a clad material with an m-thick copper foil and photoetching the copper foil.

【0015】接地用外部リード端子が固着されるパッド
およびその導電路(28)は絶縁金属基板(20)(22)の両サイ
ドに形成され、本実施例の混成集積回路装置を搭載する
マザー基板上に形成された接地パターンにより、混成集
積回路装置の接地回路と後述するシールドケースの接地
ピンが低インピーダンスで接続される。また、導電路(2
8)の線幅は銅箔厚に等しい略35μmと微細であるた
め、電荷集中によるノイズ発生を防止するため、滑らか
な曲線模様に形成される。さらに、導電路パターンが鋭
角となる個所はアールが付与される。なお、前記熱硬化
性絶縁樹脂はホットプレス後略35μm厚の絶縁層(24)
となる。
A pad to which an external lead terminal for grounding is fixed and its conductive path (28) are formed on both sides of the insulating metal substrates (20) and (22), and a mother substrate on which the hybrid integrated circuit device of this embodiment is mounted. The ground pattern formed above connects the ground circuit of the hybrid integrated circuit device and the ground pin of the shield case described later with low impedance. Also, the conductive path (2
Since the line width of 8) is as fine as about 35 μm, which is equal to the copper foil thickness, it is formed in a smooth curved pattern in order to prevent noise generation due to electric charge concentration. Further, a radius is given to a portion where the conductive path pattern has an acute angle. In addition, the thermosetting insulating resin is an insulating layer (24) having a thickness of approximately 35 μm after hot pressing.
Becomes

【0016】この後、絶縁金属基板の前記捨孔のブリッ
ジ部を切断して、二枚の絶縁金属基板(20)(22)に分割す
ることにより、ブリッジ部において相互の回路パターン
が導電路で接続された二枚の絶縁金属基板(20)(22)が得
られる。しかしながら、二枚の絶縁金属基板(20)(22)を
個々に形成し適宜の接続手段によりそれぞれの回路を接
続することも可能である。
After that, the bridge portion of the dead hole of the insulating metal substrate is cut and divided into two insulating metal substrates (20) and (22), so that mutual circuit patterns are conductive paths in the bridge portion. Two connected insulating metal substrates (20) (22) are obtained. However, it is also possible to individually form the two insulating metal substrates (20) and (22) and connect the respective circuits by appropriate connecting means.

【0017】二枚の絶縁金属基板(20)(22)上に形成され
た所定のパッド(26)に前記したA/D変換回路(12)、画
像メモリ(14)、演算回路(16)、D/A変換回路(18)を構
成する集積回路素子等の半導体素子、チップ抵抗、チッ
プコンデンサ等の回路素子および端子ノイズを抑制する
フェライトビーズコア(36)あるいは抵抗(38)等の異型部
品が半田等のろう材で固着される。
A predetermined pad (26) formed on the two insulating metal substrates (20) and (22) has the above-mentioned A / D conversion circuit (12), image memory (14), arithmetic circuit (16), Semiconductor elements such as integrated circuit elements constituting the D / A conversion circuit (18), circuit elements such as chip resistors and chip capacitors, and atypical parts such as ferrite bead cores (36) or resistors (38) for suppressing terminal noise are It is fixed with a brazing material such as solder.

【0018】そして、所定の回路をワイアボンディング
接続し、外部リード(30)を半田固着した二枚の絶縁金属
基板(20)(22)を接着性シートを使用して、その実装素子
が対向するように、枠形状の樹脂ケース(32)で固着、一
体化する。二枚の絶縁金属基板(20)(22)の回路接続部
(折曲げ部)は図3に示されるように二枚の絶縁金属基
板(20)(22)の終端部内に配置される構造となる。
Then, a predetermined circuit is connected by wire bonding, and the two insulating metal substrates (20) and (22) to which the external leads (30) are fixed by soldering are mounted using an adhesive sheet so that their mounting elements face each other. As described above, the frame-shaped resin case (32) is fixed and integrated. As shown in FIG. 3, the circuit connecting portions (folded portions) of the two insulating metal substrates (20) and (22) are arranged in the end portions of the two insulating metal substrates (20) and (22). Become.

【0019】図5は本発明に特徴的なシールドケースの
一例の展開図である。本発明で使用されるシールドケー
ス(40)は混成集積回路装置の外部リード(30)が設けられ
る面を除く全ての面を覆う構造であるため、プレス加工
の難易を考慮して、二つの面材料を個別に蓋状にプレス
加工し、それらを重ね合わせた後、その重畳部(図4の
スポット溶接部(46)の面)を、発生ノイズの波長、特
に、問題となるノイズの波長の略1/10以下の間隔で
スポット溶接を行って、接合して箱状にされる。
FIG. 5 is a development view of an example of a shield case characteristic of the present invention. The shield case (40) used in the present invention has a structure that covers all surfaces of the hybrid integrated circuit device except the surface on which the external leads (30) are provided. After pressing the materials individually into a lid shape and overlapping them, the overlapping part (the surface of the spot welded part (46) in Fig. 4) is used to determine the wavelength of the generated noise, especially the wavelength of the noise in question. Spot welding is performed at intervals of about 1/10 or less, and they are joined to form a box.

【0020】厚さが10mmに満たないシールドケース
(40)の重畳部の連続、完全溶接は接合コストが高く、ま
た作業性が低いのに対し、シールドケース(40)の重畳部
をスポット溶接する本発明によれば、接合コストを低下
させることができ、ノイズ漏洩も充分に防止できる。
Shield case whose thickness is less than 10 mm
Continuation of the overlapping portion of (40), complete welding has a high joining cost, and workability is low, whereas the present invention for spot welding the overlapping portion of the shield case (40) reduces the joining cost. It is possible to prevent noise leakage sufficiently.

【0021】このシールドケース(40)は、前記したよう
に、混成集積回路装置を搭載するマザー基板上に形成し
た接地パターンにより、混成集積回路の接地回路とこの
シールドケース(40)を低インピーダンスで接続するため
の接地ピン(42)を備えると共に絶縁金属基板(20)(22)か
らの放熱を妨げないように複数の放熱孔(44)が形成され
る。実施例は円形の放熱孔を示すが、長径が、問題とな
るノイズの波長の略1/10以下であれば任意の形状と
することができる。本実施例では放熱孔(44)がシールド
ケース(40)の側面にマトリクス状に形成されているが、
絶縁金属基板(20)(22)上に搭載される回路素子の位置関
係を考慮して、チドリ配置あるいは放熱が必要な領域に
部分的に形成してもよい。
As described above, the shield case (40) has a low impedance between the ground circuit of the hybrid integrated circuit and the shield case (40) by the ground pattern formed on the mother board on which the hybrid integrated circuit device is mounted. A plurality of heat dissipation holes (44) are formed so as to include a ground pin (42) for connection and not to interfere with heat dissipation from the insulating metal substrates (20) and (22). Although the embodiment shows a circular heat dissipation hole, any major shape can be used as long as its major axis is about 1/10 or less of the wavelength of noise in question. In this embodiment, the heat dissipation holes (44) are formed in a matrix on the side surface of the shield case (40).
In consideration of the positional relationship of the circuit elements mounted on the insulating metal substrates (20) and (22), they may be formed in a puddle arrangement or partially formed in a region where heat dissipation is required.

【0022】図6および図7に任意の外部リードで測定
した従来例と実施例の高調波ノイズ特性を示す。同図は
中心周波数500MHZ、150KHZ/div、10d
b/divである。同図に示されるように、従来の混成
集積回路装置はノイズレベルが−20dbに達するに対
して本発明の混成集積回路装置では−40db以下が達
成される。なお、測定条件は1KΩの抵抗を測定すべき
端子と接地間に接続し、この抵抗に流れる電流を5mV
/mAの効率で変換したものである。
FIG. 6 and FIG. 7 show the harmonic noise characteristics of the conventional example and the example, which were measured with an arbitrary external lead. The figure shows center frequencies of 500 MHz, 150 KHz / div and 10 d.
b / div. As shown in the figure, the noise level of the conventional hybrid integrated circuit device reaches -20db, whereas the noise level of -40db or less is achieved in the hybrid integrated circuit device of the present invention. The measurement condition is that a resistance of 1 KΩ is connected between the terminal to be measured and ground, and the current flowing through this resistance is 5 mV.
It is converted at an efficiency of / mA.

【0023】[0023]

【発明の効果】以上述べたように本発明の混成集積回路
装置は、外部リードが設けられる面を除く全ての面をシ
ールドケースで覆ったため絶縁金属基板とシールドケー
スとの間隙からのノイズ漏洩が防止されるばかりか、シ
ールドケースに問題となるノイズを通過させないサイズ
の放熱孔を形成したため放熱特性が損なわれない。ま
た、シールドケースの重畳部を問題となるノイズの波長
の略1/10以下の間隔でスポット溶接したため接合コ
ストを上昇させることなく、漏洩ノイズを充分に抑制す
ることができる。
As described above, in the hybrid integrated circuit device of the present invention, noise leakage from the gap between the insulating metal substrate and the shield case is prevented because all the surfaces except the surface on which the external leads are provided are covered with the shield case. In addition to being prevented, the heat dissipation characteristics are not impaired because the heat dissipation holes are formed in the shield case in a size that does not allow problematic noise to pass through. Further, since the superposed portion of the shield case is spot-welded at intervals of about 1/10 or less of the wavelength of noise in question, leakage noise can be sufficiently suppressed without increasing the joining cost.

【0024】また、電源を除く全ての外部リード端子と
内部回路間にチップ形状のフェライトビースコアあるい
は抵抗を挿入したため外部リードからのノイズ漏洩が防
止される。また、全ての集積回路素子の接地回路をそれ
ぞれの集積回路素子の近傍であって、パターンインピー
ダンスが低い個所で絶縁金属基板に接続したため集積回
路素子の動作電位が安定してノイズ発生が防止される。
Further, since chip-shaped ferrite beads cores or resistors are inserted between all the external lead terminals except the power source and the internal circuit, noise leakage from the external leads is prevented. Further, since the ground circuits of all the integrated circuit elements are connected to the insulating metal substrate in the vicinity of each integrated circuit element and where the pattern impedance is low, the operating potential of the integrated circuit element is stable and noise generation is prevented. ..

【0025】また、二枚の絶縁金属基板の少なくとも両
サイドに接地パターンおよび外部リード端子を形成した
ため混成集積回路装置を搭載するマザー基板上におい
て、シールドケースが低インピータンスでその接地パタ
ーンに接続され、シールドケースの電位が安定してノイ
ズ発生が防止される。さらにまた、回路パターンを滑ら
かに形成したため電荷集中によるノイズ発生が防止され
る。
Since the ground pattern and the external lead terminals are formed on at least both sides of the two insulating metal substrates, the shield case is connected to the ground pattern with low impedance on the mother substrate on which the hybrid integrated circuit device is mounted. , The potential of the shield case is stable and noise generation is prevented. Furthermore, since the circuit pattern is formed smoothly, noise generation due to electric charge concentration is prevented.

【0026】[0026]

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の等価回路図。FIG. 1 is an equivalent circuit diagram of an embodiment of the present invention.

【図2】本発明の集積回路基板の斜視図。FIG. 2 is a perspective view of an integrated circuit board of the present invention.

【図3】本発明の一実施例の断面図。FIG. 3 is a sectional view of an embodiment of the present invention.

【図4】本発明の一実施例の斜視図。FIG. 4 is a perspective view of an embodiment of the present invention.

【図5】本発明のシールドケースの展開図。FIG. 5 is a development view of the shield case of the present invention.

【図6】従来例のノイズ特性図。FIG. 6 is a noise characteristic diagram of a conventional example.

【図7】本発明のノイズ特性図。FIG. 7 is a noise characteristic diagram of the present invention.

【図8】ディジタルTVの等価回路図。FIG. 8 is an equivalent circuit diagram of a digital TV.

【図9】従来例の斜視図。FIG. 9 is a perspective view of a conventional example.

【符号の説明】[Explanation of symbols]

10 混成集積回路装置 12 A/D変換回路 14 画像メモリ 16 演算回路 18 D/A変換回路 20 絶縁金属基板 22 絶縁金属基板 24 酸化膜 26 パッド 28 導電路 30 外部リード 32 ケース 36 フェライトビーズコア 38 抵抗 40 シールドケース 42 接地ピン 44 放熱孔 10 hybrid integrated circuit device 12 A / D conversion circuit 14 image memory 16 arithmetic circuit 18 D / A conversion circuit 20 insulating metal substrate 22 insulating metal substrate 24 oxide film 26 pad 28 conductive path 30 external lead 32 case 36 ferrite bead core 38 resistance 40 Shield Case 42 Ground Pin 44 Heat Dissipation Hole

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 絶縁金属基板に形成した回路パターン上
にA/D変換回路、画像メモリ、演算回路、D/A変換
回路等のディジタルTVに必要な回路要素の少なくとも
1つを集積化した集積回路基板と、前記絶縁金属基板上
に形成した回路要素を密封封止するケース材と、外部リ
ードが設けられる面を除く全ての面を覆うシールドケー
スとを備え、 前記シールドケースの重畳部を所定の間隔でスポット溶
接したことを特徴とする混成集積回路装置。
1. An integrated circuit in which at least one circuit element required for a digital TV, such as an A / D conversion circuit, an image memory, an arithmetic circuit, and a D / A conversion circuit, is integrated on a circuit pattern formed on an insulating metal substrate. A circuit board, a case material for hermetically sealing the circuit elements formed on the insulating metal substrate, and a shield case that covers all surfaces except the surface on which the external leads are provided, and the overlapping portion of the shield case is predetermined. A hybrid integrated circuit device characterized in that spot welding is performed at intervals of.
【請求項2】 前記シードルケースのスポット溶接間隔
を、問題となるノイズの波長の略1/10以下としたこ
とを特徴とする請求項1の混成集積回路装置。
2. The hybrid integrated circuit device according to claim 1, wherein the spot welding interval of the cider case is set to about 1/10 or less of a wavelength of noise in question.
【請求項3】 前記基板上に形成された電源を除く全て
の外部リード端子と内部回路間にチップ状のフェライト
ビーズコアおよび/あるいはチップ抵抗を配置したこと
を特徴とする請求項1の混成集積回路。
3. The hybrid integrated circuit according to claim 1, wherein chip-shaped ferrite bead cores and / or chip resistors are arranged between all external lead terminals except the power source formed on the substrate and internal circuits. circuit.
【請求項4】 前記A/D変換回路、画像メモリ、演算
回路、D/A変換回路等の集積回路素子の接地回路をそ
れぞれの集積回路素子の近傍であって、パターンインピ
ーダンスが比較的低い個所で絶縁金属基板に接続したこ
とを特徴とする請求項1の混成集積回路装置。
4. A ground circuit of an integrated circuit device such as the A / D conversion circuit, the image memory, the arithmetic circuit, the D / A conversion circuit, etc. is located in the vicinity of each integrated circuit device and has a relatively low pattern impedance. 2. The hybrid integrated circuit device according to claim 1, wherein the hybrid integrated circuit device is connected to the insulating metal substrate by.
JP27868291A 1991-09-30 1991-09-30 Hybrid integrated circuit device Expired - Lifetime JP2703434B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27868291A JP2703434B2 (en) 1991-09-30 1991-09-30 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27868291A JP2703434B2 (en) 1991-09-30 1991-09-30 Hybrid integrated circuit device

Publications (2)

Publication Number Publication Date
JPH05206673A true JPH05206673A (en) 1993-08-13
JP2703434B2 JP2703434B2 (en) 1998-01-26

Family

ID=17600706

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27868291A Expired - Lifetime JP2703434B2 (en) 1991-09-30 1991-09-30 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JP2703434B2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5591196U (en) * 1978-12-20 1980-06-24
JPS59149697U (en) * 1983-03-24 1984-10-06 シャープ株式会社 switching circuit parts
JPS6433796U (en) * 1987-08-21 1989-03-02

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5591196U (en) * 1978-12-20 1980-06-24
JPS59149697U (en) * 1983-03-24 1984-10-06 シャープ株式会社 switching circuit parts
JPS6433796U (en) * 1987-08-21 1989-03-02

Also Published As

Publication number Publication date
JP2703434B2 (en) 1998-01-26

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