JPH0821642B2 - Package for high frequency devices - Google Patents

Package for high frequency devices

Info

Publication number
JPH0821642B2
JPH0821642B2 JP62097196A JP9719687A JPH0821642B2 JP H0821642 B2 JPH0821642 B2 JP H0821642B2 JP 62097196 A JP62097196 A JP 62097196A JP 9719687 A JP9719687 A JP 9719687A JP H0821642 B2 JPH0821642 B2 JP H0821642B2
Authority
JP
Japan
Prior art keywords
signal line
package
substrate
conductor
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62097196A
Other languages
Japanese (ja)
Other versions
JPS63261859A (en
Inventor
文雄 宮川
敏一 竹之内
博之 酒井
文則 石塚
信夫 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Shinko Electric Industries Co Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd, Nippon Telegraph and Telephone Corp filed Critical Shinko Electric Industries Co Ltd
Priority to JP62097196A priority Critical patent/JPH0821642B2/en
Publication of JPS63261859A publication Critical patent/JPS63261859A/en
Publication of JPH0821642B2 publication Critical patent/JPH0821642B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、3GHz〜50GHzの超高周波数や高周波数で作
動させる半導体素子等の高周波用素子を収容する高周波
素子用パッケージに関する。
Description: TECHNICAL FIELD The present invention relates to a high-frequency element package that accommodates high-frequency elements such as semiconductor elements that operate at ultrahigh frequencies or high frequencies of 3 GHz to 50 GHz.

[従来の技術] 近時、情報処理装置の高性能高速化に伴い、これを構
成する半導体素子等の素子の高周波化が一段と進み、該
素子を収容する高周波特性に優れたパッケージの需要が
高まりつつある。
[Prior Art] In recent years, as the performance and speed of information processing devices have increased, the frequency of elements such as semiconductor elements has increased further, and the demand for packages with excellent high frequency characteristics that accommodate these elements has increased. It's starting.

この高周波用の素子を収容するパッケージとして、従
来、例えば実開昭61−86944号公報記載のものがある。
このパッケージは、金属基体上に切欠部を設けて、該切
欠部内部にメタライズ層からなる信号線路を備えたセラ
ミックの入出力端子取着部材を嵌着してなる。このパッ
ケージでは、その入出力端子取着部材を嵌着した切欠部
周囲の接地層に導通する金属基体が、セラミックの入出
力端子取着部材に備えた信号線路周囲を囲む同軸構造を
していて、金属基体からなるメタルウォールが入出力端
子取着部材中の信号線路を流れる信号が信号線路外部に
漏洩等するのを防止する。
As a package for accommodating this high frequency element, for example, there is a package described in Japanese Utility Model Laid-Open No. 61-86944.
In this package, a notch is provided on a metal substrate, and a ceramic input / output terminal attachment member having a signal line made of a metallized layer is fitted inside the notch. In this package, the metal base that conducts to the ground layer around the notch in which the input / output terminal attachment member is fitted has a coaxial structure surrounding the signal line provided in the ceramic input / output terminal attachment member. The metal wall made of a metal substrate prevents a signal flowing through the signal line in the input / output terminal attachment member from leaking to the outside of the signal line.

[発明が解決しようとする問題点] しかしながら、上述のパッケージにおいては、その製
造に際して、金属基体上に入出力端子取着部材嵌着用の
切欠部を削成するのに困難を極め、上述構造のパッケー
ジでは、近時の半導体素子の高密度実装化と入出力端子
の多端子化に対応不可能となった。また、上述のパッケ
ージでは、入出力端子取着部材周壁と切欠部内側面との
間を、予め入出力端子取着部材周壁に形成したメタライ
ズ層を介してろう付け等しなければならず、その製造に
多大な手数と時間を要した。
[Problems to be Solved by the Invention] However, in the above-described package, it is extremely difficult to form a notch for fitting the input / output terminal attachment member on the metal base during the manufacture thereof, With the package, it has become impossible to cope with the recent high-density mounting of semiconductor elements and the increase in the number of input / output terminals. Further, in the above-described package, the input / output terminal attaching member peripheral wall and the inner surface of the cutout portion must be brazed or the like via a metallized layer formed in advance on the input / output terminal attaching member peripheral wall, and the production thereof is required. It took a lot of trouble and time.

本発明は、かかる問題点を解決するためのもので、そ
の目的は、高周波用の半導体素子等の素子の高密度実装
化と入出力端子の多端子化に対応可能で、しかも製造容
易な、超高周波用や高周波用の半導体素子等の素子を収
容する高周波素子用パッケージを提供することにある。
The present invention is to solve such a problem, and an object thereof is to be compatible with high-density mounting of elements such as semiconductor elements for high frequency and multi-terminals of input / output terminals, and easy to manufacture, An object is to provide a package for a high frequency element that accommodates elements such as ultra high frequency and high frequency semiconductor elements.

[問題点を解決するための手段] 上記目的を達成するために、本発明の高周波素子用パ
ッケージは、高周波素子を取り付ける絶縁体からなる基
板に前記高周波素子を取り囲む絶縁体からなる枠体が積
層され、前記基板に複数本の信号線路が横に並べて備え
られてなる高周波素子用パッケージにおいて、前記基板
に前記複数本の信号線路の下方を連続して覆う接地層を
備え、前記枠体に前記複数本の信号線路の上方を連続し
て覆う接地層を備え、該上下の接地層に挟まれた前記信
号線路の左側と右側の前記基板と枠体とを構成する絶縁
体部分に複数の導体層を信号線路と平行か又はほぼ平行
に上下に複数段に並べて備え、前記絶縁体部分に前記導
体層を前記接地層に導通する導体線路を備えたことを特
徴としている。
[Means for Solving the Problems] In order to achieve the above object, in the high-frequency device package of the present invention, a frame body made of an insulator surrounding the high-frequency device is laminated on a substrate made of an insulator to which the high-frequency device is attached. In the package for a high-frequency device, in which a plurality of signal lines are provided side by side on the substrate, the substrate is provided with a ground layer that continuously covers the lower side of the plurality of signal lines, and the frame body is provided with the ground layer. A plurality of conductors are provided in an insulator portion that includes a ground layer that continuously covers the upper portions of the plurality of signal lines, and that sandwiches the upper and lower ground layers and that forms the substrate and the frame on the left and right sides of the signal line. It is characterized in that the layers are arranged in a plurality of layers vertically in parallel or substantially parallel to the signal line, and a conductor line for conducting the conductor layer to the ground layer is provided in the insulator portion.

[作用] 本発明の高周波素子用パッケージにおいては、各信号
線路の上方とその下方とを、シールド効果を持つ接地層
で隙間なく覆っている。
[Operation] In the high-frequency device package of the present invention, the upper side and the lower side of each signal line are covered with a ground layer having a shield effect without a gap.

また、上下の接地層に挟まれた各信号線路の左側部分
と右側部分とを、上下に複数段に並べて備えた複数の導
体層であって、接地層に導体線路を介して導通されたシ
ールド効果を持つ複数の導体層で密に囲んでいる。
Further, a plurality of conductor layers each having a left side portion and a right side portion of each signal line sandwiched between the upper and lower ground layers arranged side by side in a plurality of stages, the shield being electrically connected to the ground layer via the conductor lines. It is densely surrounded by multiple conductor layers that have an effect.

さらに、上下の接地層に挟まれた各信号線路の左側部
分と右側部分とを、接地層に導通するシールド効果を持
つ導体線路で囲んでいる。
Further, the left side portion and the right side portion of each signal line sandwiched between the upper and lower ground layers are surrounded by a conductor line having a shield effect that conducts to the ground layer.

換言すれば、各信号線路の上下とその左右を接地層と
導体層と導体線路とからなるシールド壁で隙間少なく密
に囲んでいて、各信号線路を同軸線路に極めて近い擬似
同軸線路に形成している。
In other words, the upper and lower sides and the left and right sides of each signal line are densely surrounded by a shield wall composed of a ground layer, a conductor layer, and a conductor line with a small gap, and each signal line is formed into a pseudo coaxial line extremely close to the coaxial line. ing.

そのため、各信号線路に伝わる高周波信号が他の信号
線路に混入するのを、上記隙間の少ないシールド効果の
高いシールド壁で確実に防止できる。そして、各信号線
路間の絶縁度を大幅に高めることができる。
Therefore, it is possible to reliably prevent the high-frequency signal transmitted to each signal line from mixing into another signal line by the shield wall having a small shield effect and a high shield effect. And the insulation degree between each signal line can be improved significantly.

また、信号線路とその周囲のシールド壁を構成する接
地層や導体層や導体線路との間の距離、上下に複数段に
並べて備える導体層のピッチ、又は信号線路や導体層や
導体線路の幅やその厚さを大小に調整することにより、
信号線路の特性インピーダンスを一定値に容易かつ的確
にマッチングさせることができる。
Also, the distance between the signal line and the ground layer, the conductor layer, or the conductor line that constitutes the shield wall around the signal line, the pitch of the conductor layers arranged in a plurality of upper and lower layers, or the width of the signal line, the conductor layer, or the conductor line. By adjusting the thickness and its thickness,
The characteristic impedance of the signal line can be easily and accurately matched to a constant value.

また、上下の接地層に挟まれた基板と枠体とを構成す
る絶縁体部分に上下に複数段に並べて備える複数の導体
層の数を増やしたり、その上下に複数段に並べて備える
複数の導体層のピッチを挟めたりすることにより、上下
の接地層に挟まれた基板と枠体とを構成する絶縁体部分
のほぼ全体を接地電位に近づけることができる。そし
て、信号線路に伝わる高周波信号で信号線路周囲のリン
グ状をなす枠体部分や基板部分に生ずるリング共振の共
振幅を大幅に低減させることができる。そして、信号線
路周囲の枠体部分や基板部分に生ずるリング共振の影響
を受けて、信号線路の高周波特性が低下するのを確実に
防ぐことができる。
In addition, the number of a plurality of conductor layers arranged in a plurality of upper and lower layers in an insulator portion which constitutes the substrate and the frame body sandwiched between the upper and lower ground layers may be increased, or a plurality of conductors arranged in a plurality of upper and lower layers may be arranged. By sandwiching the pitch of the layers, it is possible to bring almost the entire insulator portion sandwiching the upper and lower ground layers, which constitutes the substrate and the frame, to the ground potential. Then, the resonance width of the ring resonance generated in the ring-shaped frame portion or the substrate portion around the signal line by the high frequency signal transmitted to the signal line can be significantly reduced. Then, it is possible to reliably prevent the high frequency characteristics of the signal line from being deteriorated due to the influence of the ring resonance generated in the frame portion or the substrate portion around the signal line.

[実施例] 次に、本発明の実施例につき、図面に従い説明する。
第1図および第2図は、本発明の高周波素子用パッケー
ジの好適な実施例を示し、第1図は該パッケージの斜視
図、第2図は該パッケージの信号線路部分の横断面図で
ある。図中において8は、絶縁体3である2枚の方形の
セラミックの板8a,8bを積層してなる半導体素子等の素
子を取り付ける基板である。この基板8の上部の板8aの
表面中央に、半導体素子等の素子を埋没させる埋没孔15
を透設する。そして、上記埋没孔15周囲の上部の板8aの
上面に、その外端が板8a周縁に達する帯状メタライズ層
からなる導体層7と、同じくその外端が板8a周縁に達す
る帯状メタライズ層からなる信号線路1とを交互に所定
間隔ずつあけてその隣合う各導体層7と各信号線路1と
が平行かまたはほぼ平行となるように放射状に複数本備
える。また、基板8の上記埋没孔15内部に露呈する下部
の板8bの上面中央に、半導体等の素子を取着するボンデ
ィング層9を備える。さらに、下部の板8bの上面周囲
に、上部の板8aの下面をくぐり抜けてその外端が板8b周
縁に達する帯状メタライズ層からなる導体層7を、上記
の上部の板8aの上面に備えた各信号線路1と平行かまた
はほぼ平行に、かつ、上部の板8aの上面に備えた各導体
層7の直下に配置させて、所定間隔ずつあけて放射状に
複数本備える。また、基板8の下面全体に、その周縁が
基板8周縁に達する接地層5を備える。さらに、2枚の
ほぼ方形枠状をした絶縁体3であるセラミックの枠板12
a,12bを積層してなる半導体素子等の素子を取り囲む枠
体12を設けて、該枠体12を上記の基板8の上面に積層
し、基板8の上面周囲に放射状に備えた各信号線路1と
各導体層7の中途部を枠体12で覆う。そして、枠体12の
内側に半導体素子等の素子を収容するキャビティ10を形
成する。また、上記の枠体12の下部の枠板12bの上面周
囲に、上部の枠板12aの下面をくぐり抜けて枠板12bの内
外の周縁に達する帯状メタライズ層からなる導体層7
を、基板8の上面に備えた各信号線路1と平行かまたは
ほぼ平行に、かつ、基板8の上面に備えた各導体層7の
直上に配置させて、所定間隔ずつあけて複数本放射状に
備える。また、枠体12の上面に、封止キャップ(図示せ
ず。)を被着するその周縁が枠体12の内外の周縁に達す
る接地層5を兼ねたメタライズ層13を備える。さらに、
基板8の周囲側面に、上部の板8aの上面に備えた各導体
層7外端とその直下の下部の板8bの上面に備えた各導体
層7外端と基板8下面の接地層5周縁との間を電気的に
導通する帯状のメタライズ層13を所定間隔ずつあけて複
数本備える。また、枠体12の内外の周囲側面に、枠体12
の上面の接地層5の内外の周縁と下部の枠板12bの上面
に備えた内外の各導体層7外端とその直下の基板8の上
部の板8aの上面に備えた各導体層7表面との間を電気的
に導通する帯状のメタライズ層13をそれぞれ所定間隔ず
つあけて複数本備える。さらに、基板8と枠体12を積層
してなるパッケージ2外側周囲の4隅の各側面14に、該
各側面14に露出した基板8や枠体12の内部またはその表
面に備えた各導体層7外端と接地層5周縁との間を電気
的に導通する幅広な帯状のメタライズ層13をそれぞれ備
える。また、方形枠状の枠体12外側周囲の基板8の上面
に露出した各信号線路1端部に入出力用端子16をそれぞ
れろう付けする。第1図および第2図のパッケージ2は
以上の構成からなり、その製造に際しては、例えば、表
面に信号線路1、導体層7および接地層5等を形成する
導体ペーストを塗布した板8a,8bおよび枠体12a,12b用の
各セラミックスグリーンシートを積層して形成したパッ
ケージ部材を一体に焼成して製造する。また、導体層7
を接地層5等に電気的に導通するメタライズ層13は、板
8a,8bおよび枠板12a,12b用の各セラミックグリーンシー
トを積層して形成したパッケージ部材の内外の周囲側面
にメタライズ層13用の導体ペーストをスクリーン印刷等
により塗布した後、該パッケージ部材を一体に焼成して
パッケージ2の内外の周囲側面に備えるか、または、板
8a,8bおよび枠板12a,12b用のセラミックグリーンシート
に、内周面に導体ペーストを塗布したスルーホールを形
成しておき、セラミックグリーンシートを板8a,8bおよ
び枠板12a,12b用に裁断する際に、上記スルーホールを
跨いでセラミックグリーンシートを裁断して、板8a,8b
および枠板12a,12b用の各セラミックグリーンシートの
内外の周囲側面に、その内周面に導体ペーストを塗布し
た断面半円状の切り欠き13aを備え、該切り欠き13aを備
えた板8a,8bおよび枠板12a,12b用の各セラミックグリー
ンシートを積層して形成したパッケージ部材を一体に焼
成して、パッケージ2の内外の周囲側面に帯状のメタラ
イズ層13を備えるようにする。
[Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.
1 and 2 show a preferred embodiment of the high-frequency device package of the present invention. FIG. 1 is a perspective view of the package, and FIG. 2 is a cross-sectional view of a signal line portion of the package. . In the figure, reference numeral 8 is a substrate on which an element such as a semiconductor element, which is a laminate of two rectangular ceramic plates 8a and 8b as the insulator 3, is mounted. At the center of the surface of the upper plate 8a of the substrate 8, a buried hole 15 for burying a device such as a semiconductor device is buried.
Through. Then, on the upper surface of the upper plate 8a around the buried hole 15, a conductor layer 7 having a strip-shaped metallized layer whose outer end reaches the peripheral edge of the plate 8a and a strip-shaped metallized layer having its outer end reaching the peripheral edge of the plate 8a are formed. A plurality of signal lines 1 are provided in a radial pattern so that the conductor layers 7 adjacent to each other and the signal lines 1 are alternately arranged at predetermined intervals and are parallel or substantially parallel to each other. A bonding layer 9 for mounting an element such as a semiconductor is provided at the center of the upper surface of the lower plate 8b exposed inside the buried hole 15 of the substrate 8. Further, a conductor layer 7 composed of a band-shaped metallized layer that passes through the lower surface of the upper plate 8a and reaches the peripheral edge of the plate 8b around the upper surface of the lower plate 8b is provided on the upper surface of the upper plate 8a. A plurality of them are provided in parallel or substantially in parallel with each signal line 1 and immediately below each conductor layer 7 provided on the upper surface of the upper plate 8a, and are spaced at predetermined intervals. In addition, the ground layer 5 whose peripheral edge reaches the peripheral edge of the substrate 8 is provided on the entire lower surface of the substrate 8. Further, two ceramic frame plates 12 that are substantially rectangular frame-shaped insulators 3
A frame body 12 surrounding an element such as a semiconductor element formed by laminating a and 12b is provided, the frame body 12 is laminated on the upper surface of the substrate 8, and each signal line radially provided around the upper surface of the substrate 8 is provided. A frame 12 covers the intermediate portions of 1 and each conductor layer 7. Then, a cavity 10 for accommodating an element such as a semiconductor element is formed inside the frame body 12. In addition, a conductor layer 7 composed of a strip-shaped metallized layer that passes through the lower surface of the upper frame plate 12a and reaches the inner and outer peripheral edges of the frame plate 12b around the upper surface of the lower frame plate 12b of the frame body 12 described above.
Are arranged in parallel or substantially parallel to the respective signal lines 1 provided on the upper surface of the substrate 8 and directly above the respective conductor layers 7 provided on the upper surface of the substrate 8, and a plurality of them are radially arranged at predetermined intervals. Prepare Further, on the upper surface of the frame body 12, there is provided a metallization layer 13 which also serves as a ground layer 5 whose peripheral edge to which a sealing cap (not shown) is attached reaches inner and outer peripheral edges of the frame body 12. further,
On the peripheral side surface of the substrate 8, the outer ends of the conductor layers 7 provided on the upper surface of the upper plate 8a and the outer ends of the conductor layers 7 provided on the upper surface of the lower plate 8b immediately below and the periphery of the ground layer 5 on the lower surface of the substrate 8 A plurality of strip-shaped metallization layers 13 are provided at predetermined intervals so as to be electrically connected to each other. In addition, on the inner and outer peripheral side surfaces of the frame body 12, the frame body 12
The outer edges of the inner and outer conductor layers 7 provided on the upper and lower edges of the ground layer 5 and the upper surface of the lower frame plate 12b, and the surfaces of the conductor layers 7 provided on the upper surface of the upper plate 8a of the substrate 8 immediately thereunder. A plurality of strip-shaped metallized layers 13 are provided at predetermined intervals so as to be electrically connected to each other. Further, on each side surface 14 at four corners around the outside of the package 2 formed by stacking the substrate 8 and the frame body 12, each conductor layer provided inside or on the surface of the substrate 8 or the frame body 12 exposed on each side surface 14. A wide strip-shaped metallization layer 13 is provided to electrically connect the outer edge of the ground layer 7 and the periphery of the ground layer 5. Further, the input / output terminals 16 are brazed to the end portions of each signal line 1 exposed on the upper surface of the substrate 8 around the outer side of the rectangular frame-shaped frame 12. The package 2 shown in FIGS. 1 and 2 has the above-described structure. For manufacturing the package 2, for example, the plates 8a, 8b coated with the conductor paste for forming the signal line 1, the conductor layer 7, the ground layer 5 and the like on the surface thereof. A package member formed by stacking the ceramic green sheets for the frames 12a and 12b is integrally fired to manufacture. In addition, the conductor layer 7
The metallization layer 13 that electrically connects the grounding layer 5 to the ground layer 5 is a plate.
After the conductor paste for the metallization layer 13 is applied by screen printing or the like to the inner and outer peripheral side surfaces of the package member formed by laminating the ceramic green sheets for 8a, 8b and the frame plates 12a, 12b, the package member is integrated. To prepare for the inner and outer peripheral side surfaces of the package 2 by firing to
The ceramic green sheets for 8a, 8b and the frame plates 12a, 12b have through holes coated with the conductor paste on the inner peripheral surface, and the ceramic green sheets are cut for the plates 8a, 8b and the frame plates 12a, 12b. The ceramic green sheets are cut across the above-mentioned through holes, and the plates 8a, 8b are cut.
And on the inner and outer peripheral side surfaces of each of the ceramic green sheets for the frame plates 12a and 12b, a notch 13a having a semicircular cross section in which a conductor paste is applied to the inner peripheral surface thereof, and a plate 8a having the notch 13a, The package member formed by laminating the ceramic green sheets for 8b and the frame plates 12a, 12b is integrally fired to provide the strip-shaped metallization layer 13 on the inner and outer peripheral side surfaces of the package 2.

次に、その使用例を説明する。キャビティ10内部に半
導体素子等の素子(図示せず。)を収容して、その底部
の埋没孔15内部に露呈する基板8中のボンディング層9
表面に素子裏面を取着する。そして、素子中の各接続パ
ターンと枠体12内側のキャビティ10内周囲に露出した基
板8の上面の各信号線路1との間をワイヤで接続する。
次に、枠体12上面とキャビティ10上面とに亙って封止キ
ャップ(図示せず。)をかぶせて、該キャップ周囲を金
−錫材等を用いて枠体12上面のメタライズ層13に被着す
る。そして、枠体12外側の基板8の上面に露出した各信
号線路1端部にろう付けした各入出力用端子16に信号を
流せば、該各端子16を接続した基板8の上面の各信号線
路1に信号が流れて、各信号線路1にワイヤで接続した
キャビティ10内に封入した半導体素子等の素子に該信号
が伝わる。そして、その際に、該パッケージ2の各信号
線路1周囲の誘電体材料であるセラミックの絶縁体3の
基板8や枠体12の内部やその表面に各信号線路1と平行
かまたはほぼ平行に備えた擬似メタルウォール6を構成
する接地層5に導通する各導体層7が、各信号線路1を
流れる信号が基板8や枠体12を構成するセラミックの絶
縁体3を介し、あるいは空中を介してその外部に漏れた
り、その隣合う他の各信号線路1に混入したりするのを
的確に防止する。
Next, an example of its use will be described. A bonding layer 9 in the substrate 8 in which a device (not shown) such as a semiconductor device is housed inside the cavity 10 and exposed inside the buried hole 15 at the bottom thereof.
Attach the back side of the element to the front side. Then, each connection pattern in the element and each signal line 1 on the upper surface of the substrate 8 exposed around the inside of the cavity 10 inside the frame 12 are connected by wires.
Next, a sealing cap (not shown) is covered over the upper surface of the frame body 12 and the upper surface of the cavity 10, and the metallized layer 13 on the upper surface of the frame body 12 is covered with a gold-tin material or the like around the cap. Put on. Then, when a signal is sent to each input / output terminal 16 brazed to the end of each signal line 1 exposed on the upper surface of the substrate 8 outside the frame 12, each signal on the upper surface of the substrate 8 to which each terminal 16 is connected is connected. A signal flows through the line 1 and is transmitted to an element such as a semiconductor element enclosed in the cavity 10 connected to each signal line 1 by a wire. Then, at that time, the signal lines 1 are provided inside or on the surface of the substrate 8 or the frame body 12 of the ceramic insulator 3 which is the dielectric material around the signal lines 1 of the package 2 in parallel or substantially parallel to each signal line 1. Each conductor layer 7 that conducts to the ground layer 5 that constitutes the pseudo metal wall 6 is provided such that the signal flowing through each signal line 1 passes through the ceramic insulator 3 that constitutes the substrate 8 or the frame 12, or through the air. It is properly prevented from leaking to the outside and mixing into the other adjacent signal lines 1.

また、信号線路1の上方とその下方とを接地層5で広
く連続して覆っている。また、上下の接地層5で挟まれ
た信号線路1の左側部分と右側部分とに接地層5に導通
された複数の導体層7を上下に複数段に並べて備えてい
る。さらに、上下の接地層5で挟まれた信号線路1の左
側部分と右側部分とに接地層5に導通されたメタライズ
層13からなる導体線路を備えている。そして、信号線路
1が、同軸線路に極めて近い擬似同軸線路構造をしてい
る。そのため、信号線路1と接地層5や導体層7や前記
導体線路との間の距離、上下に複数段に並べて備える複
数の導体層7のピッチ、又は信号線路1や接地層5や導
体層7や前記導体線路の幅やその厚さを調整して、信号
線路1の特性インピーダンスを一定値に的確にマッチン
グさせることができる。そして、信号線路1に伝える高
周波信号の伝送損失を少なく抑えることができる。
Further, the ground line 5 widely and continuously covers the upper part and the lower part of the signal line 1. Further, a plurality of conductor layers 7 electrically connected to the ground layer 5 are arranged in a plurality of layers vertically on the left side portion and the right side portion of the signal line 1 sandwiched between the upper and lower ground layers 5. Further, a conductor line composed of a metallized layer 13 electrically connected to the ground layer 5 is provided on the left side portion and the right side portion of the signal line 1 sandwiched between the upper and lower ground layers 5. The signal line 1 has a pseudo coaxial line structure that is extremely close to the coaxial line. Therefore, the distance between the signal line 1 and the ground layer 5, the conductor layer 7, or the conductor line, the pitch of the plurality of conductor layers 7 arranged vertically in a plurality of stages, or the signal line 1, the ground layer 5, or the conductor layer 7. By adjusting the width and the thickness of the conductor line, the characteristic impedance of the signal line 1 can be accurately matched to a constant value. Then, it is possible to suppress the transmission loss of the high frequency signal transmitted to the signal line 1.

また、上下の接地層5で挟まれた信号線路1の左側部
分と右側部分とを上下に複数段に密に並べて備えた複数
の導体層7と該導体層7を接地層5に導通する上記導体
線路とからなるシールド効果の高いシールド壁で隙間少
なく密に囲んでいるため、信号線路1に伝わる高周波信
号の一部が、前記シールド壁の隙間を通り抜けて、他の
信号線路1に混入するのを確実に防止できる。
Further, a plurality of conductor layers 7 provided with the left side portion and the right side portion of the signal line 1 sandwiched between the upper and lower ground layers 5 densely arranged in a plurality of upper and lower stages, and the conductor layers 7 are electrically connected to the ground layer 5. Since it is closely surrounded by a shield wall having a high shield effect including a conductor line with a small gap, a part of the high frequency signal transmitted to the signal line 1 passes through the gap of the shield wall and is mixed with another signal line 1. Can be reliably prevented.

また、上下の接地層5に挟まれた基板8と枠体12とを
構成する絶縁体部分に複数の導体層7を上下に複数段に
密に並べて備えているため、その上下の接地層5に挟ま
れた基板8と枠体12とを構成する絶縁体部分のほぼ全体
を接地電位に近づけることができる。そして、信号線路
1に伝わる高周波信号で信号線路1周囲のリング状をな
す枠体12部分や基板8部分に生ずるリング共振の振幅幅
を大幅に低減させることができる。そして、信号線路1
周囲の枠体12部分や基板8部分に生ずるリング共振の悪
影響を受けて、信号線路1に伝える高周波信号の伝送特
性が低下するのを防止できる。
Further, since a plurality of conductor layers 7 are densely arranged vertically in a plurality of stages in an insulator portion which constitutes the substrate 8 and the frame body 12 sandwiched between the upper and lower ground layers 5, the upper and lower ground layers 5 are provided. It is possible to bring almost the entire insulator portion that constitutes the substrate 8 and the frame body 12 sandwiched between the two close to the ground potential. Then, the amplitude width of the ring resonance generated in the ring-shaped frame 12 portion and the substrate 8 portion around the signal line 1 by the high frequency signal transmitted to the signal line 1 can be significantly reduced. And the signal line 1
It is possible to prevent the transmission characteristics of the high-frequency signal transmitted to the signal line 1 from being deteriorated due to the adverse effect of ring resonance generated in the surrounding frame 12 portion and the substrate 8 portion.

なお、上述実施例のパッケージ2においては、その各
信号線路1に流す信号の周波数の高低に応じて、各信号
線路1周囲の絶縁体3の基板や枠体12の内部やその表面
に備える擬似メタルウォール6を構成する各導体層7と
各信号線路1との間の距離を、パッケージ2を構成する
絶縁体3である板8a,8bや枠板12a,12bの厚さを変える等
して調整して、各信号線路1を流れる信号が擬似メタル
ウォールの各導体層7を越えてその外部へと漏れ出ぬよ
うにする必要がある。
In addition, in the package 2 of the above-described embodiment, according to the high and low of the frequency of the signal sent to each signal line 1, the pseudo inside of the substrate of the insulator 3 around each signal line 1 and the frame 12 and the surface thereof are provided. The distance between each conductor layer 7 forming the metal wall 6 and each signal line 1 is adjusted by changing the thickness of the plates 8a, 8b and the frame plates 12a, 12b which are the insulators 3 forming the package 2. It is necessary to adjust so that the signal flowing through each signal line 1 does not leak over the conductor layers 7 of the pseudo metal wall to the outside thereof.

また、各信号線路1周囲のセラミックの絶縁体3であ
る基板8や枠体12の内部やその表面に備える擬似メタル
ウォール6の構成する接地層5に導通する各導体層7が
長い場合は、第3図に示したように、該各導体層7の中
途部と接地層5との間や各導体層7間の絶縁体3である
基板8や枠体12中に、メタライズ導体を充填したヴィア
ホール17を設けて、該各ヴィアホール17を介して接地層
5と各導体層7中途部との間を電気的に導通し、各導体
層7の全てが接地層5と同一電位を保つようにすると良
い。また、そうした場合には、上下の接地層5に挟まれ
た信号線路1の左側部分と右側部分とを、上下に複数段
に並べて備えた複数の導体層7と該導体層7を接地層5
に導通するメタライズ層13とに加えて、導体層7を接地
層5に導通するメタライズ導体を充填したヴィアホール
17で、密に囲むことができる。そして、上下の接地層5
に挟まれた信号線路1の左側部分と右側部分とを前記導
体層7と接地層5とメタライズ層13とヴィアホール17と
からなる隙間の少ないシールド効果の高いシールド壁で
密に囲んで、信号線路1に伝わる高周波信号の一部が、
前記シールド壁の隙間を通り抜けて、他の信号線路1に
混入するのを確実に防いだり、信号線路1の特性インピ
ーダンスを的確にマッチングさせたりできて都合が良
い。さらに、各導体層7と接地層5との同電位性を的確
に保つためには、各信号線路1周囲の絶縁体3である基
板8や枠体12の内部やその表面に備える各導体層7の幅
やその厚さを、各信号線路1の持つインピーダンスを考
慮して、所定の幅と厚さに形成する必要がある。
Further, in the case where the conductor layers 7 which are electrically connected to the ground layer 5 formed by the pseudo metal wall 6 provided inside or on the surface of the substrate 8 or the frame 12 which is the ceramic insulator 3 around each signal line 1 are long, As shown in FIG. 3, the metallized conductor was filled in the substrate 8 or the frame 12 which is the insulator 3 between the midway portion of each conductor layer 7 and the ground layer 5 or between each conductor layer 7. The via holes 17 are provided, and the ground layer 5 and the middle portions of the conductor layers 7 are electrically connected through the via holes 17, and all the conductor layers 7 maintain the same potential as the ground layer 5. It is good to do so. Further, in such a case, a plurality of conductor layers 7 provided with the left side portion and the right side portion of the signal line 1 sandwiched between the upper and lower ground layers 5 arranged vertically in a plurality of stages and the conductor layers 7 are ground layers 5.
In addition to the metallization layer 13 that conducts to the ground, the via hole filled with the metallization conductor that conducts the conductor layer 7 to the ground layer 5
At 17, it can be tightly enclosed. And the upper and lower ground layers 5
The left side portion and the right side portion of the signal line 1 sandwiched between are densely surrounded by a shield wall having a high shielding effect, which is composed of the conductor layer 7, the ground layer 5, the metallized layer 13 and the via hole 17 and has a high shield effect. Part of the high-frequency signal transmitted on line 1
This is convenient because it can be surely prevented from entering the other signal line 1 through the gap of the shield wall, and that the characteristic impedance of the signal line 1 can be accurately matched. Furthermore, in order to maintain the same potential of each conductor layer 7 and the ground layer 5 accurately, each conductor layer provided inside or on the surface of the substrate 8 or the frame 12 which is the insulator 3 around each signal line 1 is provided. The width and the thickness of 7 need to be formed in a predetermined width and thickness in consideration of the impedance of each signal line 1.

さらに、上述実施例のパッケージ2では、基板8や枠
体12をそれぞれ二層に構成したが、これを三層以上の多
層として、パッケージ2中の導体層7の数量を増やすこ
とが好ましいことは言うまでもない。
Furthermore, in the package 2 of the above-described embodiment, the substrate 8 and the frame body 12 each have two layers, but it is preferable to increase the number of the conductor layers 7 in the package 2 by using three layers or more. Needless to say.

また、上述実施例に類似する実施例として、第4図に
示したような、各信号線路1をパッケージ2を構成する
絶縁体3である基板8の内部やその表面に上下二段等の
多段に亙って備えると共に、各段の各信号線路1周囲の
絶縁体3である基板8や枠体12の内部やその表面に、接
地層5に導通する複数本の導体層7を各信号線路1と平
行かまたはほぼ平行に備えたパッケージ2が考えられ
る。
Further, as an embodiment similar to the above-mentioned embodiment, as shown in FIG. 4, multistages such as upper and lower two stages are provided inside or on the surface of the substrate 8 which is the insulator 3 constituting each package of each signal line 1. A plurality of conductor layers 7 that are electrically connected to the ground layer 5 are provided inside or on the surface of the substrate 8 or the frame body 12 that is the insulator 3 around each signal line 1 at each stage. A package 2 with or in parallel with 1 is conceivable.

さらに、パッケージ2の基板8や枠体12を構成する絶
縁体3に、ポリイミド樹脂等の樹脂を用いると共に、該
樹脂の内部やその表面に、蒸着や張り合わせ等により信
号線路1や導体層7等を構成する導体パターンを設ける
ようにして、本発明の高周波素子用パッケージ2を形成
しても良い。
Further, a resin such as a polyimide resin is used for the insulator 3 that forms the substrate 8 and the frame 12 of the package 2, and the signal line 1 and the conductor layer 7 are formed inside or on the surface of the resin by vapor deposition or laminating. The high frequency element package 2 of the present invention may be formed by providing the conductor pattern constituting the above.

次の第1表は、従来の通常の積層法により形成したセ
ラミックパッケージAと、実開昭61−86944号公報記載
のパッケージBと、本発明のパッケージCとにおける隣
合う各信号線路1間の絶縁度の比較を示す。
The following Table 1 shows the relationship between the adjacent signal lines 1 in the ceramic package A formed by the conventional ordinary lamination method, the package B described in Japanese Utility Model Laid-Open No. 61-86944, and the package C of the present invention. A comparison of insulation is shown.

第1表によれば、従来のパッケージAに比べて、本発
明のパッケージCが、その超高周波等における絶縁度
が、実開昭61−86944号公報記載のパッケージBと同様
に極めて高く、高周波特性に優れたパッケージであるこ
とが判る。
According to Table 1, compared with the conventional package A, the package C of the present invention has an extremely high degree of insulation at ultra-high frequencies, etc., similarly to the package B described in Japanese Utility Model Application Laid-Open No. 61-86944. It can be seen that the package has excellent characteristics.

[発明の効果] 以上説明したように、本発明の高周波素子用パッケー
ジによれば、上下の接地層に挟まれた信号線路の左側部
分と右側部分とに、上下に複数段に密に並べて備えた複
数の導体層と該導体層を接地層に導通する導体線路とか
らなる隙間の少ないシールド効果の高いシールド壁を形
成できる。そして、信号線路に伝わる高周波信号の一部
が、前記シールド壁の隙間を通り抜けて、他の信号線路
に混入するのを確実に防止できる。
[Effects of the Invention] As described above, according to the high-frequency device package of the present invention, the left and right portions of the signal line sandwiched between the upper and lower ground layers are densely arranged vertically in a plurality of stages. Further, it is possible to form a shield wall having a high shield effect with a small gap formed of a plurality of conductor layers and a conductor line that conducts the conductor layers to the ground layer. Then, it is possible to reliably prevent a part of the high frequency signal transmitted to the signal line from passing through the gap of the shield wall and being mixed into another signal line.

また、信号線路の上方と下方とに複数本の信号線路の
上方とその下方とを連続して隙間なく覆うシールド効果
の高い接地層を備えることができると共に、上下の接地
層に挟まれた信号線路の左側部分と右側部分とに隙間の
少ないシールド効果の高い上記シールド壁を備えること
ができる。そして、信号線路を同軸線路に極めて近い擬
似同軸線路に形成できる。そして、信号線路と上記接地
層や導体層や導体線路との間の距離、上下に複数段に並
べて備える複数の導体層のピッチ、又は信号線路や接地
層や導体層や導体線路の幅やその厚さを大小に調整し
て、信号線路の特性インピーダンスを一定値に的確にマ
ッチングさせることができる。そして、信号線路の特性
インピーダンスの不整合に基づく、信号線路を伝わる高
周波信号の伝送損失を低減させることができる。
In addition, a ground layer having a high shielding effect can be provided above and below the signal line so as to continuously cover the upper and lower parts of the signal line with no gap, and the signal sandwiched between the upper and lower ground layers can be provided. It is possible to equip the left side portion and the right side portion of the line with the shield wall having a small shield and a high shield effect. Then, the signal line can be formed into a pseudo coaxial line extremely close to the coaxial line. Then, the distance between the signal line and the ground layer, the conductor layer, or the conductor line, the pitch of the plurality of conductor layers arranged in a plurality of layers vertically, or the width of the signal line, the ground layer, the conductor layer, or the conductor line, or the width thereof. By adjusting the thickness to a large or small value, the characteristic impedance of the signal line can be accurately matched to a constant value. Then, it is possible to reduce the transmission loss of the high frequency signal transmitted through the signal line based on the mismatch of the characteristic impedance of the signal line.

また、上下の接地層に挟まれた基板と枠体とを構成す
る絶縁体部分に複数の導体層を上下に複数案に小ピッチ
で密に並べて備えて、その上下の接地層に挟まれた基板
と枠体とを構成する絶縁体部分のほぼ全体を接地電位に
近づけることができる。そして、信号線路に伝わる高周
波信号で信号線路周囲のリング状をなす枠体部分や基板
部分に生ずるリング共振の振幅幅を大幅に低減させるこ
とができる。そして、信号線路周囲の枠体部分や基板部
分に生ずるリング共振の悪影響を受けて、信号線路の高
周波特性が低下するのを確実に防ぐことができる。
Further, a plurality of conductor layers are densely arranged vertically with a plurality of small pitches in an insulator portion forming a substrate and a frame body sandwiched between the upper and lower ground layers, and sandwiched between the upper and lower ground layers. It is possible to bring almost the entire insulator portion forming the substrate and the frame close to the ground potential. Then, the amplitude width of the ring resonance generated in the ring-shaped frame portion or the substrate portion around the signal line by the high frequency signal transmitted to the signal line can be significantly reduced. Then, it is possible to reliably prevent the high frequency characteristics of the signal line from being deteriorated due to the adverse effect of the ring resonance generated in the frame portion and the substrate portion around the signal line.

加えて、本発明のパッケージの製造に際しては、従来
のセラミックグリーンシートを複数枚積層して一体焼成
して形成するセラミックパッケージの製造方法をそのま
ま用いて、本発明のパッケージを極めて容易に製造でき
る。そして、セラミック等からなる入出力端子取着部材
を嵌着するための切欠部をパッケージ本体を構成する金
属基体に削成する手数の掛かる作業を不要とすることが
できる。
In addition, when manufacturing the package of the present invention, the package of the present invention can be manufactured very easily by using the conventional method of manufacturing a ceramic package in which a plurality of ceramic green sheets are laminated and integrally fired. Further, it is possible to eliminate the need for the laborious work of cutting the notch for fitting the input / output terminal attachment member made of ceramic or the like on the metal base body forming the package body.

また、本発明のパッケージの製造に際して、信号線路
形成用のメタライズ線路、導体層形成用のメタライズ層
及び導体層を接地層に導通するための導体線路形成用の
メタライズ層やメタライズ導体を充填したヴィアホール
を基板や枠体形成用のセラミックグリーンシートに多数
並べて備えることにより、本発明のパッケージの多端子
化を容易に行える。
Further, in manufacturing the package of the present invention, a metallized line for forming a signal line, a metallized layer for forming a conductor layer, and a metallized layer for forming a conductor line for conducting the conductor layer to a ground layer and a via filled with a metallized conductor are used. By providing a large number of holes on the substrate or the ceramic green sheet for forming the frame, the package of the present invention can be easily provided with multiple terminals.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明のパッケージの斜視図、第2図は第1図
のパッケージの信号線路部分の拡大横断面図、第3図は
本発明の他のパッケージの信号線路部分の横断面図、第
4図は本発明の他のパッケージの信号線路部分の横断面
図である。 1……信号線路、2……パッケージ、 3……絶縁体、7……導体層、 8……基板、12……枠体。
1 is a perspective view of a package of the present invention, FIG. 2 is an enlarged cross-sectional view of a signal line portion of the package of FIG. 1, FIG. 3 is a cross-sectional view of a signal line portion of another package of the present invention, FIG. 4 is a cross-sectional view of a signal line portion of another package of the present invention. 1 ... Signal line, 2 ... Package, 3 ... Insulator, 7 ... Conductor layer, 8 ... Substrate, 12 ... Frame body.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 酒井 博之 長野県長野市大字栗田字舎利田711番地 新光電気工業株式会社内 (72)発明者 石塚 文則 東京都武蔵野市緑町3丁目9番11号 日本 電信電話株式会社電子機構技術研究所内 (72)発明者 佐藤 信夫 東京都武蔵野市緑町3丁目9番11号 日本 電信電話株式会社電子機構技術研究所内 (56)参考文献 実開 昭59−74758(JP,U) ─────────────────────────────────────────────────── ─── Continuation of front page (72) Hiroyuki Sakai, Hiroyuki Sakai, 711, Rita, Kurita, Nagano City, Nagano Shinko Electric Industry Co., Ltd. (72) Inventor Nobuo Sato 3-9-11 Midoricho, Musashino City, Tokyo Japan Telegraph and Telephone Corporation, Research Institute for Electronic Devices (56) References: 59-74758 (JP) , U)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】高周波素子を取り付ける絶縁体からなる基
板に前記高周波素子を取り囲む絶縁体からなる枠体が積
層され、前記基板に複数本の信号線路が横に並べて備え
られてなる高周波素子用パッケージにおいて、前記基板
に前記複数本の信号線路の下方を連続して覆う接地層を
備え、前記枠体に前記複数本の信号線路の上方を連続し
て覆う接地層を備え、該上下の接地層に挟まれた前記各
信号線路の左側と右側の前記基板と枠体とを構成する絶
縁体部分に複数の導体層を信号線路と平行か又はほぼ平
行に上下に複数段に並べて備え、前記絶縁体部分に前記
導体層を前記接地層に導通する導体線路を備えたことを
特徴とする高周波素子用パッケージ。
1. A package for a high-frequency element, comprising a substrate made of an insulator for mounting a high-frequency element, a frame made of an insulator surrounding the high-frequency element laminated on the substrate, and a plurality of signal lines arranged side by side on the substrate. In the above, the substrate is provided with a ground layer continuously covering the lower portions of the plurality of signal lines, and the frame body is provided with a ground layer continuously covering the upper portions of the plurality of signal lines. The plurality of conductor layers are arranged in parallel in the signal lines on the left and right sides of the respective signal lines sandwiched between the substrate and the frame, and are arranged substantially vertically in parallel with each other. A package for a high-frequency element, comprising a conductor line for conducting the conductor layer to the ground layer in a body portion.
JP62097196A 1987-04-20 1987-04-20 Package for high frequency devices Expired - Fee Related JPH0821642B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62097196A JPH0821642B2 (en) 1987-04-20 1987-04-20 Package for high frequency devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62097196A JPH0821642B2 (en) 1987-04-20 1987-04-20 Package for high frequency devices

Publications (2)

Publication Number Publication Date
JPS63261859A JPS63261859A (en) 1988-10-28
JPH0821642B2 true JPH0821642B2 (en) 1996-03-04

Family

ID=14185841

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62097196A Expired - Fee Related JPH0821642B2 (en) 1987-04-20 1987-04-20 Package for high frequency devices

Country Status (1)

Country Link
JP (1) JPH0821642B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0377450U (en) * 1989-11-28 1991-08-05
JP3618046B2 (en) * 1998-04-27 2005-02-09 京セラ株式会社 High frequency circuit package
JP3346752B2 (en) 1999-11-15 2002-11-18 日本電気株式会社 High frequency package
JP6224322B2 (en) * 2013-01-30 2017-11-01 京セラ株式会社 Electronic component storage package and electronic device using the same
JP6272052B2 (en) * 2014-01-29 2018-01-31 京セラ株式会社 Electronic device mounting substrate and electronic device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5974758U (en) * 1982-11-11 1984-05-21 三洋電機株式会社 Wiring board structure
JPS62274754A (en) * 1986-05-23 1987-11-28 Hitachi Ltd Integrated circuit package

Also Published As

Publication number Publication date
JPS63261859A (en) 1988-10-28

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