JPH05206419A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To forcibly restrain a voltage change in a power-supply voltage and in a substrate voltage due to a transient charging and discharge current at an output buffer in a semiconductor integrated circuit device according to a master slice system. CONSTITUTION:Normally, a terminal 6 for cutoff control is fixed to an 'H' level; it is insulated by a transfer gate. A voltage which is higher than that of a power-supply line 3a by the portion of the absolute value of a threshold value for a P-channel MOS transistor for correction use is applied to a power- supply line 3b for correction use; a voltage which is lower than that of a grounding line 2a by the portion of the absolute value of the threshold value for an N-channel MOS transistor for correction use is applied to a grounding line 2b for correction use. When a source potential is changed by a transient charging and discharge current, the P-channel MOS transistor 13 for correction use or the N-channel MOS transistor 16 for correction use is set to an ON state, an effect that a power-supply voltage or a substrate voltage is returned forcibly to a reference potential is obtained, and the power supply voltage and the substrate voltage can be supplied stably.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a digital integrated circuit.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional semiconductor integrated circuit device has a bonding pad 1, a ground line 2a, a power supply line 3a, an output interface circuit 21, a logic integrated circuit 4 for performing a logic operation, and a logic operation. It has a logical operation output signal line 9 for propagating the result to the output interface circuit 21, an external output terminal 8, an additional ground terminal 22, an input interface circuit 10, and an external input terminal 11.

FIG. 4 shows the output interface circuit 2 of FIG.
1 is a circuit diagram of FIG. 1 and is composed of a P channel MOS type transistor 14 and an N channel MOS type transistor 15.

In FIGS. 3 and 4, a signal input to the external input terminal 11 passes through the input interface circuit 10, and a signal logically operated by the logic integrated circuit 4 passes through the output interface circuit 21. It is output to the external output terminal 8.

Focusing on the operating current of the output interface circuit 21, when the signal logically operated in the logic integrated circuit changes from the "L" level to the "H" level, the P-channel MOS type transistor 14 is in the OFF state, N-level. The channel MOS type transistor 15 is turned on,
A charging current for the entire load capacity driven by the output interface circuit 21 transiently flows into the ground line 2a.

Then, the potential of the ground line 2a rises, which adversely affects the input interface circuit 10 near the output interface circuit 21 and causes a malfunction. In order to avoid this, an additional grounding terminal 22 is provided so that the potential to rise can be released to the outside,
Techniques such as arranging the input interface circuit 10 as far as possible from the output interface circuit 21 are provided.

[0007]

In this conventional semiconductor integrated circuit device, when a plurality of additional ground terminals 22 are provided,
In fact, the number of usable terminals is reduced, the number of pins is increased along with the increase in scale of LSI, and the potential fluctuation of the power supply line or the ground line due to the transient operating current is increasing.

Also, in the process of creating a test pattern by a circuit designer, the number of output buffers that change at the same time becomes extremely large due to the effect of increasing the number of pins, so that the redundancy of the test pattern or the increase in the number of steps for designing the circuit is increased. Connected to.

An object of the present invention is to provide a semiconductor integrated circuit device which solves the above-mentioned problems, suppresses potential fluctuations and prevents man-hours from increasing.

[0010]

A semiconductor integrated circuit device according to the present invention has a final stage output interface circuit including a P-channel MOS type transistor for correcting a power supply voltage and an N-channel MOS type transistor for correcting a substrate voltage. And a cutoff circuit that cuts off several kinds of voltage levels of the power supply voltage and the substrate voltage, respectively.

[0011]

1 is a block diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing the cutoff circuit 5 and the output interface circuit 7 of FIG.

1 and 2, the semiconductor integrated circuit device according to the present embodiment has a logic integrated circuit 4, a cutoff circuit 5, an output interface circuit 7, an input interface circuit 10, and a cutoff control terminal 6. External output terminal 8, external input terminal 11, logical operation output signal line 9, and ground line 2
a, correction ground wire 2b, power supply wire 3a, correction power supply wire 3b
It has and.

Here, the cutoff circuit 5 has two inverters and two transfer gates 12. The output interface circuit 7 includes a P-channel MOS type transistor 14, an N-channel MOS type transistor 15, and a correcting P-channel MOS type transistor 13.
And a correction N-channel MOS type transistor 16. Each line 2a, 2b, 3a, 3b is the same as in FIG.

The components shown in FIGS. 1 and 2 will be described in accordance with the flow of signals. The signal input from the external input terminal 11 passes through the input interface circuit 10, and the signal logically operated by the logic integrated circuit 4 is placed on the logical operation output signal line 9 and passes through the output interface circuit 7 to the output signal terminal 8. Is output.

Normally, the cutoff control terminal 6 is set to the "H" level, and the power supply line 3a and the correction power supply line 3b, and the ground line 2a and the correction ground line 2b are insulated by the transfer gate 12, respectively. . The correction power supply line 3b is supplied with a potential higher than the potential of the power supply line 3a by the absolute value of the threshold value of the correction P-channel MOS transistor 13, and the correction ground line 2b is supplied with the potential of the ground line 2a. A potential lower than the absolute value of the threshold value of the correcting N-channel MOS transistor 16 is applied.

Focusing on the operating current of the output interface circuit 7, when the logical operation output signal line 9 changes from the "L" level to the "H" level, the P-channel MOS type transistor 14 is in the OFF state, and the N-channel MOS type transistor. 15 is turned on, and the charging current for the entire load capacity driven by the output interface circuit 7 transiently flows into the ground line 2a.

Then, the potential of the ground line 2a tends to rise, but the correction N-channel MOS type transistor 16
Since the difference of the gate potential with respect to the source potential of the above exceeds the threshold value, the correction N-channel MOS transistor 16
Is turned on, and the potential rise of the ground line 2a is forcibly suppressed. For the same reason, the potential fluctuation of the power supply line 3a can be similarly suppressed.

Further, by setting the cutoff control signal 6 to the "L" level, the correction power supply line 3b and the correction ground line 2b.
Can be used as a reinforcing power line and a reinforcing ground line, respectively.

In the semiconductor integrated circuit device of this embodiment, when the reference potentials of the power supply line and the ground line change, a correction transistor forcibly returning to the reference potential, a plurality of source voltage correction power supplies, and those power supplies. And a shutoff circuit for shutting off.

[0021]

As described above, according to the present invention, the P-channel MOS type transistor for correcting the power supply voltage and the N for correcting the substrate voltage are provided in the final stage output interface circuit.
By including a channel MOS transistor and a cutoff circuit that cuts off a plurality of voltage levels of the power supply voltage and the substrate voltage, respectively, a stable power supply voltage and a substrate voltage can be supplied at all times. The semiconductor integrated circuit device can be prevented from malfunctioning due to a transient charge / discharge current.

[Brief description of drawings]

FIG. 1 is a plan view showing a semiconductor integrated circuit device of one embodiment of the present invention.

FIG. 2 is a plan view showing a cutoff circuit and an output interface circuit of FIG.

FIG. 3 is a plan view showing a conventional semiconductor integrated circuit device.

FIG. 4 is a circuit diagram of the output interface circuit of FIG.

[Explanation of symbols]

 2a Ground line 2b Correction ground line 3a Power line 3b Correction power line 4 Logic integrated circuit 5 Breaking circuit 6 Breaking control terminal 7,21 Output interface circuit 8 External output terminal 9 Logical operation output signal line 10 Input interface circuit 11 External Input terminal 12 Transfer gate 13 P channel MOS transistor for correction 14 P channel MOS transistor 15 N channel MOS transistor 16 N channel MOS transistor for correction 22 Additional ground terminal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 27/04 G 8427-4M

Claims (1)

[Claims] 1. An output interface circuit at a final stage,
A cutoff circuit having a P-channel MOS type transistor for correcting the power supply voltage and an N-channel MOS type transistor for correcting the substrate voltage, and for interrupting several kinds of voltage levels of the power supply voltage and the substrate voltage, respectively. Integrated circuit device.