JPH0786904A - Interface circuit - Google Patents

Abstract

PURPOSE:To prevent a transistor under use from being degraded by an impressed voltage without using a transistor provided with high voltage resistance. CONSTITUTION:An N channel MOS transistor TN 2 is used for lowering (clamping) a voltage which is higher than a power supply voltage VCC 1 and impressed from a pad P1. When inputting an H state to an input IN, a voltage boost clamp circuit U outputs a voltage at a voltage degree adding a threshold voltage Vt of this N channel MOS transistor TN 2 to the power supply voltage VCC 1 to an output OUT. On the other hand, when inputting an L state, the circuit U outputs a voltage lower than the power supply voltage VCC 1. The voltage to be impressed to the N channel MOS transistor TN 2 is made higher than the power supply voltage VCC 1 but lower than the voltage to be impressed to the pad P1, and the term of impression is short time as well.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention According to the present invention, a signal voltage from an external circuit operating at a power supply voltage VCC2 higher than the power supply voltage VCC1 of the interface circuit is applied to an interface terminal connected to the outside. At least a certain period, the signal input from the outside via the interface terminal, and the signal output to the outside via the interface terminal, the interface circuit for performing at least one of these signal input and signal output, in particular,
An interface circuit that can reduce problems such as deterioration due to the applied voltage of the transistor used, a leak current flowing in the forward direction of the parasitic diode, and an increase in the risk of occurrence of a latch-up phenomenon, which are problems in such an interface circuit Regarding

[0002]

2. Description of the Related Art In a general computer, a CP is usually used.
In order for a U (central processing unit) to access various peripheral devices such as a main storage device and an input / output device,
A predetermined bus such as what is called a system bus is used. With such a bus, it is possible to share a transmission path for program instructions and data in the computer,
It is possible to unify the interfaces of the peripheral devices in the computer. Further, with such a bus, the scale of the interface unit occupying the entire computer hardware can be reduced.

On the other hand, in semiconductor integrated circuits used for computers, control devices, etc., a lower power supply voltage is used as compared with the conventional one. For example, a power supply voltage that has been generally set to 5 volts in the related art and one that uses a lower power supply voltage of 3 volts or 3.3 volts has been widely used. One of the reasons for lowering the power supply voltage is reduction of power consumption and reduction of withstand voltage due to reduction in size of elements such as transistors built in a semiconductor integrated circuit.

The manufacturing technology of semiconductor integrated circuits has made dramatic progress, and the degree of integration of semiconductor integrated circuits to be manufactured has also been dramatically improved due to, for example, miniaturization of the manufacturing process. With such miniaturization of the manufacturing process,
In recent years, the breakdown voltage of elements such as transistors built into semiconductor integrated circuits has become a problem. That is, due to the miniaturization of the manufacturing process, the size of an element such as a built-in transistor is reduced, and the breakdown voltage thereof is also reduced accordingly. Therefore, for example, a semiconductor integrated circuit manufactured by a manufacturing process of 0.5 micron rule generally has a power supply voltage of 3 volts.

When the power supply voltage used in the semiconductor integrated circuit is lowered in this way, a conventional power supply voltage such as 5 volts is used in a part of a series of logic circuits, and a part of the logic circuit is 3 volts. And lower power supply voltage will be used. For example, in a system using a bus as described above, it is also necessary for circuits of different power supply voltages to access the same bus.

FIG. 16 is a circuit diagram showing an example of an interface circuit for inputting / outputting a signal to / from a certain bus.

FIG. 16 shows an interface circuit which inputs or outputs a signal through pad P3 of a semiconductor integrated circuit in which the interface circuit connected to a bus line of a bus is built. ing. It should be noted that the one that performs at least one of signal input and signal output to the bus in this manner is hereinafter referred to as a bus interface circuit.

The bus interface circuit shown in FIG. 16 mainly includes a P channel MOS transistor TP.
30 and TP31, N-channel MOS transistor T
It is composed of N30 and TN31. In the bus interface circuit, the P-channel MOS transistor TP30 and the N-channel MOS transistor TN30 form an output interface circuit. On the other hand, the P-channel MOS transistor T
P31 and the N-channel MOS transistor TN31
An input interface circuit is configured by
The power supply voltage of this bus interface circuit applied between the power supply VCC1 and the ground GND is 3 volts.

This bus interface circuit has a terminal T1.
And a signal input to the terminal T2 is output to the pad P3. Specifically, the terminal T1 and the terminal T2
When the L state is inputted to both of P and P, the bus interface circuit outputs the H state to the pad P3. On the other hand, when the H state is input to both the terminal T1 and the terminal T2, the L state is output to the pad P3.
When the H state is input to the terminal T1 and the L state is input to the terminal T2, the output from the bus interface circuit is not performed, and the output is in the high impedance state.

Further, the interface circuit uses the P-channel MOS transistor TP31 and the N-channel MOS transistor TN31 to form the pad P.
The signal input to 3 is output to terminal T3.

In the bus interface circuit shown in FIG. 16, a signal voltage from an external circuit which operates at a power supply voltage of 5 volts higher than the power supply voltage of 3 volts of the bus interface circuit is applied to the pad P3. I shall. At this time, a voltage equal to or higher than the power supply voltage of 3 V is applied to the pad P3. If such a higher voltage is applied, the following problems will occur.

(1) Degradation of applied transistor due to applied voltage: Since the power supply voltage of the bus interface circuit is 3 V, the withstand voltage of the used transistor is based on this voltage. However,
When a voltage higher than 3 volts is applied to the pad P3, the P-channel MOS transistor TP31
Gate and the N-channel MOS transistor TN3
A voltage higher than 3 volts is applied to the gate of 1. When a voltage higher than the breakdown voltage is applied in this way, the deterioration of the transistor is accelerated,
In some cases, there is a risk of dielectric breakdown. or,
When a voltage higher than the specified voltage is applied to the gate, hot carriers are injected into the oxide insulating film, and the MOS transistor does not turn off and deteriorates.

(2) Leakage current flows in the forward direction of the parasitic diode: For example, in FIG. 16, the parasitic diode D5 exists around the P-channel MOS transistor TP30. Therefore, the pad P3
If a voltage higher than the power supply voltage is applied to the power supply VC, the power is supplied from the pad P3 to the power supply VC via the parasitic diode D5.
A leak current flows into C1. If such a leak current occurs, there is not only a problem such as a malfunction, but also a problem that the element deteriorates due to heat generation or the like.

(3) Increasing possibility of occurrence of latch-up phenomenon: When a forward bias voltage is applied to the parasitic diode and a leak current flows as described above, the possibility of occurrence of latch-up phenomenon is inevitable. It will increase.

In order to solve the problems shown in (1) to (3) above, Japanese Patent Laid-Open No. 4-243321 discloses a technique as shown in FIG. In FIG. 17, an N channel MOS transistor TN32 is particularly used for the bus interface circuit shown in FIG. The N channel MOS transistor TN3
A higher power supply voltage of 5 volts used in an external circuit connected to the pad P3 is applied to the gate of the power supply VCC2. This Japanese Patent Laid-Open No. 4-243
According to the technique disclosed in No. 321, the applied voltage can be clamped lower in the N-channel MOS transistor TN32. Therefore, it is possible to reduce the above-mentioned problems such as the deterioration due to the applied voltage and the leakage current in the parasitic diode.

[0016]

However, in the technique disclosed in Japanese Patent Laid-Open No. 4-243321, a voltage higher than the power supply voltage is applied to the newly used MOS transistor. That is, in the Japanese Patent Laid-Open No. 4-243321, the P-channel MOS transistors TP30 and TP31 or the N-channel MOS transistors TN30 and TN31 are not applied with a voltage higher than the power supply voltage thereof, but the newly provided N-channel MOS transistor TN32 is provided. For
A higher voltage is applied to the power supply VCC2.

Therefore, in order to prevent the N-channel MOS transistor TN32 from being deteriorated by the applied voltage, the P-channel MOS transistor TP30 is used.
And TP31 or the N-channel MOS transistor TN
It is necessary to increase the breakdown voltage with respect to 30 and TN31. For example, the N-channel MOS transistor TN3
For 2 only, the gate oxide film needs to be thickened.

Therefore, in Japanese Patent Laid-Open No. 4-243321,
If the interface circuit is to be built into one semiconductor integrated circuit, it is necessary to thicken the gate oxide film in the local portion of the layout, which complicates the manufacturing process and increases the number of steps. Therefore, there is a problem in terms of cost and the like.

The present invention has been made to solve the above-mentioned conventional problems, and an interface terminal connected to the outside is connected to an external circuit operating at a power supply voltage VCC2 higher than the power supply voltage VCC1 of the interface circuit. There is a risk of deterioration due to the applied voltage of the transistor used, leakage current flowing in the forward direction of the parasitic diode, and latch-up phenomenon, which are problems in the interface circuit in which the signal voltage is applied for at least a certain period. An object of the present invention is to provide an interface circuit capable of reducing an increase or the like without using a transistor having a high breakdown voltage.

[0020]

According to the present invention, a signal voltage from an external circuit operating at a power supply voltage VCC2 higher than the power supply voltage VCC1 of the interface circuit is applied to an interface terminal connected to the outside. However, there is at least a certain period of time, in the interface circuit that performs at least one of these signal input and signal output of the signal input from the outside via the interface terminal and the signal output to the outside via the interface terminal, And a signal clamp transistor that clamps to a voltage according to the voltage input to the input terminal, and when inputting an H state to the input IN, outputs a voltage of about the sum of the power supply voltage VCC1 and the threshold voltage Vt of the signal clamp transistor. However, when inputting the L state, the power source voltage is not higher than VCC1. A voltage boosting clamp circuit for outputting a voltage, the output of the voltage boosting clamp circuit is connected to the gate of the signal clamp transistor, and the signal clamp transistor is connected to the interface terminal. The object is achieved by inserting and connecting the transistor of the internal circuit and the interface terminal.

In the interface circuit, the voltage boost clamp circuit includes a boost capacitor C, a boost charging diode D1, and a voltage clamp diode D2 having a threshold voltage substantially equal to the threshold voltage Vt of the signal clamp transistor. The boosting capacitor C is provided with one terminal of the boosting capacitor C as the input IN, and is located between the other terminal of the boosting capacitor C and the power supply of the power supply voltage VCC1 and has its anode on the power supply side. D1 is connected to the voltage clamp diode D2 so that its anode is on the boost capacitor C side.
And the terminal of the step-up capacitor C to which the step-up charging diode D1 and the voltage clamp diode D2 are connected is used as the output of the voltage step-up clamp circuit, thereby achieving the above-mentioned object and The interface circuit can be operated with at least a single power source. In other words, it is possible to operate by using only the power supply voltage VCC1 without using the higher power supply voltage VCC2.

[0022]

The present invention is based on the above-mentioned Japanese Unexamined Patent Publication No.
243321, the N-channel MO of FIG.
A signal clamp transistor corresponding to the S transistor TN32 is used to reduce the higher voltage applied to the interface terminal connected to the outside. However, in the present invention, the signal clamp transistors are not uniformly operated. That is, first, consideration is given to the timing at which the signal clamp transistor operates. Further, the signal clamp transistor is designed so as not to cause an unnecessary voltage drop.

In the present invention, a voltage boosting clamp circuit is provided which includes the signal clamp transistor for clamping to a voltage according to the voltage input to the gate, and which generates a voltage to be input to the gate of the signal clamp transistor. I am preparing. When the H state is input to the input IN, the voltage boosting clamp circuit outputs a voltage that is about the sum of the power supply voltage VCC1 and the threshold voltage Vt of the signal clamp transistor.
The voltage boosting clamp circuit outputs a voltage equal to or lower than the power supply voltage VCC1 when the L state is input to its input IN.

Therefore, in the present invention, since the signal clamp transistor does not always operate, a voltage higher than the power supply voltage VCC1 is input to its gate, but deterioration due to this can be further reduced. . That is, since a voltage higher than the power supply voltage VCC1 is not always input, deterioration due to the applied voltage is reduced.

Since the voltage input to the gate of the signal clamp transistor is about the voltage obtained by adding the power supply voltage VCC1 to the threshold voltage Vt of the signal clamp transistor, the voltage generated by the signal clamp transistor. The clamp does not unnecessarily apply voltage. Further, it is possible to reduce the leakage current flowing in the forward direction of the parasitic diode and the risk of occurrence of a latch-up phenomenon.

[0026]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram of an interface circuit to which the present invention is applied.

The interface circuit shown in FIG. 1 is a bus interface circuit which operates at a power supply voltage VCC1 of 3 volts, particularly a bus output interface circuit. The interface circuit is mainly composed of a P-channel MOS transistor TP1, N-channel MOS transistors TN1 to TN3, an inverter I1, and a boost clamp circuit U.

The P-channel MOS transistor TP1
Corresponds to the P-channel MOS transistor TP30 shown in FIG. The N-channel MOS transistor TN1 corresponds to the N-channel MOS transistor TN30 shown in FIG.

Further, the N-channel MOS transistor T
N2 and TN3 are provided as the signal clamp transistors of the present invention. That is, these N channel MOS
The transistors TN2 and TN3 are used to clamp the pad P1 even if a signal voltage from an external circuit operating at a power supply voltage VCC2 higher than the power supply voltage VCC1 of the interface circuit is applied. . That is, even if a voltage higher than the power supply voltage VCC1 is applied to the pad P1, it is provided to prevent such a high voltage from being applied to the P-channel MOS transistor TP1 and the N-channel MOS transistor TN1. ing.

Further, in this embodiment, a voltage boosting clamp circuit U to which the present invention is applied is provided. The voltage boosting clamp circuit U outputs a voltage obtained by adding the threshold voltage Vt of the N-channel MOS transistor TN2 to the power supply voltage VCC1 to the output OUT when inputting the H state to the input IN. On the other hand, when the L state is input to the input IN, a voltage obtained by subtracting the threshold voltage Vt of the N-channel MOS transistor TN2 from the power supply voltage VCC1 is output to the output OUT. A signal obtained by inverting the signal input to the terminal T1 by the inverter I1 is input to the input IN of the voltage boosting clamp circuit U.

Therefore, in the first embodiment, the N
The channel MOS transistors TN2 and TN3 can clamp a voltage higher than the power supply voltage VCC1 applied from the pad P1 to a low level. Further, when the P-channel MOS transistor TP1 is turned on and the H state is output from the interface circuit, the output OUT of the voltage boosting clamp circuit U is output.
Outputs a voltage of (VCC1 + Vt) = (3 volts + Vt). Therefore, the N channel M
When the OS transistor TN2 is turned on, it is possible to reduce unnecessary voltage drop due to this. That is, the problem of the voltage drop between the source and drain of the N-channel MOS transistor TN2 corresponding to the threshold voltage Vt thereof is reduced.

FIG. 2 is a circuit diagram of a second embodiment of the interface circuit to which the present invention is applied.

The interface circuit of the second embodiment is
It is a bus interface circuit, particularly a bus input interface circuit for a bus line connected to the pad P2. The interface circuit is mainly composed of an N-channel MOS transistor TN4, a voltage boosting clamp circuit U, and a buffer gate G3. The N-channel MOS transistor TN4 is used as the signal clamp transistor of the present invention.

The interface circuit of this embodiment operates at a power supply voltage VCC1 of 3 volts. Further, the power supply voltage VCC1 is applied to the pad P2 to which the bus line is connected.
A signal voltage from an external circuit operating at a higher power supply voltage VCC2, that is, a power supply voltage of 5 volts may be applied. This signal voltage may become higher than the power supply voltage VCC1 by 5 V for at least a certain period.

In the present embodiment, even if the H-state signal of 3 V corresponding to the power supply voltage VCC1 is input to the pad P2, the signal voltage of 5 V corresponding to the power supply voltage VCC2 is also applied. Even if input, a voltage obtained by adding the threshold voltage Vt of the N-channel MOS transistor TN4 to the power supply voltage VCC1 from the output OUT of the voltage boosting clamp circuit U, that is, a voltage of (3 volts + Vt). Is output. Therefore, even if the H state of 3 V is input to the pad P2 or the H state signal of 5 V is input, the H state signal of 3 V is input to the buffer gate G3. The Rukoto.

Therefore, in this embodiment, a voltage higher than the power supply voltage VCC1 will not be input to the buffer gate G3. Also, the N channel M
The threshold voltage Vt is applied to the gate of the OS transistor TN4.
However, although a voltage higher than the power supply voltage VCC1 may be applied, this is only temporary and deterioration due to the applied voltage can be further reduced. To the N-channel MOS transistor TN4, (V
The higher voltage of (CC1 + Vt) is applied only when the H state of 5 volts is input to the pad P2.

FIG. 3 is a circuit diagram of a third embodiment of the interface circuit to which the present invention is applied.

The interface circuit shown in FIG. 3 outputs a signal or inputs a signal to / from a bus interface circuit which operates at a power supply voltage VCC1 of 3 volts, particularly a bus line connected to the pad P3. It is a bus input / output interface circuit. The interface circuit of the third embodiment is a combination of the interface circuit of the first embodiment and that of the second embodiment, and each effect can be obtained.

FIG. 4 is a circuit diagram of a first example of the voltage / voltage boost clamp circuit used in the first to third embodiments.

The voltage boosting clamp circuit mainly consists of N
Channel MOS transistors TN10 and TN11,
It is composed of a boosting capacitor C.

The N-channel MOS transistor TN1
0 is a boost charging diode whose anode is connected to the power supply VCC1 side and whose cathode is connected to the boost capacitor C side. On the other hand, the anode of the N-channel MOS transistor TN11 has the boost capacitor C.
Is used as a voltage clamp diode whose cathode is connected to the power supply VCC1 side.

In the voltage boosting clamp circuit shown in FIG. 4, first, when an L state, for example, a voltage of 0 volt is input to the input IN, VCC1 or 3 volt is applied across the boosting capacitor C. Is applied. When the voltage is thus applied and the boosting capacitor C is sufficiently charged, the voltage of the output OUT becomes (VC
C1-Vt). It should be noted that this Vt is the N-channel MOS transistor TN2 shown in FIGS.
And TN4, which is the threshold voltage of the N-channel MOS transistor TN10.

After the boosting capacitor C has been sufficiently charged in this way, the H state is input to the input IN, and when the voltage of the input IN rises, the
The voltage on the output OUT side also rises. At this time, the N
The channel MOS transistor TN11 operates as a voltage clamp diode. That is, even if the voltage of the input IN rises and the voltage of the output OUT rises,
When the voltage of the output OUT becomes (VCC1 + Vt) or more, the N-channel MOS transistor TN11 is turned on, so that the voltage of the output OUT does not rise above (VCC1 + Vt).

As described above, in the voltage boosting clamp circuit shown in FIG. 4, when the L state is inputted to the input IN, the voltage of the output OUT is (VCC1-V).
From t), the voltage becomes about VCC1. On the other hand, the input I
When the H state is input to N, the voltage of the output OUT is (VCC1 + Vt) whether the H state voltage is equal to the power supply voltage VCC1 or the power supply voltage VCC2. ). Although the power supply voltage is VCC1, the voltage boosting clamp circuit has the power supply voltage VCC when the H state is input.
A voltage higher than 1 will be output.

FIG. 5 is a circuit diagram of a second example of the voltage boosting clamp circuit used in the first to third embodiments.

In the voltage boosting clamp circuit shown in FIG. 4, the N-channel MOS transistor TN is used.
10 is used as the boost charging diode, and the N-channel MOS transistor TN11 is used as the voltage clamp diode. However,
As shown in FIG. 5, actual diodes may be used as the boost charging diode and the voltage clamp diode. The same operation as that of the first example of the voltage boost clamp circuit can be performed in the second example of the voltage boost clamp circuit.

FIG. 6 is a circuit diagram of a third example of the voltage boosting clamp circuit used in the first to third embodiments.

As shown in FIG. 6, the third example of the voltage boosting clamp circuit is obtained by adding an N-channel MOS transistor TN12 to the circuit shown in FIG. The N-channel MOS transistor TN12
Is for causing the voltage on the output OUT side to follow the input IN side. From the power supply VCC1 to the boost capacitor C
It is to encourage the charging of. Therefore, in the third example of the voltage boosting clamp circuit, the boosting capacitor C is compared with the first and second examples of the voltage boosting clamp circuit.
It is possible to reduce the capacity of. Therefore, the third example of the voltage boosting clamp circuit is effective when the area of the boosting capacitor C cannot be taken sufficiently.

FIG. 7 is a circuit diagram of a fourth embodiment of an interface circuit to which the present invention is applied.

The fourth embodiment is a bus interface circuit for a bus line connected to the pad P1, especially a bus output interface circuit. In the fourth embodiment,
It operates with a power supply voltage VCC1 of 3 volts.

The interface circuit of this embodiment is similar to that of the first embodiment using the first example of the voltage boosting clamp circuit in comparison with the inverter gates I10 to I.
14, a NOR logic gate G1 and a NAND logic gate G2.

In the interface circuit of the fourth embodiment,
The terminal T2 is an enable input. That is, when the H state is input to the terminal T2 and the L state is input to the terminal T1, the L state is output from the pad P1. When the H state is input to the terminal T2 and the H state is input to the terminal T1, the pad P1
Outputs an H state. On the other hand, L to the terminal T2
When the state is input, the pad P1 is in the high impedance state regardless of the logical state input to the terminal T1.

FIG. 8 is a circuit diagram showing the operation at the time of outputting the H state in the fourth embodiment.

As shown in FIG. 8, when an H state of 3 volts equal to the power supply voltage VCC1 is input to the terminal T1 and an H state of 3 volts is input to the terminal T2, the pad P1 is applied. Is input to the H state of 3 volts. At this time, the output of the voltage boosting clamp circuit, that is, the gate of the N-channel MOS transistor TN2 becomes (3 V + Vt). Therefore, the N channel MO
When the S transistor TN2 is turned on, the voltage drop between the source and drain of the N channel MOS transistor TN2 does not matter.

FIG. 9 is a circuit diagram showing the operation at the time of outputting the L state in the fourth embodiment.

As shown in FIG. 9, the L state, that is, 0 volt is input to the terminal T1, and the terminal T2
When the H state of 3 volts is input to the pad P1,
Is 0 volts. At this time, the output of the voltage boost clamp circuit becomes (3 volts-Vt), and the power supply voltage V
It will be lower than CC1. Thus, although the voltage higher than the power supply voltage VCC1 is applied to the N-channel MOS transistor TN2 in the case shown in FIG. 8, in the case shown in FIG. A voltage lower than VCC1 is applied.

FIG. 10 is a circuit diagram showing the operation when the H state of 5 volts is input from the bus line side when the output in this embodiment is high impedance.

As shown in FIG. 10, even if a voltage higher than the power supply voltage VCC1 is applied from the pad P1, a high voltage such as the power supply voltage VCC2 is not applied to each part of the interface circuit. . For example, regarding the N-channel MOS transistor TN2 used as a signal clamp transistor,
The voltage applied between the source and drain and the gate is (5 volts- (3 volts-Vt)), which is about the power supply voltage VCC1.

FIG. 11 is a circuit diagram showing the operation of the fourth embodiment when its output is in the high impedance state and the L state is input from the pad P1.

As shown in FIG. 11, the pad P
Even when 1 is 0 volt, a high voltage such as the power supply voltage VCC2 is not applied to each part, and in this case, a voltage higher than the power supply voltage VCC1 is not applied. For example, the voltage applied to the gate of the N-channel MOS transistor TN2 is (3 V-Vt).

As described above, also in the fourth embodiment, even if the power supply voltage VCC2 equal to or higher than the power supply voltage VCC1 is applied to the pad P1 without using a transistor having a high breakdown voltage, each part is not affected. The applied voltage can be reduced and deterioration of the transistor or the like can be reduced.

FIG. 12 is a time chart showing the operation of the fourth embodiment.

In FIG. 12, the terminal T2 is set to H
A time chart is shown in which the terminal T1 is changed from the L state to the H state and then brought to the L state again while the state is kept, that is, the output of the interface circuit is enabled. Also, the horizontal axis of this time chart is
The unit is the nanosecond time axis. Further, in this time chart, as indicated by reference numerals N1 to N4 in FIG. 7, the node N1 of the input of the inverter I10,
The input node N2 of the inverter I13 and the input node N3 of the N-channel MOS transistor TN2.
And a node N4 connected to the pad P1 is a time chart of the voltage at each node.

First, at time 0 nanosecond in FIG. 12, the H state is input to the node 1 from the terminal T1. Along with this, the voltage of the node N1 rises to 3 volts. Further, the voltage of the node N2 is also 3 V after a little overshoot. The voltage of the node N3 is 4.
It is 7 volts. The voltage of the node N4 is approximately 3 volts.

After this, at time 100 nanoseconds, the voltage input from the terminal T1 to the node N1 is in the L state. At this time, the signal of the node N1 becomes 0 volt after about 5 nanoseconds. The voltage of the node N2 also becomes 0 V after a slight time delay. The node N3
Voltage drops to about 1.8 volts. The node N
For the voltage of 4, it drops to 0 volts.

As is clear from the time chart of FIG. 12, for example, the N-channel MOS transistor TN2 is used.
Is applied to the power supply voltage VCC1 (=
3 V) or more, but is lower than the power supply voltage VCC2 (= 5 V), and the application period of such a voltage higher than the power supply voltage VCC1 is limited. . Therefore, also in the fourth embodiment, it is possible to further reduce the deterioration of the transistor due to the high applied voltage.

FIG. 13 is a circuit diagram of the fifth embodiment of the interface circuit to which the present invention is applied.

The fifth embodiment uses the first example of the voltage boosting clamp circuit in the second embodiment. In addition, the buffer gate G3 of FIG.
Is a P-channel MOS transistor TP20 and an N-channel MOS transistor TN20 in this embodiment.
Further, it is based on the inverter gate I20.

FIG. 14 is a circuit diagram showing the operation at the time of inputting the H state of 5 volts according to the fifth embodiment.

As shown in FIG. 14, when the H state of 5 V is input to the pad P2, the output of the voltage boosting clamp circuit becomes (3 V + Vt). This voltage is input to the gate of the N channel MOS transistor TN4. The voltage of 5 V applied to the pad P2 is clamped to 3 V by the N-channel MOS transistor TN4.

FIG. 15 is a circuit diagram showing the operation of the fifth embodiment when the 0 volt L state is input.

As shown in FIG. 15, the pad P
When 0 volt L state is input to 2, the output of the voltage boost clamp circuit becomes (3 volt-Vt). The voltage is input to the gate of the N-channel MOS transistor TN4. The N-channel MOS transistor TN4 has a 0-volt L input from the pad P2.
The state signal is transmitted as it is.

As described above, also in the fifth embodiment, by clamping a voltage higher than the power supply voltage VCC1 input to the pad P2, the voltage applied to the internal transistor or the like is reduced. Is possible. At this time, the N-channel MOS used for clamping
Also for the transistor TN4, the power supply voltage VCC1
Although higher, the applied voltage is suppressed. In addition, the period in which a voltage higher than the power supply voltage VCC1 is applied is also shortened as described above, and the deterioration thereof is suppressed.

[0075]

As described above, according to the present invention, the power supply voltage VCC higher than the power supply voltage VCC1 of the interface circuit is supplied to the interface terminal connected to the outside.
Applying a signal voltage from an external circuit that operates in 2 causes a problem in an interface circuit that has been present for at least a certain period of time. Deterioration due to a higher applied voltage to the transistor used, the parasitic diode flowing in the forward direction. It is possible to obtain an excellent effect that it is possible to reduce the leakage current, the increase in the risk of occurrence of the latch-up phenomenon, and the like without using a transistor having a high breakdown voltage.

[Brief description of drawings]

FIG. 1 is a first interface circuit to which the present invention is applied.
Example circuit diagram

FIG. 2 is a second interface circuit to which the present invention is applied.
Example circuit diagram

FIG. 3 is a third interface circuit to which the present invention is applied.
Example circuit diagram

FIG. 4 is a circuit diagram of a first example of a voltage boost clamp circuit used in the first to third embodiments.

FIG. 5 is a circuit diagram of a second example of the voltage boosting clamp circuit used in the first to third embodiments.

FIG. 6 is a circuit diagram of a third example of the voltage boosting clamp circuit used in the first to third embodiments.

FIG. 7 is a fourth interface circuit to which the present invention is applied.
Example circuit diagram

FIG. 8 is a circuit diagram showing an operation at the time of outputting an H state in the fourth embodiment.

FIG. 9 is a circuit diagram showing an operation at the time of outputting an L state in the fourth embodiment.

FIG. 10 is a circuit diagram showing the operation of the fourth embodiment when the output is in a high impedance state and an H state of 5 volts is applied.

FIG. 11 is a circuit diagram showing an operation when 0 volt is applied in the high impedance state of the output in the fourth embodiment.

FIG. 12 is a time chart showing the operation of the fourth embodiment.

FIG. 13 is a circuit diagram of an interface circuit according to a fifth embodiment of the invention.

FIG. 14 is a circuit diagram showing an operation at the time of inputting an H state of 5 volts in the fifth embodiment.

FIG. 15 is a circuit diagram showing an operation at the time of inputting an L state of 0 volt in the fifth embodiment.

FIG. 16 is a circuit diagram of a first example of a conventional interface circuit.

FIG. 17 is a circuit diagram of a second example of a conventional interface circuit.

[Explanation of symbols]

TP1, TP20, TP30, TP31 ... P channel M
OS transistors TN1, TN20, TN30, TN31 ... N-channel M
OS transistors TN2, TN4 ... N-channel MOS transistors (used as signal clamp transistors to which the present invention is applied) TN3 ... N-channel MOS transistors (used for signal clamp) I1, I10 to I14, I20 ... Inverter gate G1 G3 ... Logic gate U ... Voltage boosting clamp circuit C ... Boosting capacitors D1, D2 ... Diodes T1 to T3 ... Terminals (connected to internal circuit) P1 to P3 ... Pads (to be externally connected as interface terminals) VCC1, VCC2 ... Power supply voltage or power supply (VCC1 <V
CC2) GND ... Ground N1-N4 ... Nodes

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H03K 19/0185 19/0944 8321-5J H03K 19/094 A

Claims (2)

[Claims] 1. A signal voltage from an external circuit operating at a power supply voltage VCC2 higher than a power supply voltage VCC1 of the interface circuit is applied to an externally connected interface terminal for at least a certain period, According to the voltage input to the gate in an interface circuit that performs at least one of signal input and signal output from the outside via the interface terminal and the signal output to the outside via the interface terminal. When a signal clamp transistor that clamps to a voltage and an H state is input to its input IN, the threshold voltage V of the signal clamp transistor is added to the power supply voltage VCC1.
a voltage boosting clamp circuit that outputs a voltage of about the voltage added with t and outputs a voltage equal to or lower than the power supply voltage VCC1 when the L state is input, and the output of the voltage boosting clamp circuit is the signal clamp transistor. And the signal clamp transistor is inserted and connected between the interface terminal and a transistor of another internal circuit connected to the interface terminal. Interface circuit to do. 2. The voltage boost clamp circuit according to claim 1, further comprising a boost capacitor C, a boost charging diode D1, and a voltage clamp diode D2 having a threshold voltage substantially equal to the threshold voltage Vt of the signal clamp transistor. The step-up charging diode is provided such that one terminal of the step-up capacitor C is the input IN, and the other terminal of the step-up capacitor C is between the power source of the power supply voltage VCC1 and its anode is on the side of the power source. D1 is connected, the voltage clamp diode D2 is connected so that its anode is on the boost capacitor C side, and the boost charging capacitor C is connected to the boost charging diode D1 and the voltage clamp diode D2. Is the output of the voltage boost clamp circuit. Scan circuit.