JPH05206158A - Bipolar transistor and manufacture thereof, and semiconductor device provided with bipolar transistor and mos transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To form a bipolar transistor having high performance and a small forming area in a silicon layer in which a back gate type MOS transistor can be formed on an SOI substrate. CONSTITUTION:A p-type base region 15 is formed on an n-type silicon layer 12 of a thin film SOI substrate 11, an n<+> type emitter region 16 is formed on the upper layer, an n<+> type collector region 17 is formed on the layer 12 at both or one side of the region 15 through part of the layer 12, and a p<+> type base leading electrode 19 to be connected to the region 15 is provided on a lower insulating layer 18 of the region 15. This semiconductor device has a bipolar transistor 1 and a back gate type MOS transistor having another silicon layer of the substrate 11 as a channel on the substrate 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor, a method of manufacturing the same, a bipolar transistor and an MO transistor.
The present invention relates to a semiconductor device having an S transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art Large-scale integrated circuits are required to have a larger scale and higher performance. Among them, a Bi-CMOS device has been proposed in which a CMOS transistor capable of high integration with low power consumption and a bipolar transistor excellent in high-speed operability are mounted on the same substrate.

However, in a field effect type MOS transistor (hereinafter referred to as MOSFET) whose gate length is miniaturized to a sub-half micron, there is a problem that the subthreshold characteristic is deteriorated by the short channel effect. Therefore, as a solution to this problem, a MOS transistor having a fully depleted thin film SOI structure has been proposed. In this complete depletion type thin film SOI structure MOS transistor, the thickness of the SOI structure silicon thin film is made equal to or less than the thickness of the depletion layer so that the drain electric field is terminated at the gate and does not reach the source region. ing. Therefore, the deterioration of the subthreshold characteristics due to the short channel effect can be suppressed.

Further, in the MOSFET having the thin film SOI structure, the bending of the band in the silicon thin film at the time of forming the inversion layer is suppressed to reduce the surface scattering of carriers. Therefore, carrier mobility is increased. In particular, a so-called double-gate structure MOSFET in which a silicon thin film of an SOI substrate is sandwiched by gate electrodes has a larger transconductance gm than a MOSFET of a single gate structure formed in a silicon thin film of an SOI substrate.

Next, a so-called double-gate structure MOSFET in which a silicon thin film on an SOI substrate is sandwiched between gate electrodes
Will be described with reference to FIG. As shown, the substrate 111
An insulating layer 112 made of silicon oxide is formed on top. A silicon thin film 113 is formed on the insulating layer 112. A channel forming region 114 is formed in the silicon thin film 113. A source region 115 is formed in the silicon thin film 113 on one side of the channel forming region 114, and a drain region 1 is formed on the other side.
16 are formed. Further, the channel forming region 114
A back gate electrode 118 is formed under the back gate insulating film 117. A front gate electrode 120 is formed above the channel forming region 114 via a front gate insulating film 119.

An insulating film 121 is formed on the entire surface on the side of the front gate electrode 120. Contact holes 122 and 123 are provided in the insulating film 121 on the source and drain regions 115 and 116. Electrodes 124 and 125 connected to the source / drain regions 115 and 116 through the contact holes 122 and 123 are formed. As described above, the so-called double gate structure MOSF in which the silicon thin film 113 of the SOI substrate is sandwiched between the back gate electrode 118 and the front gate electrode 120.
ET110 is formed.

A bipolar transistor that can be mounted together with the MOSFET 110 will be described with reference to the schematic sectional view of FIG. 10 and the layout diagram of FIG. As shown in FIG. 10, the SOI substrate 131 is formed of an insulating layer 132 and an n-type silicon thin film 133. Element isolation regions 134 and 135 are formed in the n-type silicon thin film 133. N-type silicon thin film 13 on the element isolation region 134 side
A silicon oxide film 136 is formed on the third layer. In addition, the upper surface of the n-type silicon thin film 133 is n-shaped so as to overlap a part of the silicon oxide film 136.
^{A +} collector electrode 137 is provided. A sidewall insulating film 138 is formed on the sidewall of the n ⁺ collector electrode 137 on the element isolation region 134 side.

On the element isolation region 134 side of the n-type silicon thin film 133, an n ⁺ emitter region 139 is formed. Further, a p-type base region 140 is formed in the n-type silicon thin film 133 below the sidewall insulating film 138 on the n ⁺ emitter region 139 side. Further, as shown in FIG. 11, in the p-type base region 140, p
The base contact portions 141 and 142 are connected. The p-type base contact portions 141 and 142 are formed of a diffusion layer in which p-type impurities are diffused, similar to the p-type base region 140. In addition, the element isolation region 135
The n-type silicon thin film 133 on the side is the n-type collector region 143.
become. As described above, the lateral npn bipolar transistor 130 is formed.

The lateral npn bipolar transistor 1 described above.
Since 30 is formed on the n-type silicon thin film 133 of the SOI substrate 131, the MOSFET described in FIG.
(110) and the lateral npn bipolar transistor 1
30 and 30 can be mounted on the same SOI substrate.

[0010]

However, in the lateral npn bipolar transistor described above, the width of the sidewall insulating film is the width of the base region. Therefore, the width of the base region is 100 nm or less, and it is necessary to make contact with the base region away from the base region. As a result, the parasitic capacitance increases and the electrical characteristics deteriorate. Moreover, since the base region becomes large, the element area increases, and high integration cannot be achieved.

It is an object of the present invention to provide a bipolar transistor excellent in electrical characteristics and high integration, a manufacturing method thereof, a semiconductor device having the bipolar transistor and a MOS transistor mounted therein, and a manufacturing method thereof. ..

[0012]

The present invention has been made to achieve the above object. That is, as a bipolar transistor, a base region and an emitter region are formed in the upper layer of a silicon layer of an SOI substrate, and a collector region is formed in a silicon layer on both sides or one side of the base region via a part of this silicon layer. A base lead electrode connected to the base region is formed in the insulating layer of the SOI substrate below the base region.

As a method of manufacturing the above bipolar transistor, after forming a first insulating layer on a silicon substrate, a groove is formed in the first insulating layer. Next, after forming a base extraction electrode in the groove, a second insulating layer is formed on the entire surface on the groove forming side to form an insulating layer. Then, a part of the silicon substrate is removed to form a silicon layer, and then a separation pattern and an insulating film are formed on the silicon layer. Next, collector regions are formed on both sides or one side of the silicon layer on the base take-out electrode, and then the insulating film, the polycrystalline silicon film, and the separation pattern on the portion where the emitter region is formed are removed. An emitter contact portion is formed. Next, after forming a sidewall insulating film on the sidewall of the emitter contact portion, a lead electrode forming film is formed. Then, impurities are diffused from the extraction electrode formation film to form a base region and an emitter region in the silicon layer, and then an extraction electrode formation film is formed using the extraction electrode formation film.

A semiconductor device having a bipolar transistor and a MOS transistor mounted thereon includes the bipolar transistor described above, a gate electrode formed on the upper surface of a second silicon layer formed on the same SOI substrate via a gate insulating film, and a gate. A bipolar transistor comprising a source / drain region formed on the second silicon layer on both sides of the electrode and a back gate electrode formed in the insulating layer of the SOI substrate via a back gate insulating film connected to the lower surface of the silicon layer; It is composed of

As a method of manufacturing the above semiconductor device, MO
After forming a back gate insulating film on the silicon substrate in the S transistor forming region and then forming a first insulating layer on the entire surface of the semiconductor substrate, a first insulating layer on the bipolar transistor forming region and the MOS transistor forming region is formed. To form a groove. Next, a base lead electrode is formed in the groove on the side of the bipolar transistor formation region, a back gate electrode is formed in the groove on the side of the MOS transistor formation region, and then a second insulation layer is formed on the entire surface on the side of the first insulation layer. To do. Then, a portion of the silicon substrate is removed to remove the SOI
A first silicon layer and a second silicon layer of the substrate are formed. After that, a separation pattern is formed on the first silicon layer, and a gate insulating film is formed on the upper surface of the second silicon layer. Further, a polycrystalline silicon film and an insulating film are formed, and then a collector region is formed in the first silicon layer. Next, an emitter contact portion is formed on a portion where an emitter region is formed, a collector lead electrode is formed of a polycrystalline silicon film, and a gate electrode is formed of a polycrystalline silicon film. Subsequently, an emitter sidewall insulating film is formed on the sidewall of the emitter contact portion, a polycrystalline silicon film is formed on the entire surface on the insulating film side, and then a base region and an emitter region are formed in the first silicon layer, and a gate is formed. Source / drain regions are formed in the second silicon layer on both sides of the electrode. After that, an emitter lead-out electrode is formed of a polycrystalline silicon film, and source / drain lead-out electrodes are formed on both sides of the gate electrode.

[0016]

The bipolar transistor having the above-described structure is an SOI
By forming the base take-out electrode inside the groove provided in the insulating layer of the substrate, forming the base region on the base take-out electrode, and further forming the collector region on both sides or one side of the base region, It can be taken out near the base area. Therefore, the parasitic capacitance is reduced and the electrical characteristics are improved. Further, since the base region is small, the formation area of the bipolar transistor is reduced.

In the method of manufacturing a bipolar transistor described above, after the groove is formed in the first insulating layer which becomes the insulating layer of the SOI substrate, the base lead electrode is formed in this groove, so that the base region and the base lead electrode are separated from each other. Formed in close proximity.

In the above semiconductor device, the base take-out electrode is formed inside the groove provided in the insulating layer of the SOI substrate, and the base region is formed on the base take-out electrode.
The base electrode can be taken out easily. Therefore, the parasitic capacitance is reduced and the electrical characteristics are improved. Further, since the base region becomes smaller, the formation area of the bipolar transistor can be reduced. Furthermore, since the silicon layer is formed thin, it becomes possible to form a back gate type MOS transistor on the same SOI substrate.

In the method of manufacturing a semiconductor device described above, the thin film SO
Since a groove is formed in the insulating layer of the I substrate, a base take-out electrode is formed inside the groove, and a silicon layer in which a base region is formed is formed on the base take-out electrode.
It is not necessary to form a thick silicon layer of the OI substrate. Therefore, since the silicon layer in the MOS transistor formation region is also formed at the same time, it becomes easy to manufacture the bipolar transistor and the MOS transistor on the same SOI substrate in substantially the same process.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to the schematic sectional view of FIG. As shown in FIG. 1, for example, a thin film SOI substrate 11 is used as the SOI substrate. This thin film SOI substrate 1
Element isolation regions 13 and 14 are formed in a first conductivity type (hereinafter referred to as n-type) silicon layer 12 which constitutes the element 1.
A second conductivity type (hereinafter referred to as p-type) base region 1 is formed in a part of the n-type silicon layer 12 between the element isolation regions 13 and 14.
5 is formed. An n ⁺ emitter region 16 is formed in the upper layer of the p-type base region 15. Further, on the n-type silicon layer 12 on both sides or one side of the p-type base region 15, an n ⁺ collector region 17 is formed via a part of the n-type silicon layer 12.

Further, in the insulating layer 18 constituting the thin film SOI substrate 11 below the p-type base region 15, a p ⁺ base lead-out electrode 19 connected to the p-type base region 15 is formed.
Are formed. The p ⁺ base during under the insulating layer 18 of the take-out electrode 19, p ⁺ base contact electrode 19
The low-resistance layer 20 connected to is formed.

A separation pattern 21 is formed on a part of the upper surface of the n-type silicon layer 12. While overlapping to the separation pattern 21, on each side of the isolation region 13 and 14, n ⁺ collector contact electrode 22 connected to the n ⁺ collector region 17 are formed. Further, an insulating film 23 is formed on each n ⁺ collector extraction electrode 22, and an emitter contact portion 24 is formed on the insulating film 23 on the n ⁺ emitter region 16. An emitter sidewall insulating film 25 is formed on the sidewall of the emitter contact portion 24. Furthermore the emitter contact 24, n ⁺ emitter lead-out electrode 26 to be connected to the n ⁺ emitter region 16 is formed. The bipolar transistor 1 is configured as described above. In the above description, the first conductivity type is the n-type and the second conductivity type is the second type.
Although the conductivity type is described as p-type, conversely, the first conductivity type is p-type.
The second conductivity type may be the n-type.

The bipolar transistor 1 is a thin film S.
By forming the p ⁺ base extraction electrode 19 in the OI substrate 11 and forming the n-type silicon layer 12 of the thin film SOI substrate 11 in a state of being connected to the p ⁺ base extraction electrode 19, the intrinsic region (p-type base region) is formed. 15, n ⁺ emitter region 16, n ⁺ collector region 17) and a minimum contact region (p ⁺ base extraction electrode 19). Therefore, the formation area of the bipolar transistor 1 is reduced. Further, since the periphery of the bipolar transistor 1 is almost covered with an insulator, the performance is improved.

Next, a method of manufacturing the bipolar transistor 1 will be described with reference to manufacturing process diagrams (No. 1) to (No. 3) of FIGS. As shown in (1) of FIG.
Process. In this process, first, for example, a normal LOC
By the OS oxidation method, element isolation regions 13 and 14 are formed in a surface layer of a first conductivity type (hereinafter referred to as n type) silicon substrate 31 to a thickness of 200 nm, for example.

After that, the first insulating layer 3 is formed on the entire surface on the element isolation regions 13 and 14 side by, for example, a chemical vapor deposition method.
Form 2. The first insulating layer 32 is formed of, for example, silicon oxide. After that, a resist is applied to form a resist film (not shown) having a flat surface, and then the resist film and the upper layer of the first insulating layer 32 are etched back to perform a film of the first insulating layer 32. The thickness is, for example, 300 nm
˜400 nm, and the surface of the first insulating layer 32 is flattened. Then, a groove 33 reaching the n-type silicon substrate 31 is formed in a part of the first insulating layer 32 by usual photolithography and etching. The etching is performed under etching conditions in which the selection ratio of silicon oxide to silicon is large.

Next, the second step is performed. In this process,
First, as shown in (2) of FIG. 2, for example, a silicon oxide film (34) is formed by, for example, a chemical vapor deposition method. Subsequently, the silicon oxide film (34) is subjected to an etch back process to form a sidewall 35 on the sidewall of the groove 33. The sidewalls 35 provide a margin for alignment between the p-type base region (15) and the p ⁺ base take-out region (19) described later.

Then, for example, a p-type polycrystalline silicon film 36 is formed inside the groove 33 and on the upper surface of the first insulating layer 32 by, for example, a chemical vapor deposition method. After that, a resist is applied to form a resist film (not shown) having a flat surface, and then a portion indicated by a chain double-dashed line of the resist film and the polycrystalline silicon film 36 is removed by an etch back process to form a groove. Polycrystalline silicon film 3 inside 33
A p ⁺ base take-out electrode 19 of 6 is formed. The p ⁺ base take-out electrode 19 has a thickness of 50 nm to 100 n.
It is formed to a thickness of m. The polycrystalline silicon film 3
6 may introduce an n-type impurity [for example, boron (B ⁺ )] after the film formation by, for example, an ion implantation method.

As shown in the subsequent Figure 2 (3), in order to reduce the resistance of the p ⁺ base contact electrode 19, in the trench 33 on the p ⁺ base contact electrode 19, selective growth, for example, tungsten (W) Let the tungsten electrode 37
To form.

Then, for example, by chemical vapor deposition,
A second insulating layer 38 made of a silicon oxide film is formed on the entire surface on the first insulating layer 32 side. The insulating layer 18 is formed by the first insulating layer 32 and the second insulating layer 38.
Then, after polishing the surface of the second insulating layer 38 to be flat,
For example, a single crystal silicon wafer 39 is bonded as a base wafer by a normal wafer bonding method.

Then, as shown in FIG. 3D, in the third step, the n-type silicon substrate 31 is exposed until the element isolation regions 13 and 14 are exposed by, for example, grinding and polishing (normal lapping). The portion indicated by the chain double-dashed line is removed. At this time, the element isolation regions 13 and 14 serve as polishing stoppers. Then, the n-type silicon layer 12 is formed between the element isolation regions 13 and 14. At this time, the thickness of the n-type silicon layer 12 is usually about 1/2 of the thickness of the element isolation regions 13 and 14.
become. The diagram shown in (4) of FIG. 3 is shown in an inverted state of the diagram shown in (3) of FIG. Further, the drawings shown in (5) and subsequent figures in FIG. 3 are also shown in an inverted state of the drawing shown in (3) in FIG.

Next, as shown in FIG. 3 (5), a fourth step is performed. In this step, first, the isolation insulating film 40 is formed on the surface layer of the n-type silicon layer 12 by, for example, a normal thermal oxidation method. After that, by the usual photolithography and etching, 2 of the isolation insulating film 40 is removed.
The part indicated by the dotted chain line is removed to form the separation pattern 41. It is also possible to form the polycrystalline silicon film 42 on the upper surface side of the isolation insulating film 40 in order to prevent impurities from entering the isolation insulating film 40 during photolithography.

Subsequently, as shown in (6) of FIG. 3, a fifth step is performed. In this step, first, a polycrystalline silicon film 43 is formed on the entire surface of the separation pattern 41 side by a normal chemical vapor deposition method. Subsequently, for example, arsenic (As ⁺ ) is introduced into the polycrystalline silicon film 43 as an n-type impurity by a normal ion implantation method. Then, an n ⁺ collector region 17 is formed on the n-type silicon layer 12 on one side or both sides of the element isolation regions 13 and 14 by a normal diffusion process.

After that, for example, an insulating film 44 made of silicon oxide is formed on the upper surface of the polycrystalline silicon film 43 by an ordinary chemical vapor deposition method. Then, the insulating film 44 is formed by ordinary photolithography and etching.
Then, the portion indicated by the chain double-dashed line between the polycrystalline silicon film 43 and the separation pattern 41 is removed to form the emitter contact portion 24. At the same time, the n ⁺ collector take-out electrode 4 connected to the n-type silicon layer 12 by the polycrystalline silicon film 43.
5 is formed.

Then, as shown in (7) of FIG. 4, a sidewall made of silicon oxide is formed on the entire surface on the side of the insulating film 44 including the inner wall of the emitter contact portion 24 by a normal chemical vapor deposition method. The insulating film 46 is formed.
After that, the sidewall insulating film 46 is etched back by a normal etchback process, and the emitter sidewall insulating film 2 is formed on the sidewall of the emitter contact portion 24.
5 is formed.

Subsequently, as shown in FIG. 4 (8), a sixth step is performed. In this step, the extraction electrode forming film 47 made of a polycrystalline silicon film is formed by, for example, a normal chemical vapor deposition method. Then, for example, by a normal ion implantation method, in the extraction electrode forming film 47,
For example, boron (B ⁺ ) is introduced as the p-type impurity. Then, an annealing treatment is performed to diffuse the p-type impurities from the extraction electrode forming film 47 of the emitter contact portion 24 to the upper layer of the n-type silicon layer 12 to form the p-type base region 15.

After that, for example, arsenic (As ⁺ ) is introduced as an n-type impurity into the extraction electrode forming film 47 by a normal ion implantation method. Then, annealing treatment is performed to diffuse the n-type impurities from the extraction electrode forming film 47 of the emitter contact portion 24 to the upper layer of the p-type base region 15 to form the n ⁺ emitter region 16.

Then, the extraction electrode forming film 4 is formed by, for example, ordinary photolithography and etching.
The portion indicated by the two-dot chain line 7 is removed, and the n ⁺ emitter extraction electrode 26 is formed by the extraction electrode forming film 47.

The first conductivity type (for example, n type) impurities and the second conductivity type (for example, p type) impurities in the extraction electrode forming film 47 are simultaneously subjected to the same diffusion treatment to simultaneously form the n type silicon layer. 12 and diffuses into the p-type base region 1
It is also possible to form 5 and the n ⁺ emitter region 16.

Thereafter, as shown in FIG. 4 (9), an interlayer insulating film 50 made of silicon oxide is formed by, for example, a chemical vapor deposition method. Further, by photolithography and etching, the n ⁺ collector take-out electrode 4
5 and the n ⁺ emitter take-out electrode 26, contact holes 51 and 52 are formed, and then a base electrode (not shown) is formed in the contact hole 51 and a contact hole is formed by a normal metal electrode forming method. 5
2, an emitter electrode (not shown) is formed.

In the manufacturing method described above, p of the bipolar transistor 1 is formed in the first insulating layer 32 of the thin film SOI substrate 11.
^{Since the +} base extraction electrode 19 is formed and then the n-type silicon layer 12 of the thin film SOI substrate 11 is formed, the thickness of the n-type silicon layer 12 can be reduced. In the above description, the first conductivity type is n-type and the second conductivity type is p-type. However, conversely, the first conductivity type may be p-type and the second conductivity type may be n-type.

Next, as a second embodiment, the thin film SOI described above is used.
A semiconductor device in which the bipolar transistor 1 and the MOS transistor are mounted on the substrate 11 will be described with reference to the schematic cross-sectional view of FIG. As shown in the figure, on the thin film SOI substrate 11, the bipolar transistor 1 described in the first embodiment and the MOS transistor 2 described below are mounted. Since the structure of the bipolar transistor 1 is the same as that described in the first embodiment, the description thereof is omitted here.

Next, the structure of the MOS transistor 2 will be described. As shown in the figure, the thin film SOI substrate 11 has a first silicon layer 6 on which the bipolar transistor 1 is formed.
An n-type second silicon layer 61 is formed at a position corresponding to 0 (corresponding to the silicon layer 12 of the first embodiment) with the element isolation region 14 interposed therebetween. This second silicon layer 61
A gate insulating film 62 is formed on the upper surface of the. The gate insulating film 62 is made of, for example, a silicon oxide film.
A gate electrode 63 is formed on the upper surface of the gate insulating film 62. The gate electrode 63 is made of, for example, polycrystalline silicon.

The second electrodes on both sides of the gate electrode 63 are also provided.
In the silicon layer 61, source / drain regions 64 and 65 of the second conductivity type (for example, p ⁺ ) are formed. Further, a back gate insulating film 66 is formed on the lower surface of the second silicon layer 61. This back gate insulating film 66
Is made of, for example, a silicon oxide film. Further, in the insulating layer 18 of the thin film SOI substrate 11, a back gate electrode 67 connected to the lower surface of the back gate insulating film 66 is formed. In this way, the MOS transistor 2 is configured.

Therefore, as described above, the semiconductor device 3 on which the bipolar transistor 1 and the MOS transistor 2 are mounted is formed. In the above description, the first conductivity type is n-type and the second conductivity type is p-type. However, conversely, the first conductivity type may be p-type and the second conductivity type may be n-type.

In the bipolar transistor 1, by forming the p ⁺ base take-out electrode 19 on the insulating layer 18, the thickness of the first silicon layer 60 of the thin film SOI substrate 11 can be reduced. Therefore, it is possible to form the high-performance MOS transistor 2 having a back gate structure on the same thin film SOI substrate 11. Further, as in the first embodiment, the formation area of the bipolar transistor 1 becomes small.

In the semiconductor device 3 described above, the MOS transistor 2 has been described as an NMOS transistor.
A similar structure can be formed with the S transistor. Further, by providing a PMOS transistor in the same manner as the NMOS transistor to form a CMOS transistor, the semiconductor device 3 is provided in the Bi-CMOS.
It can also be a device.

Next, a method of manufacturing the semiconductor device 3 will be described with reference to FIG.
-(1)-(3) of manufacturing process drawing of FIG. 8 demonstrates. As shown in FIG. 6A, the first step is performed.
In this step, first, a first conductivity type (hereinafter referred to as n type) silicon substrate 31 is formed by, for example, a normal LOCOS oxidation method.
Of the bipolar transistor formation region 71 and the MO
The element isolation regions 13, 14, 73 for separating the S transistor formation region 72 from each other are formed to have a thickness of 200 nm, for example.

Then, for example, by a conventional thermal oxidation method,
The back gate insulating film 7 is formed on the surface of the n-type silicon substrate 31.
4 is formed. Then, the polycrystalline silicon film 7 is formed on the entire surface on the side of the back gate insulating film 74 by chemical vapor deposition.
5 is formed into a film. The polycrystalline silicon film 75 prevents the back gate insulating film 74 from being contaminated by, for example, a resist in a photolithography process to be performed later. Then, by photolithography and etching, the polycrystalline silicon film 75 (the portion indicated by the two-dot chain line) and the back gate insulating film 74 (the portion indicated by the one-dot chain line) on the bipolar transistor formation region 71 are removed. And MO
The back gate insulating film 66 is formed of the back gate insulating film 74 on the S transistor formation region 72.

Thereafter, as shown in FIG. 6B, the element isolation regions 13 and 1 are formed by, for example, a chemical vapor deposition method.
The first insulating layer 32 is formed on the entire surface on the 4,73 side. The first insulating layer 32 is formed of, for example, silicon nitride.
After that, a resist is applied to form a resist film (not shown) having a flat surface, and then the resist film and the upper layer of the first insulating layer 32 (a portion indicated by a chain double-dashed line) are etched back. , The thickness of the first insulating layer 32 is, for example, 3
The surface is flattened while being set to 00 nm to 400 nm.

Then, by ordinary photolithography and etching, trenches 33 and 76 reaching the n-type silicon substrate 31 are formed in a part of the first insulating layer 32. The above etching is performed under etching conditions in which the selection ratio of silicon nitride to the n-type silicon substrate 31 is large.

Then, the groove 3 is formed by chemical vapor deposition.
A silicon oxide film 34 is formed on the entire inside of 3,76 and the first insulating layer 32 side. Then, the portion indicated by the chain double-dashed line of the silicon oxide film 34 is etched back to form the groove 33,
A sidewall 35 is formed on each sidewall of 76.

Next, the second step is performed. In this process,
First, as shown in (3) of FIG. 6, for example, by a chemical vapor deposition method, for example, a p-type polycrystal is formed inside the groove 33, inside the groove 76 and on the upper surface of the first insulating layer 32. A silicon film 36 is formed. After that, a resist is applied to form a resist film (not shown) having a flat surface, and then a portion indicated by a chain double-dashed line of the resist film and the polycrystalline silicon film 36 is removed by an etch back process to form a groove. A p ⁺ base take-out electrode 19 made of the polycrystalline silicon film 36 is formed inside 33, and a back gate electrode 67 made of the polycrystalline silicon film 36 is formed inside the groove 76.
The p ⁺ base take-out electrode 19 is, for example, 50 nm to 1
It is formed to a thickness of 00 nm. In addition, the back gate electrode 6
7 is formed to have a thickness of 300 nm to 400 nm, for example. The polycrystalline silicon film 36 may be formed into a p-type polycrystalline silicon film by introducing a p-type impurity [for example, boron (B ⁺ )] by, for example, an ion implantation method after the film formation.

Thereafter, as shown in FIG. 6D, in order to lower the resistance of the p ⁺ base take-out electrode 19 and the back gate electrode 67, the groove 33 on the p ⁺ base take-out electrode 19 is formed.
Tungsten (W), for example, is selectively grown in the inside of the trench and in the groove 76 on the back gate electrode 67 to form the tungsten electrodes 37 and 77. In this case, for example,
By increasing the thickness of the first insulating layer 32, the groove 33,
Form 76 deep.

Then, for example, by chemical vapor deposition,
A second insulating layer 38 made of a silicon oxide film is formed on the entire surface on the first insulating layer 32 side. The insulating layer 18 is formed by the first insulating layer 32 and the second insulating layer 38.
Then, after polishing the surface of the second insulating layer 38 to be flat,
For example, a single crystal silicon wafer 39 is bonded as a base wafer by a normal wafer bonding method.

Then, as shown in FIG. 7 (5), in the third step, the n-type silicon substrate is exposed until the element isolation regions 13, 14, 73 are exposed by, for example, grinding and polishing (normal lapping). The part indicated by the two-dot chain line 31 is removed. At this time, the element isolation regions 13, 14, 73 serve as polishing stoppers. Then, the first silicon layer 60 is formed between the element isolation regions 13 and 14, and the element isolation region 1 is formed.
A second silicon layer 61 is formed between 4 and 73. At this time, the thickness of the first and second silicon layers 60, 61 is normally about 1/2 of the thickness of the element isolation regions 13, 14, 73. The diagram shown in (5) of FIG. 7 is shown in an inverted state of the diagram shown in (4) of FIG. Further, the drawings shown in (6) and subsequent figures in FIG. 7 are also shown in a state where the drawing shown in (4) in FIG. 6 is inverted.

Then, as shown in FIG. 7 (6), a fourth step is performed. In this step, first, the gate insulating film 78 is formed on each surface layer of the first and second silicon layers 60 and 61 by, for example, a normal thermal oxidation method. Then, a film 79 for forming a gate of a polycrystalline silicon film is formed on the entire surface on the gate insulating film 78 side by, for example, a normal chemical vapor deposition method. After that, the portion indicated by the alternate long and two short dashes line between the gate insulating film 78 and the gate forming film 79 is removed by ordinary photolithography and etching, and a part of the upper surface of the first silicon layer 60 for the gate The insulating film 78 forms the separation pattern 41. At the same time, the gate forming pattern 80 is formed by removing the portion of the gate forming film 79 and the gate insulating film 78 indicated by the alternate long and two short dashes line so as to cover the second silicon layer 61.

Subsequently, as shown in FIG. 7 (7), a fifth step is performed. In this step, first, the polycrystalline silicon film 43 is formed on the entire surface of the separation pattern 41 side and the gate formation pattern 80 side by a normal chemical vapor deposition method. Then, as a n-type impurity, for example, arsenic (A
s ⁺ ) is introduced. And by the normal diffusion process,
An n ⁺ collector region 17 is formed in the upper layer of the first silicon layer 60 on one side or both sides of the element isolation regions 13 and 14.

After that, for example, an insulating film 44 made of silicon oxide is formed on the upper surface of the polycrystalline silicon film 42 by an ordinary chemical vapor deposition method. Then, the insulating film 44 is formed by ordinary photolithography and etching.
Then, the portion indicated by the chain double-dashed line between the polycrystalline silicon film 43 and the separation pattern 41 is removed to form the emitter contact portion 24. At the same time, with the polycrystalline silicon film 43, the first
An n ⁺ collector take-out electrode 45 connected to the silicon layer 60 is formed with the insulating film 44 placed thereon. Further, the gate electrode 63 is formed by the polycrystalline silicon film 43 and the film 79 for forming a gate, and the gate insulating film 7 is formed.
At 8, the gate insulating film 62 is formed.

Then, as shown in FIG. 8 (8), a sidewall made of silicon oxide is formed on the entire surface on the insulating film 44 side including the inner wall of the emitter contact portion 24 by a normal chemical vapor deposition method. The insulating film 46 is formed.
After that, the sidewall insulating film 46 is etched back by a normal etchback process, and the emitter sidewall insulating film 2 is formed on the sidewall of the emitter contact portion 24.
5 and the gate side wall insulating film 81 is formed on the side wall of the gate electrode 63. When forming the MOS transistor 2 in the LDD structure, before forming the sidewall insulating film 46, the gate electrode 63 is formed.
Ion implantation for forming LDD is performed on the second silicon layer 61 on both sides of.

Subsequently, as shown in FIG. 8 (9), a sixth step is performed. In this step, the extraction electrode forming film 47 made of a polycrystalline silicon film is formed by, for example, a normal chemical vapor deposition method. Then, for example, by a normal ion implantation method, in the extraction electrode forming film 47,
For example, boron (B ⁺ ) is introduced as the p-type impurity. Then, an annealing treatment is performed to diffuse the p-type impurities from the extraction electrode forming film 47 of the emitter contact portion 24 to the upper layer of the first silicon layer 60, and to the n ⁺ collector region 17 with the first impurity. The p-type base region 15 is formed via a part of the silicon layer 60, and p ⁺ is formed on the second silicon layer 61 on both sides of the gate electrode 63.
Source / drain regions 64 and 65 are formed.

After that, for example, arsenic (As ⁺ ) is introduced as an n-type impurity into the upper emitter extraction electrode forming film 47 forming the emitter region by a normal ion implantation method. Then, an annealing process is performed,
The n-type impurity is diffused from the extraction electrode forming film 47 of the emitter contact portion 24 to the upper layer of the p-type base region 15 to form the n ⁺ emitter region 16. In addition, the p ⁺ source / drain region 6 is formed by an ordinary ion implantation method.
Boron (B ⁺ ) is introduced as a p-type impurity into the lead-out electrode forming film 47 on the layers 4, 65.

Then, the extraction electrode forming film 4 is formed by, for example, ordinary photolithography and etching.
7 is removed to form the n ⁺ emitter take-out electrode 26 with the take-out electrode forming film 47, and p ⁺ is connected to the p ⁺ source / drain regions 64 and 65 on both sides of the gate electrode 63. Source / drain extraction electrodes 82 and 83 are formed.

As described above, the bipolar transistor 1 and the MOS transistor 2 are formed to form the semiconductor device 3. The first conductivity type (for example, n type) impurities and the second conductivity type (for example, p type) impurities in the extraction electrode forming film 47 are simultaneously formed in the first silicon layer 60 by the same diffusion process. It is also possible to form the p-type base region 15 and the n ⁺ emitter region 16 by diffusion.

Thereafter, as shown in (10) of FIG. 8, an interlayer insulating film 50 made of silicon oxide is formed by, for example, a chemical vapor deposition method. Further, by photolithography and etching, contact holes 51 and 52 are formed on the n ⁺ collector extraction electrode 45 and the n ⁺ emitter extraction electrode 26, and the p ⁺ source / electrode is formed.
After forming contact holes 84, 85, (not shown) on the drain extraction electrodes 82, 83 and on the gate electrode 63, a collector metal electrode (not shown) is formed in the contact hole 51 by a normal metal electrode forming method. ) Is formed, an emitter metal electrode (not shown) is formed in the contact hole 52, and the contact holes 84, 85 are formed.
A source / drain metal electrode (not shown) is formed in and a gate metal electrode (not shown) is formed in a contact hole (not shown).

In the above manufacturing method, the p ⁺ base take-out electrode 19 of the bipolar transistor 1 is formed inside the groove 33 formed in the first insulating layer 32 of the thin film SOI substrate 11, and is formed in the first insulating layer 32. Since the back gate electrode 67 of the MOS transistor 2 is formed inside the groove 76, the first and second silicon layers 60 and 61 of the thin film SOI substrate 11 are formed.
It becomes possible to form a thin film. In the above description, the first conductivity type is n-type and the second conductivity type is p-type. However, conversely, the first conductivity type may be p-type and the second conductivity type may be n-type.

In the above manufacturing, the MOS transistor 1
Has been described with an NMOS transistor as an example, but PMO
The S transistor can be formed in the same manner. It is also possible to form a Bi-CMOS device by forming a CMOS transistor by similarly providing a PMOS transistor in addition to the NMOS transistor.

[0067]

As described above, according to the first aspect of the present invention, the base take-out electrode is formed in the insulating layer of the SOI substrate below the emitter region and the base region of the bipolar transistor. The area of the base contact portion occupying the formation region is reduced.
Further, since the base take-out electrode can be provided near the base region, the parasitic capacitance can be reduced and the characteristics of the bipolar transistor can be improved. Further, since the bipolar transistor is formed on the SOI substrate, the periphery of the bipolar transistor is almost surrounded by the insulator. For this reason,
Higher performance can be achieved. According to the invention of claim 2, when the SOI substrate is formed, the trench is formed in the insulating layer, the base lead electrode is formed in the trench, and then the silicon layer is provided to form the base region. It is possible to reduce the formation area of the bipolar transistor formed on the substrate. According to the invention of claim 3, since a high performance bipolar transistor and a back gate type MOS transistor can be mounted on the SOI substrate, for example, a high performance Bi-CMOS device can be constructed. According to the invention of claim 4, when the SOI substrate is formed, a groove is formed in the insulating layer, the base take-out electrode is formed inside the one groove, and the back gate electrode is formed inside the other groove. Since the silicon layer is formed and then the silicon layer is formed on each groove, the lateral bipolar transistor and the back gate type MOS transistor can be formed on the same SOI substrate by substantially the same process.

[Brief description of drawings]

FIG. 1 is a schematic configuration sectional view of a first embodiment.

FIG. 2 is a manufacturing process diagram (1) of the first embodiment.

FIG. 3 is a manufacturing process diagram (2) of the first embodiment.

FIG. 4 is a manufacturing process diagram (3) of the first embodiment.

FIG. 5 is a schematic configuration sectional view of a second embodiment.

FIG. 6 is a manufacturing process diagram (1) of the second embodiment.

FIG. 7 is a manufacturing process diagram (2) of the second embodiment.

FIG. 8 is a manufacturing process diagram (3) of the second embodiment.

FIG. 9 is a schematic cross-sectional view of a conventional MOSFET.

FIG. 10 is a schematic cross-sectional view of a conventional lateral npn bipolar transistor.

11 is a layout diagram of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 bipolar transistor 2 MOS transistor 3 semiconductor device 11 thin film SOI substrate 12 n-type silicon layer 13 element isolation region 14 element isolation region 15 p-type base region 16 n ⁺ emitter region 17 n ⁺ collector region 18 insulating layer 19 p ⁺ base extraction electrode 21 Separation Pattern 22 n ⁺ Collector Extraction Electrode 23 Insulation Film 24 Emitter Contact Part 25 Emitter Sidewall Insulation Film 26 n ⁺ Emitter Extraction Electrode 31 n-Type Silicon Substrate 32 First Insulation Layer 33 Groove 38 Second Insulation Layer 41 Separation Pattern 43 polycrystalline silicon film 44 insulating film 47 extraction electrode forming film 60 first silicon layer 61 second silicon layer 62 gate insulating film 63 gate electrode 64 p ⁺ source / drain region 65 p ⁺ source / drain region 66 back Gate Insulating film 67 Back gate electrode 71 Bipolar transistor forming region 72 MOS transistor forming region 73 Element isolation region 76 Groove 78 Gate insulating film 79 Gate forming film 82 p ⁺ source / drain extraction electrode 83 p ⁺ source / drain extraction electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H01L 27/12 Z 8728-4M 29/784 9056-4M H01L 29/78 311 G

Claims (4)

[Claims] 1. An S formed by laminating an insulating layer and a silicon layer.
A base region formed on the upper layer of the silicon layer of the OI substrate, an emitter region formed on the upper layer of the base region, and the silicon layer on both sides or one side of the base region formed with a portion of the silicon layer interposed therebetween. A bipolar transistor comprising a collector region and a base take-out electrode formed in a state of being connected to the base region in an insulating layer of the SOI substrate below the base region. 2. After forming an element isolation region on the surface layer of a silicon substrate, a first insulating layer is formed on the entire surface of the silicon substrate on the element isolation region side, and then the first insulating layer is formed on the silicon substrate. A first step of forming a reaching groove, and a second step of forming a base lead-out electrode connected to the silicon substrate inside the groove and then forming a second insulating layer on the entire surface on the base lead-out electrode side. A third step of removing the silicon substrate until the element isolation region is exposed, and forming a silicon layer on the silicon substrate between the element isolation regions; and above the base extraction electrode. A fourth step of forming a separation pattern on a part of the silicon layer, a polycrystalline silicon film and an insulating film are formed on the entire surface on the separation pattern side, and then either or both of them are formed. A collector region is formed in the upper layer of the silicon layer on one of the element isolation regions, and then the insulating film, the polycrystalline silicon film and the isolation pattern above which form the emitter region are removed to form an emitter contact portion. Fifth step of forming, forming an emitter sidewall insulating film on a side wall of the emitter contact portion, subsequently forming a lead electrode forming film on the emitter contact portion, and diffusing impurities from the lead electrode forming film. A sixth step of forming a base region in the silicon layer in a state of being connected to the base extraction electrode and forming an emitter region on an upper layer of the base region, and then forming an emitter extraction electrode with the extraction electrode forming film. And a bipolar transistor manufacturing method. 3. A bipolar transistor and a MOS mounted on an SOI substrate on which the bipolar transistor is formed.
A semiconductor device including a transistor, wherein the bipolar transistor includes a base region formed in an upper layer of a first silicon layer of an SOI substrate, an emitter region formed in an upper layer of the base region, and both sides of the base region or A collector region formed in the silicon layer on one side through a part of the silicon layer, and a base lead electrode formed in the insulating layer of the SOI substrate below the base region so as to be connected to the base region. The MOS transistor may include a gate insulating film formed on an upper surface of the second silicon layer of the SOI substrate, a gate electrode formed on an upper surface of the gate insulating film, and second gates on both sides of the gate electrode. The source / drain regions formed in the second silicon layer and the lower surface of the second silicon layer. A bipolar transistor comprising a formed back gate insulating film and a back gate electrode formed in a state of being connected to a lower surface of the back gate insulating film in an insulating layer of the SOI substrate below the gate electrode. A semiconductor device equipped with a MOS transistor. 4. A back gate insulating film is formed on the entire surface of the silicon substrate in the MOS transistor formation region after forming an element isolation region for separating the bipolar transistor formation region and the MOS transistor formation region on the surface layer of the silicon substrate. Then, after forming a first insulating layer on the entire surface of the element isolation region side, a groove reaching the silicon substrate is formed in the first insulating layer on the bipolar transistor forming region and the MOS transistor forming region. First step of forming, forming a base lead electrode connected to the silicon substrate inside the groove on the side of the bipolar transistor formation region, and forming a back gate electrode inside the groove on the side of the MOS transistor formation region. And then forming a second insulating layer on the entire surface of the first insulating layer side. And the step of removing the silicon substrate until the element isolation regions are exposed, and forming a first silicon layer and a second silicon layer on the silicon substrate between the element isolation regions. A third step, forming a separation pattern on a portion of the first silicon layer above the collector region, forming a gate insulating film on the upper surface of the second silicon layer, and further forming a gate electrode A fourth step of forming a film for forming a film, a polycrystalline silicon film and an insulating film are formed on the entire surface of the isolation pattern side, and then either or both of the first silicon layers on the element isolation region side A collector region is formed in the first silicon layer, and a part of the insulating film, the polycrystalline silicon film, and the isolation pattern above which form an emitter region are removed to remove the emitter contact portion. And forming a collector extraction electrode with the polycrystalline silicon film, forming a gate electrode with the polycrystalline silicon film and a film forming the gate electrode, and forming a gate insulating film with the gate insulating film. And a step of forming an emitter side wall insulating film on the side wall of the emitter contact portion and a gate side wall insulating film on the side wall of the gate electrode, and then forming an extraction electrode forming film on the entire surface on the side of the insulating film. And then forming a base region in the first silicon layer, forming an emitter region in the upper layer of the base region, and forming source / drain regions in the second silicon layer on both sides of the gate electrode. After that, with the extraction electrode forming film,
An emitter take-out electrode is formed on the emitter contact portion, and each of the source electrodes is formed on both sides of the gate electrode.
6. A method of manufacturing a semiconductor device having a bipolar transistor and a MOS transistor, which comprises a sixth step of forming a source / drain lead-out electrode connected to a drain region.