JPH05204715A - Watchdog timer circuit - Google Patents

Abstract

PURPOSE:To detect whether the processing time of a program is within set time or not. CONSTITUTION:With the start of a program processing, a bit SWP is set to show a state under processing, and a counter RW is started. A shortest/longest set time code is decoded from the operand of an instruction code by an instruction decoder DISR and a decoder DSLC and shortest set time TS is set to a processing time range setting register RSL. When the bit S is fallen before the lapse of the shortest set time TS, an detection circuit DSF detects the state of a bit FSL and detects that the program is abnormality early finished. When the bit S is fallen before the lapse of longest set time TL, the fall detection circuit DSF detects the state of the bit FSL and detects that the program is normally finished.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a watchdog timer circuit incorporated in a microcomputer or a microprocessor for detecting runaway of a program.

[0002]

2. Description of the Related Art In a microcomputer or a microprocessor, a watchdog timer is used to detect runaway or abnormality of a program or hardware.

The watchdog timer causes an interrupt when a certain time elapses during the processing of the program, and monitors the processing state of the program at that time. If normal,
The program ends before the fixed time elapses, and the watchdog timer is reset before the fixed time is reached.

If the program is still being processed even after the elapse of a certain time, the watchdog timer determines that the program is abnormal and an abnormal signal is generated.

As another watchdog timer circuit,
There is one disclosed in JP-A-55-57956 shown in FIG. In the figure, 1 is a microcomputer, 2 is a central processing unit (CPU), 3 is a memory, 4 is an input / output interface (I / O), 5 is a data bus, 6 is an address bus,
Reference numeral 7 is a control bus, 8 is a controlled device, 9 is a monitoring circuit, 10 is an alarm circuit, and 11 is a reset circuit.

This is because a continuous pulse having a predetermined range of cycles is output from an output terminal of a microcomputer according to a program, and whether or not the program is normally executed is monitored depending on the presence or absence of the continuous pulse to cause a malfunction due to noise or the like. Was detecting when the program became abnormal.

[0007]

However, in the former case, if the program processing is abnormal and is completed in a time shorter than the regular processing time, it is not judged to be abnormal because it is completed before the elapse of a certain time. ..

In the latter case, the processing time range of the program could not be set.

In view of the above, the present invention is a watch capable of detecting an abnormality not only when the program runs out of control but also when the processing time becomes abnormally short, not only when the processing time becomes abnormally long. The purpose is to provide a dog timer circuit.

[0010]

The problem solving means according to claim 1 of the present invention is, as shown in FIGS. 1 and 2, a control register R including a bit FF1 indicating that a program is being processed.
_C , a counter R _W that starts counting at the same time as the start of processing of the program, a shortest time setting register R _S that sets the shortest time T _S of the processing time of the program, and a longest time T _L of the processing time of the program comparator circuit _C SW for comparing the longest time setting register _{R L,} the counter _{R W} of the count value _{T W} and the shortest time setting register _{R S} settings _{T S} or maximum set value _{T L} time setting register _{R L} respectively, C _When the count value T _W of the counter R _W and the set values T _S and T _{L of the} shortest time setting register R _S or the longest time setting register R _L become equal to each other by _LW and these comparisons, the bit FF1 of the control register R _C is set. provided from the state and the detection circuit S _C for detecting the processing state of the program, detecting whether or not in process at the time elapsed shortest set time, the longest set Processing at the time of exceeding the time is to detect whether or not completed.

The problem solving means according to claims 2 to 4 of the present invention is a ROM storing a program as shown in FIGS.
, The instruction decoder D _ISR that decodes the instruction code from the ROM, the bit _{SWP of the} flip-flop that indicates that the program is being processed, and the operand from the instruction decoder D _ISR determine the minimum set time and the maximum set time code. a decoder D _SLC for decoding, and the longest set time pending register R _TL to be suspended temporarily maximum setting time T _L, a multiplexer M _PX switching the shortest set time T _S and the longest set time T _L, the processing time of the program Contents of the counter R _W that receives the clock CLK for measurement, the processing time range setting register R _SL that sets the shortest setting time T _S and the longest setting time T _L of the program processing, and the processing time range setting register R _SL And the bit F _{SL of the} flip-flop indicating whether is the shortest set time T _S or the longest set time T _L A coincidence detection circuit C _C for detecting whether match the counter R _W count value T _W and treatment time range setting register R _SL shortest set time T _S or maximum set time T _L of the during program processing Indicates bit _SWP
And the coincidence detection circuit E _DC for detecting an abnormality by the coincidence detection circuit C _C and the bit S indicating that the program is being processed.
_A fall detection circuit D _SF for detecting the fall of _WP ,
The output of the fall detection circuit D _{SF and} the fall abnormality detection circuit F _DC that detects an abnormality according to the state of the bit F _SL indicating the shortest set time T _S or the longest set time T _L are provided. It is to detect whether or not the processing is completed, and to detect whether or not the processing is completed before the longest set time.

[0012]

In the problem solving means according to claim 1, the shortest time and the longest time of the program processing are set in the shortest time setting register R _S and the longest time setting register R _L , respectively. When the program processing routine is entered, the bit FF1 indicating that processing is in progress is set to "1", and when the routine is exited, it is reset to "0".

If the state of the bit FF1 is "1" when the shortest set time has elapsed, it is determined to be normal, and if the state is "0", it is determined that the processing is completed abnormally early.

If the state of the bit FF1 is "0" after the elapse of the longest set time, it is normal, and if it is "1", it is determined that the program has run away and the processing time is abnormally long.

[0015] In SUMMARY by claims 2 to 4, starting at the same time the counter R _W Setting bit S _WP indicating that it is processing the program processing is started, RO by instruction decoder D _ISR
The shortest and longest set time code decoded from the M instruction code is decoded by the decoder D _SLC , and the shortest set time T _S
Is set in the processing time range setting register R _SL .

[0016] Then, when the fall of the bit S _WP indicating that a processed before a shortest set time T _S, the processing time range setting register R _SL indicates that the minimum or maximum set time is set to the bit F _SL State is detected and the shortest time T
_{If S} is set, detect that the program terminated abnormally early.

When the counter R _W and the shortest set time T _S match, the longest set time T _L becomes the processing time range setting register R _SL.
Is set to. Then, when the bit S _WP indicating that the process before the maximum setting time T _L falls, the state of the bit F _SL that indicates that minimum or maximum set time to the processing time range setting register R _SL is set If the maximum time T _L is set, it is detected that the program has ended normally.

[0018]

【Example】

(First Embodiment) FIG. 1 is a block diagram of a watchdog timer circuit showing a first embodiment of the present invention, and FIG. 2 is a signal waveform diagram in the watchdog timer circuit during normal operation and abnormal operation of a program. ..

The watchdog timer circuit of this embodiment is
A control register R _C including a bit FF1 indicating that the program is being processed, a counter R _W that starts counting at the same time as the start of the program processing, and a shortest time setting register that sets the shortest time T _S of the program processing time. R
_S and a maximum time setting register R _L for setting the maximum time T _L program processing time, the counter R _W of the count value T _W and the shortest time setting register R _S settings T _S or maximum time setting register R _L comparator circuit _{C SW, C LW} and the count value of the counter _{R W} these comparison _{T W} and the shortest time setting register _{R S} or maximum time setting register _{R L} set value _T S to compare the set value _{T L,} respectively,
When T _L becomes equal, bit F of control register R _C
A detection circuit S _C for detecting the processing state of the program from the state of F1.

Each register has a flip-flop and is composed of a plurality of bits. Then, in the bits of the control register R _C , there is a bit FF1 indicating the processing state of the program. The bit FF1 is set to “1” when entering the processing routine of the program, and reset to “0” when exiting from the routine. To be done.

[0021] The shortest time setting register R _S, is set shortest time set value T _S, the maximum time setting register R _L, the maximum time set value T _L is set.

The comparator circuits C _SW and C _LW are provided with a counter R _W.
Is a comparator for comparing the count value T _W of T _w with the set values T _S , T _L, and outputs a signal to the detection circuit S _C when T _W = T _S , T _W = T _L , respectively.

The detection circuit S _C is composed of comparison circuits C _SW and C _LW.
Is detected by detecting the state of the bit FF1 and whether or not the processing time of the program is between the shortest set time and the longest set time.

In the above structure, the bit FF1 indicating that the program of the control register R _C is being processed is in the set state "1" during the processing, and becomes the reset state "0" when the processing is completed.

[0025] Upon entering the program routine (eg interrupt), bit FF1 becomes "1", the counter _{R W} is started.

[0026] Compared with the counter _{R W} of the count value _{T W} and the shortest time setting register _{R S} settings _{T S} and a comparator circuit _{C SW,} it detects the state of the bit FF1 by the detection circuit _{S C} when equal, As shown in FIG. 2C, if the reset state is “0”, it is determined that the processing has ended abnormally early. Then, this abnormality is output as an error signal to the outside.

If the set state is "1" as shown in FIG. 2B, the counter R _W is further continued to count, and the count value T _W and the set value T _{L of the} longest time setting register R _L are compared. compared with _{LW, T W} detects the status again bit FF1 at the time beyond the _{T L} by the detection circuit _{S C,} FIG. 2
If the reset state is “0” as shown in (b), it is determined to be normal, and if the set state is “1” as shown in FIG. 2 (d), the program runs away and the processing time becomes abnormally long. It is determined that

Therefore, the conventional watchdog timer circuit can detect only when the program goes out of control, that is, when the processing time becomes abnormally long.
Even when the processing time of the program is abnormally short, it can be detected by detecting whether or not the processing is completed when the shortest time of the processing time of the program has elapsed.

(Second Embodiment) In the first embodiment, whether or not the program processing ends abnormally early when the processing time counter coincides with the shortest set time, and when the longest set time is exceeded, It was detecting whether the processing was completed normally or abnormally long.

However, if the program processing ends abnormally early before the processing time counter coincides with the shortest set time, this cannot be detected. Further, even if the program ends normally before the processing time counter matches the longest set time, this could not be detected.

Therefore, in the watchdog timer circuit of this embodiment, the ROM in which the program is stored, the instruction decoder D _ISR for decoding the instruction code from the ROM, and the bit of the flip-flop indicating that the program is being processed. _SWP, and a decoder D _SLC for decoding the minimum set time and the maximum set time code by the operand from the instruction decoder D _ISR ,
And the longest set time pending register R _TL to be suspended temporarily maximum setting time T _L, a multiplexer M _PX switching the shortest set time T _S and the longest set time T _L, a clock CLK to measure the processing time of the program A counter R _{W as} an input, a processing time range setting register R _SL for setting a shortest set time T _S and a longest set time T _L of program processing,
The content of the processing time range setting register R _SL is the shortest setting time T
Match the bit F _{SL of the} flip-flop indicating _S or the longest set time T _L, the count value T _W of the counter R _W , and the shortest set time T _S or the longest set time T _{L of the} processing time range setting register R _SL. Match detection circuit C for detecting whether or not
_C , the state of the bit _SWP indicating that the program is being processed and the coincidence abnormality detection circuit E _DC that detects an abnormality by the coincidence detection circuit C _C, and the fall detection that detects the falling of the bit _SWP that indicates that the program is being processed The output of the circuit D _SF and the fall detection circuit D _SF and the shortest set time T _S or the longest set time T _L
An abnormality detection circuit F _DC during the fall detecting an abnormality by the state of bit F _SL indicating whether the output of the abnormality detection circuit D _SF when falling output and falling of the match when the abnormality detection circuit E _DC and 2 input abnormality detection signal OR circuit OR1 for outputting a signal, an inverter INV1 for inverting the polarity of a bit _SWP indicating that a program is being processed, an OR circuit OR1 and an inverter IN
It is composed of an OR circuit OR2 which receives the output of V1 as two inputs and resets the counter R _W.

The bit _SWP indicating that the program is processing is
It is set to "1" when entering the processing routine of the program, and reset to "0" when exiting the processing routine.

Bit F indicating whether the content of the processing time range setting register R _SL is the shortest set time T _S or the longest set time T _L
SL is reset to "0" when the content of the processing time range setting register R _SL is the shortest set time T _S , and is set to "1" when the longest set time T _L.

When the shortest set time T _S is reached, the coincidence abnormality detection circuit E _DC determines that the program processing is normal if the bit _SWP is "1", and if the bit _SWP is "0", the program processing is normal. It is determined that the process of is abnormal. When the longest set time T _L is reached, if the bit _SWP is “0”, it is determined that the program processing is normal, and if the bit _SWP is “1”, it is determined that the program processing is abnormal.

The falling time abnormality detection circuit F _DC, when falling of the bits S _WP when bit F _SL is "0" is detected, it is determined that processing of the program is abnormal, the bit F _SL is " When the falling edge of the bit _SWP is detected in the case of "1", it is determined that the program has ended normally.

[0036] In the above arrangement, upon entering the program routine, decodes the instruction code from the program is stored ROM by instruction decoder D _ISR, bit S _WP becomes "1" by the output from the instruction decoder D _ISR , Counter R
_W count starts.

Then, the instruction decoder D
The shortest and longest operand setting codes from the _ISR are input to the decoder D _SLC , and the bit F _SL is reset to "0". The shortest setting time T _S from the decoder D _SLC is set in the processing time range setting register R _SL by the signal from the instruction decoder D _ISR through the multiplexer M _PX by the bit F _SL of “0”. On the other hand, the longest set time T _L is set in the longest set time holding register R _TL by a signal from the instruction decoder D _ISR .

The counter before a shortest set time T _S of R _W count value T _W and treatment time range setting register R _SL of match, the bit S _WP shows the processing of the program up to "1" to "0" When it falls, the fall detection circuit D _SF detects it. The output of the fall detection circuit D _SF causes the fall abnormality detection circuit F _DC to detect the "0" state of the bit F _SL , and determines that the program ends abnormally early as shown in FIG. 4 (c). Then, the OR circuit O
It is output to the outside as an abnormality detection output through R1, and the counter R _W is reset through the longest set time holding register R _TL and the OR circuit OR2.

[0039] When the counter R _W count value T _W and treatment time range setting register R _SL minimum setup time T _S of match,
The output of the coincidence detection circuit C _C and the state of the bit _SW P are detected by the abnormality detection circuit E _DC at the time of coincidence, and as shown in FIG.
_{If WP} is "0", it is determined that the program processing has ended abnormally early and the fall detection circuit D _SF is abnormal. Then, it is output to the outside as an abnormality detection output through the OR circuit OR1, and the longest set time holding register R _TL
And the counter R _W is reset through the OR circuit OR2.

Here, if the bit _SWP is "1" as shown in FIG. 4B, it is determined that the program is processed normally, and the bit F is generated by a control signal from the coincidence abnormality detection circuit E _{DC. SL} is set to "1", the contents of the longest set time pending register R _TL passes through the multiplexer M _PX by "1" bit F _SL, it is set in the processing range setting register R _SL.

The counter before the maximum setting time T _L of R _W counter value T _W and treatment time range setting register R _SL of match, the bit S _WP shows the processing of the program up to "0" to "1" If lowered, it is detected by the fall detecting circuit D _SF, the abnormality detection circuit during the fall from "1" state of the output bit F _SL falling detection circuit D _SF F _DC
Then, it is determined that the program has ended normally.

[0042] when the counter R _W counter value T _W and processing the longest set time T _L of the time range setting register R _SL of the match,
The output of the coincidence detection circuit C _C and the state of the bit _SW P are detected by the abnormality detection circuit E _DC at the time of coincidence, and as shown in FIG.
_{If WP} is "0", it is determined that the program has ended normally.

If the bit _SWP is "1" as shown in FIG. 4 (d), it is determined that the program has run away and the processing time is abnormally long, and an external signal is output as an abnormality detection output through the OR circuit OR1. To reset the counter R _W through the longest set time holding register R _TL and the OR circuit OR2.

Thus, by including the shortest and longest set time codes in the program operand, the shortest set time and the longest set time of the program processing can be set, and whether the program is being processed when the shortest set time has elapsed. It is possible to detect whether or not the program processing is completed when the longest set time has elapsed.

Further, by detecting the falling edge of the bit indicating that the program is being processed, the program ends abnormally early when the shortest time is set in the processing time range setting register, and the longest time. When is set, it can detect that the program ended normally.

Therefore, in the first embodiment, it is not possible to detect that the program processing ends abnormally early before the counter coincides with the shortest set time until the counter coincides with the shortest set time, and the counter has the longest set time. It was not possible to detect that the program ended normally before the match with the above, until the counter matched the maximum set time, but the code of the minimum set time and the maximum set time of the program contained in the operand of the instruction code was decoded. By setting the processing time range setting register and detecting the falling edge of the bit indicating that the program is being processed, abnormalities in the program processing before the shortest set time or normal termination of the program processing before the longest set time can be detected. Can be detected.

The present invention is not limited to the above embodiments, and it goes without saying that many modifications and changes can be made to the above embodiments within the scope of the present invention.

[0048]

As is apparent from the above description, according to claim 1 of the present invention, the shortest time setting register for setting the shortest time of the processing time of the program and the longest time setting for setting the longest time of the processing time of the program. Register and
In the conventional watchdog timer, the program runs out of control in order to detect whether the program is being processed when the shortest set time has elapsed and whether the processing has ended when the longest set time is exceeded. Although it can be detected only when the processing time is abnormally long, that is, when the processing time of the program is abnormally short, it can be detected.

According to the second to fourth aspects, since the program operands include the shortest and longest set time codes,
The minimum set time and the maximum set time of program processing can be set. Therefore, it is possible to detect whether or not the program is being processed when the shortest set time has elapsed, and to detect whether or not the program processing has ended when the longest set time has elapsed.

Further, by detecting the falling edge of the bit indicating that the program is being processed, the program ends abnormally early before the shortest set time elapses, and the program becomes normal before the longest set time elapses. It can detect the end.

[Brief description of drawings]

FIG. 1 is a block diagram of a watchdog timer circuit showing a first embodiment of the present invention.

FIG. 2 is a signal waveform diagram in the watchdog timer circuit when the program operates normally and abnormally.

FIG. 3 is a block diagram of a watchdog timer circuit showing a second embodiment of the present invention.

FIG. 4 is a signal waveform diagram in the watchdog timer circuit during normal operation of the program and during abnormal operation when the time is shorter than the shortest set time and longer than the longest set time.

FIG. 5 is a block diagram of a conventional malfunction prevention device for a microcomputer.

[Explanation of symbols]

C _SW , C _LW comparison circuit FF 1 bit R _C control register R _L longest time setting register R _S shortest time setting register S _C detection circuit D _ISR instruction decoder D _SLC decoder S _WP bit R _TL longest setting time hold register M _PX multiplexer R _W counter R _SL Processing time range setting register F _SL bit C _C Match detection circuit E _DC Match error detection circuit D _SF Fall detection circuit F _DC Fall error detection circuit

Claims (4)

[Claims] 1. A control register for detecting runaway of a program, the control register including a bit indicating that the program is being processed, a counter for starting counting at the same time as the start of processing of the program, and a processing time of the program. The shortest time setting register that sets the shortest time, the longest time setting register that sets the longest program processing time, the counter count value and the shortest time setting register setting value or the longest time setting register setting value are compared. And a detection circuit for detecting the processing state of the program from the bit state of the control register when the count value of the counter becomes equal to the set value of the shortest time setting register or the longest time setting register by these comparisons. A watchdog timer circuit characterized by being provided. 2. A program for detecting runaway of a program, the register including a bit indicating that the program is being processed, and a count being started at the same time when the bit is set and being in a reset state when the program is not being processed. A counter, a processing time range setting register that sets the processing time of the program, a register that contains a bit that indicates whether the minimum setting time or the maximum setting time is set in the processing time range setting register, the counter count value, and the processing time The match detection circuit that detects whether the set values in the range setting register match, the state of the bit that indicates that the program is being processed, and the processing time The shortest or longest set time is set in the range setting register. The processing state of the program before each set time is determined from the state of the bit indicating whether A watchdog timer circuit comprising an abnormality detection circuit for detecting. 3. The watchdog timer circuit according to claim 2, wherein a ROM containing a program and an RO
An instruction decoder that decodes and activates the contents of M, a decoder that decodes the code of the minimum set time and the maximum set time of the program included in the operand from the instruction decoder, and a multiplexer that switches the minimum set time and the maximum set time. A watchdog timer circuit, comprising: a register that holds a maximum set time. 4. The abnormality detection circuit according to claim 2, wherein a fall detection circuit that detects a fall of a bit indicating that a program is being processed, an output of the fall detection circuit, and a minimum set time or a maximum set time are set. A watchdog timer circuit, comprising: a fall abnormality detection circuit that detects whether the processing of the program is abnormal or normal depending on the state of a bit indicating whether the program is being processed.