JPH0519981B2 - - Google Patents

Info

Publication number
JPH0519981B2
JPH0519981B2 JP61264282A JP26428286A JPH0519981B2 JP H0519981 B2 JPH0519981 B2 JP H0519981B2 JP 61264282 A JP61264282 A JP 61264282A JP 26428286 A JP26428286 A JP 26428286A JP H0519981 B2 JPH0519981 B2 JP H0519981B2
Authority
JP
Japan
Prior art keywords
cell array
memory device
bonding
semiconductor memory
dip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61264282A
Other languages
Japanese (ja)
Other versions
JPS63117439A (en
Inventor
Hitonori Hayano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP61264282A priority Critical patent/JPS63117439A/en
Publication of JPS63117439A publication Critical patent/JPS63117439A/en
Publication of JPH0519981B2 publication Critical patent/JPH0519981B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Memories (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体記憶装置に関し、特に半導体記
憶装置のレイアウト方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a layout method for a semiconductor memory device.

〔従来の技術〕[Conventional technology]

従来の半導体記憶装置のレイアウト方法は、中
央部にセルアレイ領域、その外側に周辺回路領
域、更にその外側にパツド領域が配置されてい
る。又、セルアレイ領域は、ワード線及びビツト
線ごとの規則的な繰返しパタンとして設けられた
メモリセルアレイ領域とデコーダ領域とから構成
されている。 In the conventional layout method of a semiconductor memory device, a cell array area is placed in the center, a peripheral circuit area is placed outside the cell array area, and a pad area is placed outside the cell array area. Further, the cell array area is composed of a memory cell array area and a decoder area provided as a regular repeating pattern for each word line and bit line.

第５図は従来の半導体記憶装置の第１の例のレ
イアウト図である。 FIG. 5 is a layout diagram of a first example of a conventional semiconductor memory device.

第５図において、２０はセルアレイ領域で半導
体基板１cのほぼ中央部に設けられている。３−
１，３−２は周辺回路領域でありセルアレイ領域
２０の外側に設けられている。又、２２−１〜２
２−１８はボンデイングパツドであり、周辺回路
領域３−１，３−２の外側の半導体基板１cの両
端部に配置されている。 In FIG. 5, reference numeral 20 denotes a cell array region, which is provided approximately at the center of the semiconductor substrate 1c . 3-
Reference numerals 1 and 3 - 2 are peripheral circuit areas provided outside the cell array area 20 . Also, 22-1~2
Bonding pads 2-18 are arranged at both ends of the semiconductor substrate 1c outside the peripheral circuit areas 3-1 and 3-2.

第６図は第５図の半導体記憶装置を18ピンの
DIPに実装したときの部分平面図である。 Figure 6 shows an 18-pin semiconductor memory device in Figure 5.
FIG. 3 is a partial plan view when mounted on a DIP.

第６図において、１４は18ピンのDIP、１５−
１〜１５−５はDIP１４のリードであり、それぞ
れ半導体基板１c上に設けられたボンデイングパ
ツド２２−１〜２２−５とボンデイングワイヤに
よつて接続されている。 In Figure 6, 14 is an 18-pin DIP, 15-
1 to 15-5 are leads of the DIP 14, which are respectively connected to bonding pads 22-1 to 22-5 provided on the semiconductor substrate 1c by bonding wires.

第６図に示すように、ボンデイングパツド２２
−５のボンデイングワイヤが、他のボンデイング
ワイヤに比べて長く、容量が大きくなるとともに
ボンデイングワイヤが垂れることにより、半導体
記憶装置のエツジと接触して短絡障害を発生する
ことがある。 As shown in FIG.
The -5 bonding wire is longer than the other bonding wires, has a larger capacitance, and the bonding wire sag, which may contact the edge of the semiconductor memory device and cause a short circuit failure.

この問題を解決する方法としては、ボンデイン
グパツド２２−５を半導体基板１cの中央部へ配
置すればよいが、上述した第５図に示すように、
半導体基板１cの中央部はほとんどセルアレイ領
域２０で占められているため、中央部にボンデイ
ングパツドのための領域を設けるためにはセルア
レイ領域を分割しなければならない。 A method to solve this problem is to place the bonding pad 22-5 in the center of the semiconductor substrate 1c , but as shown in FIG.
Since the center of the semiconductor substrate 1c is mostly occupied by the cell array region 20, the cell array region must be divided in order to provide a region for bonding pads in the center.

第７図は従来の半導体装置の第２の例のレイア
ウト図である。 FIG. 7 is a layout diagram of a second example of a conventional semiconductor device.

第７図において、２１−１，２１−２は２つに
分割されたセルアレイ領域である。ここで、それ
ぞれのセルアレイ領域２１−１，２１−２は面積
がほぼ等しくなつているので、セルアレイ領域２
１−１，２１−２の間に設けられたボンデイング
パツド２３−５，２３−１４は、半導体基板１d
のほぼ中央部の基板縁部に配置される。 In FIG. 7, 21-1 and 21-2 are cell array regions divided into two. Here, since the respective cell array regions 21-1 and 21-2 have approximately the same area, the cell array regions 21-1 and 21-2 have approximately the same area.
Bonding pads 23-5 and 23-14 provided between semiconductor substrates 1-1 and 21-2
It is located at the edge of the board at approximately the center of the board.

しかしながら、半導体基板１dの中央部にボン
デイングパツドを配置しただけでは、以下に述べ
る理由から前述した問題を十分に解決することは
できない。 However, simply arranging the bonding pad in the center of the semiconductor substrate 1d cannot sufficiently solve the above-mentioned problems for the reasons described below.

第８図は第７図の半導体記憶装置を18ピンの
DIPに実装した場合の部分平面図である。 Figure 8 shows an 18-pin semiconductor memory device in Figure 7.
FIG. 3 is a partial plan view when mounted on a DIP.

第７図に示すように、DIP１４は18ピンである
ため、左から５番目のリード１５−５はDIP１４
の中央部に位置し、従つてリード１５−５と半導
体基板１dの中央部に配置されたボンデイングパ
ツド２３−５との位置関係はほぼ対向するように
なる。このため、リード１５−５の点Ａでボンデ
イングした場合、ボンデイングワイヤが長くな
り、リードの形状及びボンデイング位置によりボ
ンデイングパツドを中央へ配置する利点が失われ
るという欠点がある。 As shown in Figure 7, since DIP14 is 18 pins, the fifth lead 15-5 from the left is DIP14.
Therefore, the lead 15-5 and the bonding pad 23-5, which is located at the center of the semiconductor substrate 1d , are substantially opposed to each other. Therefore, when bonding is performed at point A of lead 15-5, the bonding wire becomes long, and the advantage of locating the bonding pad in the center is lost depending on the shape of the lead and the bonding position.

ボンデイングワイヤの長さを短かくするには、
リード１５−５上の点Ｂでボンデイングすればよ
いが、この時には、リードを伝つて外部から侵入
してくる水分に対する耐性（耐湿性）が劣化する
という欠点がある。 To shorten the length of the bonding wire,
Bonding may be performed at point B on the lead 15-5, but at this time, there is a drawback that the resistance (moisture resistance) to moisture entering from the outside along the lead deteriorates.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体記憶装置は、半導体基板上に設
けられたメモリセル領域とデコーダ領域とを備え
る少くとも３つのセルアレイ領域と、該セルアレ
イ領域の間に設けられたボンデイングパツドとを
含んで構成される。 A semiconductor memory device of the present invention includes at least three cell array regions provided on a semiconductor substrate, each including a memory cell region and a decoder region, and a bonding pad provided between the cell array regions. Ru.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して
説明する。 Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本発明の第１の実施例のレイアウト図
である。 FIG. 1 is a layout diagram of a first embodiment of the present invention.

第１図において、１aは半導体基板、２−１，
２−２，２−３はセルアレイ領域、３−１，３−
２は周辺回路領域、４−１〜４−１８はボンデイ
ングパツド、５−１，５−２，５−３及び６−
１，６−２，６−３はそれぞれセルアレイ領域２
−１，２−２，２−３に設けられた列デコーダ及
び行デコーダである。 In FIG. 1, 1 a is a semiconductor substrate, 2-1,
2-2, 2-3 are cell array areas, 3-1, 3-
2 is a peripheral circuit area, 4-1 to 4-18 are bonding pads, 5-1, 5-2, 5-3 and 6-
1, 6-2, and 6-3 are cell array area 2, respectively.
-1, 2-2, and 2-3 are column decoders and row decoders provided.

第２図は第１図の実施例を18ピンのDIPに実装
したときの部分平面図である。 FIG. 2 is a partial plan view of the embodiment shown in FIG. 1 mounted on an 18-pin DIP.

第２図に示すように、DIP１４は18ピンである
ため、左から５番目のリード１５−５はDIP１４
のほぼ中央部に位置するが、半導体基板１aのセ
ルアレイ領域２−１と２−２との間に配置された
リード１５−５が接続されるボンデイングパツド
４−５の位置が、前述した第７図の半導体記憶装
置の場合に比べ半導体基板１aの中央部より左へ
移動するため、ボンデイングワイヤの長さを短縮
できる。 As shown in Figure 2, DIP14 is 18 pins, so the fifth lead 15-5 from the left is DIP14.
The position of the bonding pad 4-5, to which the lead 15-5 placed between the cell array regions 2-1 and 2-2 of the semiconductor substrate 1a is connected, is located approximately in the center of the semiconductor substrate 1a. Compared to the case of the semiconductor memory device shown in FIG. 7, since the bonding wire is moved to the left from the center of the semiconductor substrate 1a , the length of the bonding wire can be shortened.

第３図は本発明の第２の実施例のレイアウト図
である。 FIG. 3 is a layout diagram of a second embodiment of the present invention.

第３図に示す第２の実施例は、20ピンの半導体
記憶装置の場合で、20ピンの半導体記憶装置をボ
ンデイングワイヤが長くならないように20ピンの
DIPに実装するためには、第２の実施例のように
セルアレイ領域を３分割し、分割したセルアレイ
領域２−１〜２−３の間すべてにボンデイングパ
ツドを設ければよい。 The second embodiment shown in FIG. 3 is for a 20-pin semiconductor memory device.
For mounting on DIP, the cell array area may be divided into three as in the second embodiment, and bonding pads may be provided between the divided cell array areas 2-1 to 2-3.

第４図は第３図の第２の実施例を20ピンのDIP
に実装した場合の部分平面図である。 Figure 4 shows the second embodiment of Figure 3 as a 20-pin DIP.
FIG.

第４図に示すように、DIP１７は20ピンである
から、左から５番目のリード１６−５と６番目の
リード１６−６とがDIP１７の中央部の両側に位
置するが、セルアレイ領域２−１〜２−３を３分
割した間にボンデイングパツド７−５，７−６，
７−１５，７−１６が設けられているので、リー
ド１６−５，１６−６とボンデイングパツド７−
５，７−６とを接続するボンデイングワイヤが長
くなることを防止できる。 As shown in FIG. 4, since the DIP 17 has 20 pins, the fifth lead 16-5 and the sixth lead 16-6 from the left are located on both sides of the center of the DIP 17. Bonding pads 7-5, 7-6, between 1 to 2-3 divided into three
Since leads 7-15 and 7-16 are provided, leads 16-5 and 16-6 and bonding pad 7-
5, 7-6 can be prevented from becoming long.

以上述べたようなレイアウト法を用いることに
より、本発明の半導体記憶装置を実現できる。 By using the layout method as described above, the semiconductor memory device of the present invention can be realized.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、半導体記憶装置
のセルアレイ領域を少くとも３つに分割し、分割
されたセルアレイ領域の間にボンデイングパツド
を設けることにより、ボンデイングワイヤの長さ
を短縮できるので、耐湿性を劣化することなく容
量の増大や短絡障害の発生を防止できるという効
果がある。 As explained above, in the present invention, the length of the bonding wire can be shortened by dividing the cell array area of a semiconductor memory device into at least three parts and providing bonding pads between the divided cell array areas. This has the effect of preventing an increase in capacity and the occurrence of short circuit failures without deteriorating moisture resistance.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の第１の実施例のレイアウト
図、第２図は第１図の第１の実施例を18ピンの
DIPに実装したときの部分平面図、第３図は本発
明の第２の実施例のレイアウト図、第４図は第３
図の第２の実施例を20ピンのDIPに実装したとき
の部分平面図、第５図は従来の半導体記憶装置の
第１の例のレイアウト図、第６図は第５図の半導
体記憶装置を18ピンのDIPに実装したときの部分
平面図、第７図は従来の半導体記憶装置の第２の
例のレイアウト図、第８図は第７図の半導体記憶
装置を18ピンのDIPに実装したときの部分平面図
である。 １a，１b，１c，１d……半導体基板、２−１〜
２−３……セルアレイ領域、３−１，３−２……
周辺回路領域、４−１〜４−１８……ボンデイン
グパツド、５−１〜５−３……列デコーダ、６−
１〜６−３……行デコーダ、７−１〜７−２０…
…ボンデイングパツド、１４……DIP、１５−１
〜１５−５，１６−１〜１６−７……リード、１
７……DIP、２０，２１−１，２１−２……セル
アレイ領域、２２−１〜２２−１８，２３−１〜
２３−１８……ボンデイングパツド。 Fig. 1 is a layout diagram of the first embodiment of the present invention, and Fig. 2 is a layout diagram of the first embodiment of the present invention.
3 is a layout diagram of the second embodiment of the present invention, and FIG. 4 is a partial plan view of the second embodiment of the present invention when mounted on a DIP.
A partial plan view of the second embodiment shown in the figure mounted on a 20-pin DIP, FIG. 5 is a layout diagram of the first example of the conventional semiconductor memory device, and FIG. 6 is the semiconductor memory device of FIG. Fig. 7 is a layout diagram of the second example of a conventional semiconductor memory device, and Fig. 8 is a partial plan view of the semiconductor memory device shown in Fig. 7 mounted on an 18-pin DIP. FIG. 1 a , 1 b , 1 c , 1 d ... semiconductor substrate, 2-1 ~
2-3... Cell array area, 3-1, 3-2...
Peripheral circuit area, 4-1 to 4-18... Bonding pad, 5-1 to 5-3... Column decoder, 6-
1 to 6-3... row decoder, 7-1 to 7-20...
...Bonding Pad, 14...DIP, 15-1
~15-5, 16-1~16-7...Lead, 1
7...DIP, 20,21-1,21-2...Cell array area, 22-1~22-18,23-1~
23-18...Bonding pad.

Claims (1)

【特許請求の範囲】[Claims] １ 半導体基板上に設けられたメモリセルアレイ
領域とデコーダ領域とを備える少くとも３つのセ
ルアレイ領域と、前記セルアレイ領域の間に設け
られたボンデイングパツドとを含むことを特徴と
する半導体記憶装置。1. A semiconductor memory device comprising at least three cell array regions provided on a semiconductor substrate, each including a memory cell array region and a decoder region, and a bonding pad provided between the cell array regions.
JP61264282A 1986-11-05 1986-11-05 Semiconductor memory device Granted JPS63117439A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61264282A JPS63117439A (en) 1986-11-05 1986-11-05 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61264282A JPS63117439A (en) 1986-11-05 1986-11-05 Semiconductor memory device

Publications (2)

Publication Number Publication Date
JPS63117439A JPS63117439A (en) 1988-05-21
JPH0519981B2 true JPH0519981B2 (en) 1993-03-18

Family

ID=17401001

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61264282A Granted JPS63117439A (en) 1986-11-05 1986-11-05 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS63117439A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2585738B2 (en) * 1988-08-12 1997-02-26 株式会社日立製作所 Semiconductor storage device

Also Published As

Publication number Publication date
JPS63117439A (en) 1988-05-21

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