JP2659179B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to preventing corrosion due to moisture entering from the outside and shortening a bonding wire connecting a lead and a bonding pad. Semiconductor device.

[Conventional technology]

FIG. 2 is a plan view showing a conventional semiconductor substrate 10;
In the figure, reference numeral 11 denotes a cell array region including memory cells arranged in a matrix and a decoder and the like. Peripheral circuits 12-1, 12-2 having an input / output circuit, a clock generation circuit, an address decoder, etc., on both sides of the cell array area 11 in the column direction.
Are formed. Bonding pads 13-1 to 13-18 are provided on the outer periphery of these peripheral circuits 12-1 and 12-2, and these bonding pads 13-1 to 13-18 are
As shown in detail in FIG. 3, bonding wires 16-1 to 16-18 are respectively connected to leads 15-1 to 15-18 provided on the package 14 at predetermined intervals in the column direction of the cell array region 11. Connected by -18.

[Problems to be solved by the invention]

However, in the conventional semiconductor memory device, the bonding pads 13-1 to 13-18 are connected to the peripheral circuits 12-1 and 12-18.
-2, that is, the leads 15-1 to 15-15 despite being formed on both sides of the cell array region 11 in the column direction.
Since −18 is provided along the column direction of the cell array region 11, the distance between the lead 15-5 and the like, which is located near the middle of the cell array region 11 in the column direction, and the bonding pad 13-5 and the like becomes longer. , And the accompanying bonding wire 16
Since -5 or the like becomes longer, there is a problem that the electric resistance is increased and the bonding wire hangs down and comes into contact with the semiconductor substrate 10 or the like to cause a short circuit.

In order to solve such a problem, the cell array region 11 is bisected in the column direction as shown in FIG. 4 to form a first cell array region 11-1 and a second cell array region 11-2. It is also conceivable to dispose a part of the bonding pads 13-5 and the like on the separation band 17 to be separated. However, in the bisected cell array regions 11-1 and 11-2, as shown in FIG. 5, the bonding pad 13-5 provided on the separation band 17 and the point A of the lead 15-5 are connected. Is still long if the bonding wire 16-5 is connected with the bonding wire 16-5, and the conventional problem cannot be solved. On the other hand, the bonding pad 13-5 and the lead 15-
When the point B is connected to point B, the semiconductor device is susceptible to corrosion or the like due to moisture penetrating along the lead 15-5, and the problem is that the life of the semiconductor device is shortened.

Therefore, an object of the present invention is to provide a semiconductor memory device having excellent moisture resistance and a reduced bonding wire length.

[Means for solving the problem]

The present invention provides a semiconductor memory device in which a bonding pad of a memory chip in which a cell array including memory cells arranged in a matrix is separated into a plurality of regions by a separation band and external leads of a package are individually electrically connected. A bonding pad is disposed on a separation band provided at a position separated from the center of the memory chip, and an external lead to be electrically connected to the bonding pad is provided at a position deviated from the separation band. A lead portion disposed in the package extends to the vicinity of the separation band in the package, and a tip of the extended lead portion in the package and a bonding pad provided in the separation band are bonded with a bonding wire. By connecting, a bonding wire connecting the bonding pad provided on the separation band and the lead is provided. There is ensured a shunting, and summarized in that moisture entering along the lead is prevented from adhering directly to the bonding wire.

〔Example〕

FIG. 1 is a plan view showing an embodiment of the present invention. A semiconductor substrate 10 has memory cells arranged in a matrix, column decoders 4-1 and 4-2, and row decoders 5-1 and 5-2. The first cell array region 1-1 and the second cell array region 1-2 including the above are formed via a separation band 8. These cell array areas 1
Peripheral circuits 2-1 and 2 comprising an input / output circuit, a clock generation circuit, an address decoder, etc.
The bonding pads 3-1 to 3-18 are formed on the outer periphery of the peripheral circuits 2-1 and 2-2 and on the separation band 8. As shown in FIG. 6, both ends of the above-mentioned separation band 8 are connected to leads 6-4 and 6-5 of leads 6-1 to 6-18 provided on package 9.
And is located in the middle. Therefore, even if the bonding pads 3-5 and 3-14 provided on the separation band 8 and the corresponding leads 6-5 and 6-14 (not shown) are connected at the shortest distance, the bonding wires 7-5 are connected. , 7-14 (not shown)
Does not directly oppose the tip L of the lead 6-5, 6-14 (not shown).

〔effect〕

As described above, according to the present invention, both ends of the separation band are located between the leads adjacent to each other, and a part of the bonding pad is provided in the separation band. Even if the shortest distance to the lead corresponding to the lead wire is connected by a bonding wire, the bonding wire does not directly oppose the tip of the lead. Therefore, the resistance value of the bonding wire can be reduced, and
The effect is obtained that the short circuit can be prevented and the moisture resistance can be maintained.

[Brief description of the drawings]

1 is a plan view of one embodiment of the present invention, FIG. 2 is a plan view of a conventional example, FIG. 3 is a partially enlarged detailed view of FIG. 2, and FIG. 4 is a case where a cell array region is simply divided into two. Plan view, fifth
FIG. 4 is a partially enlarged detailed view of FIG. 4, and FIG. 6 is a partially enlarged detailed view of FIG. 1-1, 1-2 ... cell array area, 3-1 to 3-18 ...
... bonding pads, 6-1 to 6-18 ... leads,
7-1 to 7-18: bonding wire, 8: separation band, 10: semiconductor substrate.

Claims (1)

(57) [Claims] 1. A semiconductor memory device in which a bonding pad of a memory chip in which a cell array including memory cells arranged in a matrix is separated into a plurality of regions by a separation band and external leads of a package are individually electrically connected. A bonding pad is disposed on a separation band provided at a position separated from the center of the memory chip, and an external lead to be electrically connected to the bonding pad is provided at a position shifted from the separation band. A lead portion arranged in the package of the lead extends in the package to the vicinity of the separation band, and a leading end of the extended lead portion in the package and a bonding pad provided in the separation band are connected to a bonding wire. A semiconductor memory device characterized by being connected by: