JPH05198789A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH05198789A
JPH05198789A JP31159692A JP31159692A JPH05198789A JP H05198789 A JPH05198789 A JP H05198789A JP 31159692 A JP31159692 A JP 31159692A JP 31159692 A JP31159692 A JP 31159692A JP H05198789 A JPH05198789 A JP H05198789A
Authority
JP
Japan
Prior art keywords
film
silicon
silicon substrate
semiconductor device
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP31159692A
Other languages
Japanese (ja)
Other versions
JPH0682829B2 (en
Inventor
Tatsuro Okamoto
龍郎 岡本
Ikuo Ogawa
育夫 小河
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP4311596A priority Critical patent/JPH0682829B2/en
Publication of JPH05198789A publication Critical patent/JPH05198789A/en
Publication of JPH0682829B2 publication Critical patent/JPH0682829B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To realize an ohmic junction, by combining a BPSG insulation film with a barrier metal. CONSTITUTION:A silicon oxide film is formed on the principal surface of a silicon substrate 1. After forming thereon a silicon oxide film BPSG4 including boron and phosphorus, a contact hole 7 is formed. Then, by injecting ions, an impurity diffusing layer 2 is formed near the surface of the silicon substrate 1. Subsequently, a first metallic film 5 is formed out of tungsten, etc., by a CVD method, etc. By these metals, no alloy and no spike phenomenon are generated in its junction plane to the silicon substrate, and an ohmic junction having a low resistance can be obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は半導体装置の製造方法
に関係し、特に大規模集積回路(VLSI)装置におい
て、絶縁膜にBPSG膜を用いた際の金属電極の製造方
法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a metal electrode when a BPSG film is used as an insulating film in a large scale integrated circuit (VLSI) device.

【0002】[0002]

【従来の技術】第2図は絶縁膜にシリコンの熱酸化膜と
リン(P)を含むシリコン酸化膜(PSG)を、配線用
金属膜としてシリコンを含むアルミを用いた従来の金属
電極配線構造の断面図を示し、以下これを用いて従来の
方法を説明する。
2. Description of the Related Art FIG. 2 shows a conventional metal electrode wiring structure in which a silicon thermal oxide film and a silicon oxide film (PSG) containing phosphorus (P) are used as an insulating film and aluminum containing silicon is used as a wiring metal film. A cross-sectional view of the above is shown, and the conventional method will be described below using this.

【0003】まず図に示す様に、シリコン基板(1)の
主面上にシリコン酸化膜(3)及びPSG膜(8)を形
成した後、写真製版・エッチング法によって選択的にコ
ンタクト穴(7)を形成する。続いてイオン注入法・熱
拡散法を用いてシリコン基板の表面付近に不純物層
(2)を形成する。最後にスパッタ法・CVD法等を用
いてシリコンを含むアルミニウム合金膜(6)を形成
し、熱処理を行ってこの合金膜(6)のシンタを行う。
First, as shown in the figure, after a silicon oxide film (3) and a PSG film (8) are formed on the main surface of a silicon substrate (1), contact holes (7) are selectively formed by photolithography and etching. ) Is formed. Then, an impurity layer (2) is formed near the surface of the silicon substrate by using the ion implantation method and the thermal diffusion method. Finally, an aluminum alloy film (6) containing silicon is formed by using a sputtering method, a CVD method or the like, and heat treatment is performed to sinter this alloy film (6).

【0004】[0004]

【発明が解決しようとする課題】絶縁膜にPSG膜が用
いられる従来の半導体装置では、第4図に示す様に素子
の微細化に伴う回路パターンのアスペクト比(パターン
ニングピッチに対する膜厚の比)が増加するに従い、良
好な平坦化を行う為には熱処理温度を上げるかリンの含
有量をふやす必要が生じるが、前者は素子内の不純物分
布に影響を与え、後者は耐湿性を劣化させるという問題
がある。この為従来の処理温度においてより粘性の低い
BPSGが次材料として注目されて来たが、BPSGを
絶縁膜に用いて第2図に示す様な従来の構造をとると、
図3に示す様にBPSG中のボロンがコンタクト穴底部
のシリコン基板表面付近またはシリコンを含むアルミ合
金膜(6)中に拡散しアルミ中のシリコンの動きを助長
する為に、熱処理後シリコン基板と電極の界面に多量の
シリコン(9)が、固相エピタキシャル成長により析出
し、接触抵抗が1〜2桁程度大きくなるという問題があ
った。この発明は上記のような問題点を解決するために
なされたもので、大規模集積回路における回路パターン
の良好な平坦化を行うとともに、低抵抗のすぐれたオー
ミック接合を有する半導体装置の製造方法を提供するこ
とを目的とする。
In the conventional semiconductor device in which the PSG film is used as the insulating film, as shown in FIG. 4, the aspect ratio of the circuit pattern (the ratio of the film thickness to the patterning pitch) accompanying the miniaturization of the element is shown. ) Increases, it becomes necessary to raise the heat treatment temperature or increase the phosphorus content in order to achieve good planarization, but the former affects the impurity distribution in the device, and the latter deteriorates the moisture resistance. There is a problem. For this reason, BPSG, which has a lower viscosity at the conventional processing temperature, has been attracting attention as the next material. However, when BPSG is used as the insulating film and the conventional structure as shown in FIG.
As shown in FIG. 3, boron in the BPSG diffuses near the surface of the silicon substrate at the bottom of the contact hole or in the aluminum alloy film (6) containing silicon and promotes the movement of silicon in the aluminum. There has been a problem that a large amount of silicon (9) is deposited on the interface of the electrode by solid phase epitaxial growth, and the contact resistance increases by 1 to 2 digits. The present invention has been made to solve the above problems, and provides a method for manufacturing a semiconductor device having a good ohmic junction with a low resistance as well as a good planarization of a circuit pattern in a large-scale integrated circuit. The purpose is to provide.

【0005】[0005]

【課題を解決するための手段】この発明に係わる半導体
装置の製造方法は、第2の絶縁膜として特にBPSG膜
を用いた素子において、バリアメタルとして第1の金属
膜を形成した後、シリコンを含むアルミを第2の配線用
金属膜として用いる事により、シリコン基板と電極間界
面へのシリコン析出を防ぐようにしたものである。
According to a method of manufacturing a semiconductor device according to the present invention, silicon is formed after forming a first metal film as a barrier metal in an element using a BPSG film as a second insulating film. By using the contained aluminum as the second wiring metal film, the deposition of silicon on the interface between the silicon substrate and the electrode is prevented.

【0006】[0006]

【作用】この発明の半導体装置の製造方法によって得ら
れるBPSG膜は、アスペクト比の大きな回路パターン
上の凹凸を平坦化するのに有効であり、またこの時第1
の金属膜はBPSG膜中のボロンの第2の金属膜中への
拡散を抑制し、また第2の金属膜とシリコン基板との間
に第1の金属膜をはさむ事により、第2の金属膜中のシ
リコンがコンタクト穴底部のシリコン基板表面に選択的
に固相エピタキシャル成長する現象を防止する。
The BPSG film obtained by the method of manufacturing a semiconductor device according to the present invention is effective for flattening the unevenness on the circuit pattern having a large aspect ratio.
Of the second metal film suppresses the diffusion of boron in the BPSG film into the second metal film, and the second metal film is sandwiched between the second metal film and the silicon substrate. This prevents the phenomenon that the silicon in the film selectively undergoes solid phase epitaxial growth on the surface of the silicon substrate at the bottom of the contact hole.

【0007】[0007]

【実施例】実施例1.以下、この発明の一実施例を図に
ついて説明する。第1図は本発明の一実施例による半導
体装置の断面図を示す。まず図に示す様に、シリコン基
板(1)の主面上にシリコン酸化膜約1000A(3)
を熱酸化によって形成し、その上部にリン5〜10%と
ボロン2〜5%を含むシリコン酸化膜BPSG(4)を
形成した後、写真製版・エッチング法によって選択的に
コンタクト穴(7)を形成する。次にイオン注入法また
は熱拡散法を用いてシリコン基板の表面付近に不純物拡
散層(2)を形成する。続いて第1の金属膜(5)とし
て、チタンタングステン合金、タングステン、チタン窒
化物、タンタル窒化物、モリブデンシリサイド、タング
ステンシリサイド、チタンシリサイド、タンタルシリサ
イド、Poly−Si膜のいずれかをスパッタ法、CV
D法などを用いて形成する。これらの金属はシリコン基
板との接合面においてアロイ・スパイク現象を起こさ
ず、低抵抗のオーミック接合が得られる事、またアルミ
とシリコン間の良好な拡散バリアとなる物として選ばれ
た。最後に、第2の金属膜(6)としてシリコンを含む
アルミ、アルミ・シリコン・銅の合金、及びアルミ単体
の膜をスパッタ法・CVD法などを用いて形成し、熱処
理を行って金属膜のシンタを行う。大規模集積回路にお
いて、パターン面上の平坦化を兼ねた絶縁膜としてBP
SG膜を用いる場合、第1図に示す製造方法による構造
を採用することにより、BPSG中のボロンがシリコン
を含むアルミによって形成された第2の金属膜中へ拡散
を防止し、かつシリコン基板と金属電極界面へのシリコ
ンの固層エピタキシャル成長に起因した析出を防ぐ事が
出来、具体的には1×1μm2 形状のコンタクト穴の場
合でも10Ω以下のオーミック接合を得る事が出来る。
またこの構造により、第2の金属膜にアルミの単体を用
いる事も可能となり、この場合第1の金属膜はシリコン
とアルミのアロイ・スパイク現象を防止する働きをす
る。
EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. First, as shown in the figure, a silicon oxide film of about 1000 A (3) is formed on the main surface of the silicon substrate (1).
Is formed by thermal oxidation, and a silicon oxide film BPSG (4) containing phosphorus 5 to 10% and boron 2 to 5% is formed on top of it, and then contact holes (7) are selectively formed by photolithography and etching. Form. Next, an impurity diffusion layer (2) is formed near the surface of the silicon substrate by using an ion implantation method or a thermal diffusion method. Then, as the first metal film (5), any one of titanium-tungsten alloy, tungsten, titanium nitride, tantalum nitride, molybdenum silicide, tungsten silicide, titanium silicide, tantalum silicide, and Poly-Si film is sputtered by CV.
It is formed by using the D method or the like. These metals were selected as materials that do not cause alloy spike phenomenon at the bonding surface with the silicon substrate, can obtain ohmic bonding with low resistance, and can be a good diffusion barrier between aluminum and silicon. Finally, a film of aluminum containing silicon, an alloy of aluminum, silicon, copper, and aluminum alone is formed as the second metal film (6) by a sputtering method, a CVD method, or the like, and heat treatment is performed to form the metal film. Do the sintering. In large-scale integrated circuits, BP is used as an insulating film that also serves as a flat surface on the pattern surface.
When the SG film is used, by adopting the structure according to the manufacturing method shown in FIG. 1, boron in the BPSG is prevented from diffusing into the second metal film formed of aluminum containing silicon, and a silicon substrate is formed. It is possible to prevent the deposition of silicon on the interface of the metal electrode due to the solid layer epitaxial growth, and specifically, it is possible to obtain an ohmic contact of 10Ω or less even in the case of a 1 × 1 μm 2 shape contact hole.
With this structure, it is also possible to use a simple substance of aluminum for the second metal film, and in this case, the first metal film functions to prevent the alloy spike phenomenon of silicon and aluminum.

【0008】[0008]

【発明の効果】以上の様に、この発明の半導体装置の製
造方法によればBPSG絶縁膜とバリアメタルを組み合
わせる事によって大規模集積回路における回路パターン
の微細化にもかかわらず、回路面の平坦化を行いながら
すぐれたオーミックコンタクトが得られる効果がある。
As described above, according to the method of manufacturing a semiconductor device of the present invention, by combining the BPSG insulating film and the barrier metal, the circuit surface is flat despite the miniaturization of the circuit pattern in a large-scale integrated circuit. There is an effect that excellent ohmic contact can be obtained while performing the oxidization.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の一実施例による半導体装置の構造を
示す断面図
FIG. 1 is a sectional view showing the structure of a semiconductor device according to an embodiment of the present invention.

【図2】従来の半導体装置の断面図FIG. 2 is a sectional view of a conventional semiconductor device.

【図3】金属膜とシリコン基板界面へのシリコン析出の
状態を示す図
FIG. 3 is a diagram showing a state of silicon deposition on an interface between a metal film and a silicon substrate.

【図4】素子の微細化に伴う回路パターンのアスペクト
比の増加を示す図
FIG. 4 is a diagram showing an increase in an aspect ratio of a circuit pattern with miniaturization of an element.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 不純物拡散層 3 酸化膜 4 BPSG膜 5 バリアメタル膜 6 金属膜 7 コンタクト穴 8 PSG膜 9 析出シリコン 1 Silicon Substrate 2 Impurity Diffusion Layer 3 Oxide Film 4 BPSG Film 5 Barrier Metal Film 6 Metal Film 7 Contact Hole 8 PSG Film 9 Precipitated Silicon

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体装置のシリコン基板の不純物拡散
層に電極配線を接続する製造方法であって、 (1)シリコン基板上にボロンとリンを含むシリコン酸
化膜を形成する工程と、 (2)前記シリコン酸化膜に選択的にコンタクト穴を形
成する工程と、 (3)前記シリコン酸化膜上および前記コンタクト穴を
介して、前記不純物拡散層上に第1の金属膜を形成する
工程と、 (4)前記第1の金属膜上にシリコンを含むアルミ合金
を形成する工程とを備えて、 前記第1の金属膜は、チタンとタングステンの合金、タ
ングステン、チタン窒化膜、タンタル窒化膜、モリブデ
ンシリサイド、タングステンシリサイド、チタンシリサ
イド、タンタルシリサイド、または、ポリシリコンのい
ずれかを含むことを特徴とした半導体装置の製造方法。
1. A manufacturing method for connecting an electrode wiring to an impurity diffusion layer of a silicon substrate of a semiconductor device, comprising: (1) forming a silicon oxide film containing boron and phosphorus on the silicon substrate; and (2). A step of selectively forming a contact hole in the silicon oxide film, and (3) a step of forming a first metal film on the impurity diffusion layer on the silicon oxide film and via the contact hole. 4) a step of forming an aluminum alloy containing silicon on the first metal film, wherein the first metal film is an alloy of titanium and tungsten, tungsten, titanium nitride film, tantalum nitride film, molybdenum silicide A method of manufacturing a semiconductor device, comprising any of tungsten silicide, titanium silicide, tantalum silicide, and polysilicon.
JP4311596A 1992-11-20 1992-11-20 Method for manufacturing semiconductor device Expired - Lifetime JPH0682829B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4311596A JPH0682829B2 (en) 1992-11-20 1992-11-20 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4311596A JPH0682829B2 (en) 1992-11-20 1992-11-20 Method for manufacturing semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP60201009A Division JPH0715990B2 (en) 1985-09-11 1985-09-11 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH05198789A true JPH05198789A (en) 1993-08-06
JPH0682829B2 JPH0682829B2 (en) 1994-10-19

Family

ID=18019150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4311596A Expired - Lifetime JPH0682829B2 (en) 1992-11-20 1992-11-20 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0682829B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7821065B2 (en) 1999-03-02 2010-10-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising a thin film transistor comprising a semiconductor thin film and method of manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5748249A (en) * 1980-09-08 1982-03-19 Nec Corp Semiconductor device
JPS605560A (en) * 1983-06-23 1985-01-12 Fujitsu Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5748249A (en) * 1980-09-08 1982-03-19 Nec Corp Semiconductor device
JPS605560A (en) * 1983-06-23 1985-01-12 Fujitsu Ltd Semiconductor device

Also Published As

Publication number Publication date
JPH0682829B2 (en) 1994-10-19

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