JPH05198784A - Lsi master slice chip - Google Patents

Abstract

PURPOSE:To provide an LSI master slice chip wherein the freedoms of the shape and wiring formation of a logic unit are improved and thereby, the degree of the integration of cells is improved substantially. CONSTITUTION:Regarding the present master slice chip, diffusion regions 3a-3c, 5a-5c, 13a-13c, 15a-15c and gate electrodes 4a, 4b, 14a, 14b are provided in a section 1b' too, and fundamentally, an array of gate cells is constituted. In the section 1b', not only mere wiring connections but also logic units can be formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate array integrated circuit of a semi-custom LSI, and more particularly to an LSI master having improved flexibility in forming various elements and wiring and substantially improved cell integration. It relates to slice chips.

[0002]

2. Description of the Related Art In a conventional master slice method, an integrated circuit is manufactured in the same manner up to the last wiring by metal evaporation, and only the last wiring by metal evaporation is used to manufacture an integrated circuit having different functions. It is known. In such a conventional master slice integrated circuit, an element area in which electronic circuit elements are arranged on one chip and a wiring area for wiring between these elements are predetermined, and a diffusion process (wafer process) is performed. The finished master slices are interconnected with a wiring pattern different for each product type to form an LSI.
Therefore, the master slice has a characteristic in that it can satisfy the demand for the optimum integration degree and can be designed in a circuit according to the customer's order, and its flexibility is high.

The structure of a typical master slice chip 1 is shown in FIG. As shown in the figure, the master slice chip 1 generally includes a device area 1a, a wiring area 1b, and an I / O area.
The O buffer pad portion 1c is provided, and each of these areas is partitioned on the semiconductor substrate. In the element area 1a, a large number of electronic circuit elements such as MOS transistors are arranged in an array. For example, a gate array is formed by the gates of MOS transistors. The wiring area 1b is
A plurality of underpasses (embedded wiring layers) 2 extending in the lateral direction are provided in a one-row array in a region where wiring for connecting the elements in the element area 1a is provided. These underpasses are typically polycrystalline silicon, or P
It is formed as a diffusion layer of + diffusion or N + diffusion. On the other hand, the vertical metal wiring in the wiring area 1b is formed by vapor-depositing a metal such as Al on the insulating layer existing on the underpass 2.

FIG. 2 shows a typical example of formation of logic units and wiring between logic units in a conventional master slice chip. That is, as shown in FIG. 2, in the conventional master slice chip, the element area 1a and the wiring area 1b are formed adjacent to each other.
In the element area 1a, basic cells C ₁ and C ₂ are arranged in a one-row array. In the example shown,
The left half of each basic cell has a PMOS structure, while the right half has an NMOS structure.

The PMOS structure has three P-conductivity type diffusion regions 3a, 3b and 3c which are formed in a substrate and are separated from each other.
And a pair of gate electrodes 4a and 4b provided on the substrate with an insulating layer interposed between the diffusion regions. The NMOS structure is composed of three N-conductivity type diffusion regions 5a, 5b and 5c which are formed apart from each other in the substrate, and the gate electrodes 4a and 4b which are common to the above-mentioned PMOS and spread between the diffusion regions. Has been done.

In the basic cell C ₁ , the metal wiring 6
And diffusion regions 3b and 5a via contacts 6a, 6a
And are electrically connected. The lead wire V _DD to which the power supply voltage V _DD is supplied is connected to the diffusion regions 3a and 3c via the contacts 7a and 7b, respectively, and is connected to a predetermined potential (ground potential) V _SS. V _SS is connected to the diffusion region 5c via the contact 8. Input lead wires V ₁ and V ₂ to which a pair of input voltages are supplied are connected to the pair of gate electrodes 4a and 4b, and an output lead wire V for extracting an output from the cell C ₁ is provided in the diffusion region 5a. _OUT is connected.

The cell C ₁ connected as described above is a CMOS
Forming a NAND gate, the circuit diagram of which is shown in FIG. In the figure, a pair of NMOs connected in series
A driver is composed of SQ ₁ and Q ₂ , and a load transistor is composed of a pair of PMOS Q ₃ and Q ₄ connected in parallel. When V ₁ = 0, Q ₁ is off and Q ₃ is on. Therefore, the current in Q ₁ and Q ₃ is zero regardless of the input V ₂ , and the voltage drop in PMOS Q ₃ is zero and V _OUT = V _DD . On the other hand, V ₁ = V ₂ = V _DD
, The NMOS Q ₁ and Q ₂ are on and the PMO
S Q ₃ and Q ₄ are off. Therefore, NMOS Q
The voltage drop at ₁ and Q ₂ is zero and V _OUT = 0. Incidentally, the cell C ₂ is connected in the same manner as the cell C _1, and another cell 2
It constitutes an input CMOS / NAND gate.

In FIG. 2, the wiring area 1b is the element area 1
The wiring path 1b is provided adjacent to a, and a plurality of underpasses 2 formed by diffusing impurities of a predetermined conductivity type into the substrate are provided in the wiring area 1b so as to extend in the horizontal direction. . Output V of cell C ₁ forming a NAND gate
_OUT is connected to the underpass 2a and is connected to the logic unit in another element area via the lead wire 9. On the other hand, the output V of the cell C ₂ forming another NAND gate
_OUT 'is connected to the lead wire 10 via the underpass 2b, and the lead wire 10 is connected to another logic unit (not shown) in the element area provided on the opposite side of the wiring area 1b. In the wiring area 1b in FIG. 2, two metal wirings 11, 11 are further provided.

[0009]

As is apparent from the above description, in the conventional LSI master slice chip, the element areas having a plurality of basic cells and the wiring areas for connecting the cells are alternately arranged. The desired logic unit (for example, NAND, NOR, etc.) is connected by connecting each part of the basic cell in the element area.
And the connection between the thus formed logics is connected by wiring using a wiring section to form a combined logic circuit. In this case, the wiring areas had underpasses oriented in a certain direction and were used only for wiring connections between logic units. Therefore, the degree of integration of the conventional master slice chip is determined by the number of cells provided in the element area, and the effective utilization of the chip area is limited. Furthermore, in order to connect a cell in one element area to a cell in another element area, an underpass provided in the wiring area must be passed, and the inter-cell connection must be a certain value or less. However, the degree of freedom in wiring was limited.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and improves the degree of freedom in forming logic units and wirings, and substantially improves the cell integration degree. It is an object to provide an LSI master slice chip. The LSI master slice chip of the present invention has a gate cell composed of a diffusion region formed in a substrate and a gate electrode provided on the substrate via an insulating layer as a basic cell, and a plurality of the basic cells are provided. The present invention is characterized in that a plurality of cell array areas arranged in an array are provided in parallel with each other, and the cell array areas can be selectively used for functional elements and wiring formation.

[0011]

Embodiments of the present invention will be described below with reference to FIGS. 4 and 5. As is apparent from the embodiment shown in FIG. 4, in the master slice chip of the present invention, the area 1a is substantially the same as the element area 1a of the conventional master slice chip, but the area 1b 'adjacent to the area 1a. Is not a mere wiring area, but is formed in an area which can be selectively used for forming functional elements or wiring. That is,
In the master slice chip of the present invention, a diffusion region and a gate electrode are also provided in the area 1b 'to basically form a gate cell array. Therefore, it is possible to form the logic unit in the area 1b ', not just for the wiring connection. When the area 1b 'is used as the original wiring area, the metal extends in the vertical direction in the figure, and the polysilicon extending in the horizontal direction functions as the original underpass.

In FIG. 4, the area 1a is the area 1a of FIG.
Has the same structure as the above, and substantially the same metal wiring is formed to form two independent NAND gates. In the embodiment shown in FIG. 4, the section 1b 'has the same structure as the section 1a arranged in parallel with it. Therefore, also in the area 1b ', the three P-conductivity type diffusion regions 13a, 13b, 13 formed in the substrate apart from each other are formed.
A basic cell is constituted by c, the N-conductivity type diffusion regions 15a, 15b and 15c, and the gate electrodes 14a and 14b common to them. The gate electrode is formed of, for example, doped polysilicon.

In the case of FIG. 4, the lead wire 16 connects the diffusion regions 13b and 15a, and the lead wire 1
The power supply voltage V _DD is supplied to the diffusion regions 13a and 13c via the input terminal 7 and is supplied to the respective gate electrodes 14a and 14b using V _OUT and V _OUT ′ as inputs, and the output V ₀ is taken out from the diffusion region 15a. Connected to CMOS / NA
It forms an ND gate. Therefore, the configuration of FIG. 4 with metal wiring is shown in a circuit diagram as shown in FIG. In this case, according to the configuration of the present invention, the output of the NAND 21 configured by the cell C ₁ and the NAND ₂ configured by the cell C ₂
When connecting the output of 2 and the input of the NAND 23, the length of the lead wire is significantly shortened. In the case of the conventional technique shown in FIG. 2, the output terminals of the NANDs 21 and 22 and the NA
The connection with the input end of the ND 23 could not be made shorter than the length of the underpass 2. Furthermore, in the present invention,
A logic unit can be formed not only in the area 1a but also in the area 1b ', thus increasing the cell integration degree of the master slice chip and improving the effective area utilization rate. Further, when manufacturing the master slice chip having the configuration of the present invention, it is not necessary to add any new process.

As described above, in the master slice chip of the present invention, unlike the prior art, since the area dedicated to wiring is not provided and the cell array structure is provided as a whole, the wiring flexibility of the logic unit is improved. It should be noted that the present invention should not be limited to the above-mentioned specific embodiments, and various modifications can be made within the technical scope thereof. For example, the area 1a and the adjacent area 1b '
It is also possible to reverse the arrangement relationship between PMOS and NMOS with and.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a configuration of a conventional master slice chip.

FIG. 2 is an explanatory diagram showing a state where a pair of CMOS NAND gates are formed by performing metal wiring on a conventional master slice chip.

FIG. 3 is a circuit diagram of the CMOS NAND gate of FIG.

FIG. 4 is an explanatory diagram showing a state in which metal wiring is performed in the master slice chip of one embodiment of the present invention to form a combination logic of CMOS / NAND gate.

5 is a logic circuit diagram of the structure of FIG. 4. FIG.

[Explanation of symbols]

3, 5, 13, 15 Diffusion region 4, 14 Gate electrode

Claims (1)

[Claims] 1. A basic cell having a gate cell composed of a diffusion region formed in a substrate and a gate electrode provided on the substrate via an insulating layer, wherein a plurality of the basic cells are arranged in an array. An LSI master slice chip, wherein a plurality of the provided cell array areas are provided in parallel with each other, and the cell array areas can be selectively used for functional element formation and wiring formation.