JPH05198607A - Printed wiring board - Google Patents
Printed wiring boardInfo
- Publication number
- JPH05198607A JPH05198607A JP4007927A JP792792A JPH05198607A JP H05198607 A JPH05198607 A JP H05198607A JP 4007927 A JP4007927 A JP 4007927A JP 792792 A JP792792 A JP 792792A JP H05198607 A JPH05198607 A JP H05198607A
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- wiring board
- component mounting
- semiconductor chip
- mark
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、表面実装した半導体チ
ップをポッティングした合成樹脂で封止する印刷配線板
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board for sealing a surface-mounted semiconductor chip with potted synthetic resin.
【０００２】[0002]
【従来の技術】図４は従来例の断面図である。図４にお
いて、10は、印刷配線板１にフェースアップに表面実装
する半導体チップであって、表面の四辺に沿って信号電
極, 電圧電極, 及びアース電極を枠形に配設するととも
に、裏面の全面にメタライズ層を形成している。2. Description of the Related Art FIG. 4 is a sectional view of a conventional example. In FIG. 4, reference numeral 10 denotes a semiconductor chip which is surface-mounted on the printed wiring board 1 in a face-up manner. Signal electrodes, voltage electrodes, and ground electrodes are arranged in a frame shape along the four sides of the front surface, A metallized layer is formed on the entire surface.
【０００３】また、印刷配線板１には、半導体チップ10
を表面実装するために、実装面の所望の位置に、半導体
チップ10の底形状にほぼ等しい角形のダイパッド２を設
けるとともに、このダイパッド２を中心にしてパッド４
を枠に配列し、それぞれのパッド４から信号パターン,
アースパターン及び電源パターン等の導体パターン５を
引き出している。The printed wiring board 1 also has a semiconductor chip 10
In order to surface-mount the semiconductor chip, a rectangular die pad 2 having a shape substantially equal to the bottom shape of the semiconductor chip 10 is provided at a desired position on the mounting surface, and the pad 4 is centered around the die pad 2.
Are arranged in a frame, and the signal pattern from each pad 4
Conductor patterns 5 such as an earth pattern and a power source pattern are drawn out.
【０００４】そして、パッド４の外側に枠形に部品搭載
マーク（図示省略) を、色付きのシリコン系樹脂等でス
クリーン印刷して、半導体チップ10の搭載位置を指定し
ている。A component mounting mark (not shown) is frame-printed on the outside of the pad 4 with a colored silicone resin or the like to specify the mounting position of the semiconductor chip 10.
【０００５】一方、印刷配線板１の表面は、配列したパ
ッド４より大きい枠形の開口部を有するようにソルダレ
ジストを塗布して、ソルダレジスト膜６で導体パターン
５等を被覆している。On the other hand, the surface of the printed wiring board 1 is coated with a solder resist so as to have a frame-shaped opening larger than the arranged pads 4, and the conductor pattern 5 and the like are covered with the solder resist film 6.
【０００６】半導体チップ10は、上述のように構成され
た印刷配線板１上に、その裏面がダイパッド２に合わせ
られ、導電性のダイボンディング接着剤（例えば銀混入
のエポキシ系接着剤）３を用いてダイボンディングさ
れ、表面のそれぞれの電極と印刷配線板１上の対応する
パッド４とが、金線等のボンディングワイヤ，又はテー
プキャリアのリードを介して接続されている。The semiconductor chip 10 has a back surface aligned with the die pad 2 on the printed wiring board 1 constructed as described above, and a conductive die bonding adhesive (for example, a silver-containing epoxy adhesive) 3 is applied thereto. Die-bonding is performed using each electrode on the surface and the corresponding pad 4 on the printed wiring board 1 are connected via a bonding wire such as a gold wire or a lead of a tape carrier.
【０００７】また、エポキシ系樹脂等の合成樹脂８を半
導体チップ10の表面にポッティングして、半導体チップ
10及びボンディングワイヤ等を含む半導体チップ周辺の
全面を封止している。Further, the synthetic resin 8 such as epoxy resin is potted on the surface of the semiconductor chip 10 to
The entire surface around the semiconductor chip, including 10 and bonding wires, is sealed.
【０００８】しかしながら、液状の合成樹脂を半導体チ
ップ10にポッティングすると、裾広がりに広範囲に印刷
配線板上に広がり、他の搭載部品を近接して印刷配線板
に実装することができなくなる。However, when the liquid synthetic resin is potted to the semiconductor chip 10, it spreads over the printed wiring board in a widened manner, making it impossible to mount other mounting components in close proximity to the printed wiring board.
【０００９】したがって、従来は、前述の部品搭載マー
クを出来得る限り厚くすることで、この部品搭載マーク
をダム兼用として用い、合成樹脂８の流出を防止してい
た。或いはまた、特開昭６２ー２２９８６２号公報に提
示されたように、熱硬化性樹脂と撥水性充填剤を主成分
として含む混合物により形成され、且つ表面に撥水性充
填剤が露出した高さが高い枠形のダム９（例えばダム高
さが 500μm)を設けて、合成樹脂８の流出を阻止してい
た。Therefore, conventionally, by making the above-mentioned component mounting mark as thick as possible, the component mounting mark is also used as a dam to prevent the synthetic resin 8 from flowing out. Alternatively, as disclosed in JP-A-62-229862, the height formed by a mixture containing a thermosetting resin and a water-repellent filler as a main component and having the water-repellent filler exposed on the surface is high. A high frame-shaped dam 9 (for example, a dam height of 500 μm) is provided to prevent the synthetic resin 8 from flowing out.
【００１０】[0010]
【発明が解決しようとする課題】ところで部品搭載マー
クを、ポッティングする合成樹脂の流出防止ダムとして
兼用する前者の手段は、高密度実装等の理由から部品搭
載マークの細線化が要求されている。このためにスクリ
ーン印刷時のアスペクト比（高さ／幅）上から部品搭載
マークの高さを十分に高くすることができず、高くとも
せいぜい数十μmである。したがって、流出防止の効果
が十分でないという問題点があった。By the way, the former means which also serves as the dam for preventing the outflow of the synthetic resin for potting the component mounting mark is required to have a thin component mounting mark for reasons such as high density mounting. For this reason, the height of the component mounting mark cannot be made sufficiently high in view of the aspect ratio (height / width) at the time of screen printing, and it is at most several tens of μm. Therefore, there is a problem that the effect of preventing outflow is not sufficient.
【００１１】一方、撥水性充填剤を用いた後者の手段
は、そのダム材の性質からして流出防止作用が十分にあ
り、且つ高さを十分に高く( 500 μm)すると、流出防止
がほぼ完璧である。On the other hand, the latter means using a water-repellent filler has a sufficient outflow preventing action due to the nature of the dam material, and if the height is sufficiently high (500 μm), the outflow prevention is almost complete. Perfect.
【００１２】しかしながら部品搭載マークの材料に較べ
てダムの材料費が高いこと、部品搭載マーク形成の他に
ダム形成の工程が付加されること等から、コストアップ
になるという問題点があった。However, the material cost of the dam is higher than the material of the component mounting mark, and the dam forming process is added in addition to the component mounting mark formation.
【００１３】本発明はこのような点に鑑みて創作された
もので、低コストで且つポッティングする封止用樹脂が
広範囲に広がるのを防止し得る印刷配線板を提供するこ
とを目的としている。The present invention has been made in view of the above points, and an object thereof is to provide a printed wiring board which is low in cost and can prevent the potting resin for sealing from spreading over a wide range.
【００１４】[0014]
【課題を解決するための手段】上記の目的を達成するた
めに本発明は図１に例示したように、表面実装した半導
体チップ10をポッティングした合成樹脂８で封止する印
刷配線板において、半導体チップ10の実装領域が開口す
るよう、印刷配線板１の表面に被着されたソルダレジス
ト膜６と、ソルダレジスト膜６の開口部の縁にスクリー
ン印刷された、半導体チップ10の搭載位置を表示する枠
形の部品搭載マーク30と、部品搭載マーク30の内側で、
部品搭載マーク30に近接した位置に穿孔された複数の孔
20とを有する構成とする。In order to achieve the above object, the present invention provides a printed wiring board for sealing a surface-mounted semiconductor chip 10 with potted synthetic resin 8 as shown in FIG. The solder resist film 6 deposited on the surface of the printed wiring board 1 so that the mounting area of the chip 10 is opened, and the mounting position of the semiconductor chip 10 screen-printed on the edge of the opening of the solder resist film 6 are displayed. Inside the frame-shaped component mounting mark 30 and the component mounting mark 30,
Multiple holes drilled near the component mounting mark 30
20 and 20.
【００１５】また図３に例示したように、少なくとも部
品搭載マーク30のコーナーの内側及び近接して実装され
る他の搭載部品15側の該部品搭載マーク30の内側に、孔
20が近接して配列された構成とする。Further, as illustrated in FIG. 3, a hole is provided at least inside the corner of the component mounting mark 30 and on the inside of the component mounting mark 30 on the side of another mounting component 15 to be mounted in close proximity.
It is assumed that 20s are closely arranged.
【００１６】[0016]
【作用】本発明によれば、ソルダレジスト膜の縁に枠形
に部品搭載マークが形成されているので、細幅で膜厚を
厚くすることの出来ない部品搭載マークであっても、印
刷配線板の表面と部品搭載マークの上端面との差が大き
くなる。According to the present invention, since the component mounting mark is formed in a frame shape on the edge of the solder resist film, even if the component mounting mark is thin and the film thickness cannot be increased, the printed wiring can be formed. The difference between the surface of the plate and the upper end surface of the component mounting mark becomes large.
【００１７】一方、液状の合成樹脂の流動抵抗が孔部分
で大きくなり（表面張力があるので孔には殆ど流れ込ま
ない）図２に図示したように孔の縁で堰き止められる。
なお、孔の縁で堰き止められる結果、孔を外れた位置を
流れる部品搭載マーク方向に流れる合成樹脂の速度が減
速される。On the other hand, the flow resistance of the liquid synthetic resin increases at the hole portion (since there is surface tension, it hardly flows into the hole) and is blocked at the edge of the hole as shown in FIG.
As a result of being blocked by the edge of the hole, the speed of the synthetic resin flowing in the direction of the component mounting mark flowing out of the hole is reduced.
【００１８】上述のように部品搭載マークの上端面の高
さが高いことと、部品搭載マークの内壁に到達する合成
樹脂の量が少なくなることにより、ポッティングされた
合成樹脂が部品搭載マークを乗り越えることが阻止され
る。As described above, since the height of the upper end surface of the component mounting mark is high and the amount of synthetic resin reaching the inner wall of the component mounting mark is small, the potted synthetic resin gets over the component mounting mark. Is prevented.
【００１９】一方、液状の合成樹脂を部品搭載マーク内
にポッティングすると、ポッティングされた合成樹脂
は、枠形の部品搭載マークのコーナーにより多量に集中
する。しかし、コーナーに孔を配列しているので、部品
搭載マークのコーナーから合成樹脂が流出することがな
い。On the other hand, when the liquid synthetic resin is potted in the component mounting mark, the potted synthetic resin is concentrated in a large amount at the corners of the frame-shaped component mounting mark. However, since the holes are arranged at the corners, the synthetic resin does not flow out from the corners of the component mounting mark.
【００２０】さらにまた、近接して搭載する他の搭載部
品側に孔をより多く配列することにより、この搭載部品
側に殆どポッティングした合成樹脂が流出しない。Furthermore, by arranging a larger number of holes on the side of the other mounted component to be mounted in close proximity, almost no potted synthetic resin flows out to the side of this mounted component.
【００２１】[0021]
【実施例】以下図１乃至図３を参照しながら、本発明を
具体的に説明する。なお、全図を通じて同一符号は同一
対象物を示す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to FIGS. The same reference numerals denote the same objects throughout the drawings.
【００２２】図１は本発明の実施例の図で、(A) は断面
図、(B) は平面図、図２は本発明の作用を説明する図、
図３は本発明の他の実施例の平面図である。図１，図２
において、印刷配線板１には、半導体チップ10を表面実
装するために、実装面の所望の位置に、半導体チップ10
の底形状にほぼ等しい角形のダイパッド２を設けるとと
もに、このダイパッド２を中心にしてパッド４を枠に配
列し、それぞれのパッド４から信号パターン, アースパ
ターン及び電源パターン等の導体パターン５を引き出し
ている。FIG. 1 is a diagram of an embodiment of the present invention, (A) is a sectional view, (B) is a plan view, and FIG. 2 is a diagram for explaining the operation of the present invention.
FIG. 3 is a plan view of another embodiment of the present invention. 1 and 2
In order to surface-mount the semiconductor chip 10 on the printed wiring board 1, the semiconductor chip 10 is mounted at a desired position on the mounting surface.
In addition to providing a rectangular die pad 2 having a shape substantially equal to the bottom shape, the pads 4 are arranged in a frame with the die pad 2 as the center, and conductor patterns 5 such as a signal pattern, an earth pattern and a power supply pattern are drawn from each pad 4. There is.
【００２３】そして、印刷配線板１の表面は、配列した
パッド４より大きい枠形の開口部を有するようにソルダ
レジストを塗布して、ソルダレジスト膜６で導体パター
ン５等を被覆している。Then, the surface of the printed wiring board 1 is coated with a solder resist so as to have a frame-shaped opening larger than the arranged pads 4, and the conductor pattern 5 and the like are covered with the solder resist film 6.
【００２４】一方、ソルダレジスト膜６の開口部の縁に
半導体チップ10の搭載位置を表示する枠形の部品搭載マ
ーク30を色付きのシリコン系樹脂等をスクリーン印刷し
て設けている。On the other hand, a frame-shaped component mounting mark 30 for displaying the mounting position of the semiconductor chip 10 is provided on the edge of the opening of the solder resist film 6 by screen-printing a colored silicone resin or the like.
【００２５】なお、この部品搭載マーク30は高密度実装
の要求から細幅のことが要求されたものである。したが
って、このことに伴い膜厚を十分に大きくすることがで
きず、その膜厚はせいぜい40μm 〜50μm である。The component mounting mark 30 is required to have a narrow width due to the requirement for high-density mounting. Therefore, with this, the film thickness cannot be made sufficiently large, and the film thickness is at most 40 μm to 50 μm.
【００２６】また、部品搭載マーク30の内側で、部品搭
載マーク30に近接した位置の要所要所に孔20を穿孔して
いる。なお、図示した孔20は印刷配線板１を貫通してい
るが、この孔20は印刷配線板を貫通することなく、下層
の導体パターンを損傷することがないような深さが望ま
しい。Further, inside the component mounting mark 30, holes 20 are drilled in the required positions in the vicinity of the component mounting mark 30. Although the illustrated hole 20 penetrates the printed wiring board 1, it is preferable that the hole 20 does not penetrate the printed wiring board and has a depth such that the underlying conductor pattern is not damaged.
【００２７】半導体チップ10は、上述のように構成され
た印刷配線板１上に、その裏面がダイパッド２に合わせ
られ、導電性のダイボンディング接着剤（例えば銀混入
のエポキシ系接着剤）３を用いてダイボンディングさ
れ、表面のそれぞれの電極と印刷配線板１上の対応する
パッド４とが、金線等のボンディングワイヤ，又はテー
プキャリアのリードを介して接続されている。The semiconductor chip 10 has a back surface aligned with the die pad 2 on the printed wiring board 1 constructed as described above, and a conductive die bonding adhesive (for example, silver-containing epoxy adhesive) 3 is applied thereto. Die-bonding is performed using each electrode on the surface and the corresponding pad 4 on the printed wiring board 1 are connected via a bonding wire such as a gold wire or a lead of a tape carrier.
【００２８】また、エポキシ系樹脂等の合成樹脂８を半
導体チップ10の表面、即ち部品搭載マーク30内にポッテ
ィングして、半導体チップ10及びボンディングワイヤ等
を含む半導体チップ周辺の全面を封止している。Further, a synthetic resin 8 such as an epoxy resin is potted on the surface of the semiconductor chip 10, that is, inside the component mounting mark 30, and the entire surface around the semiconductor chip including the semiconductor chip 10 and bonding wires is sealed. There is.
【００２９】詳細を図２に図示したように、ソルダレジ
スト膜６の開口部の縁に枠形に部品搭載マーク30を設け
てあるので、印刷配線板１の表面と部品搭載マーク30の
上端面との差が、（部品搭載マーク30の膜厚＋ソルダレ
ジスト膜６の膜厚）となりほぼ 100μm の高さでダムと
しての機能が附加されている。As shown in detail in FIG. 2, since the component mounting mark 30 is provided in a frame shape on the edge of the opening of the solder resist film 6, the surface of the printed wiring board 1 and the upper end surface of the component mounting mark 30 are shown. The difference between and is (film thickness of component mounting mark 30 + film thickness of solder resist film 6), and the function as a dam is added at a height of approximately 100 μm.
【００３０】一方、ポッティングされた液状の合成樹脂
８の流動抵抗は、孔20で大きくなり（表面張力があるの
で孔には殆ど流れ込まない）孔20縁で堰き止められる。
また、孔20の縁で堰き止められる結果、孔20を外れた位
置を流れる部品搭載マーク30方向に流れる合成樹脂の速
度が減速され、内壁に衝突しても部品搭載マーク30を乗
り越えるように盛り上がらない。On the other hand, the flow resistance of the potted liquid synthetic resin 8 increases in the hole 20 (it hardly flows into the hole because of surface tension) and is blocked by the edge of the hole 20.
Further, as a result of being blocked by the edge of the hole 20, the speed of the synthetic resin flowing in the direction of the component mounting mark 30 flowing out of the hole 20 is reduced, and even if it collides with the inner wall, it rises so as to get over the component mounting mark 30. Absent.
【００３１】また、部品搭載マーク30の内壁に到達する
合成樹脂量が少なくなること、及び印刷配線板の表面か
ら部品搭載マーク30の上端面までの高さが大きくなった
ことにより、ポッティングされた合成樹脂８が部品搭載
マーク30を乗り越えて、印刷配線板１の表面に広く拡開
することが阻止される。Further, since the amount of synthetic resin reaching the inner wall of the component mounting mark 30 is small and the height from the surface of the printed wiring board to the upper end surface of the component mounting mark 30 is large, potting is performed. It is prevented that the synthetic resin 8 gets over the component mounting mark 30 and spreads widely on the surface of the printed wiring board 1.
【００３２】図３において、15は部品搭載マーク30の外
側に半導体チップ10に近接して実装する他の搭載部品で
ある。印刷配線板１の表面は、配列したパッド４より大
きい枠形の開口部を有するようにソルダレジストを塗布
して、ソルダレジスト膜６で導体パターン５等を被覆
し、さらにソルダレジスト膜６の開口部の縁に半導体チ
ップ10の搭載位置を表示する枠形の部品搭載マーク30を
色付きのシリコン系樹脂等をスクリーン印刷して設けて
いる。In FIG. 3, reference numeral 15 is another mounting component to be mounted outside the component mounting mark 30 in the vicinity of the semiconductor chip 10. The surface of the printed wiring board 1 is coated with solder resist so as to have a frame-shaped opening larger than the arranged pads 4, the conductor pattern 5 and the like are covered with the solder resist film 6, and the openings of the solder resist film 6 are further formed. A frame-shaped component mounting mark 30 for displaying the mounting position of the semiconductor chip 10 is provided on the edge of the portion by screen-printing a colored silicone resin or the like.
【００３３】そして、部品搭載マーク30の４つのコーナ
ーのそれぞれの内側に孔20を近接して多数配列して設け
ている。さらにまた、他の搭載部品15側の部品搭載マー
ク30の辺の内側に、孔20を近接して多数配列して設けて
いる。A large number of holes 20 are closely arranged inside each of the four corners of the component mounting mark 30. Furthermore, a large number of holes 20 are arranged in close proximity inside the side of the component mounting mark 30 on the side of the other mounting component 15.
【００３４】図３のように孔20を配列してあるので、ポ
ッティングされた液状の合成樹脂８は、部品搭載マーク
30のそれぞれのコーナーにより多く集中してその高さが
他の部分に較べて高くなるが、孔20を多数設けてあるの
で、前述の理由により、部品搭載マーク30を乗り越えて
印刷配線板１の表面に拡開することがない。Since the holes 20 are arranged as shown in FIG. 3, the potted liquid synthetic resin 8 is a component mounting mark.
Although it is concentrated more on each corner of 30 and its height is higher than other parts, since many holes 20 are provided, the printed wiring board 1 is overcome by passing the component mounting mark 30 for the above-mentioned reason. Does not spread to the surface.
【００３５】また、近接して搭載する他の搭載部品15側
にも、孔20を近接して設けているので、ポッティングさ
れた液状の合成樹脂８が部品搭載マーク30を乗り越えて
流出することがない。Further, since the holes 20 are provided in the vicinity of the other mounting components 15 to be mounted in close proximity, the potted liquid synthetic resin 8 can flow over the component mounting marks 30 and flow out. Absent.
【００３６】[0036]
【発明の効果】以上説明したように本発明は、部品を高
い密度に実装し得るように、部品搭載マークの幅を細く
したものに適用して、半導体チップを封止する合成樹脂
が、部品搭載マークの外側に流出することがないので、
高密度に部品を印刷配線板に実装することができる。As described above, the present invention is applied to a component mounting mark having a narrow width so that the component can be mounted at a high density. Since it does not leak to the outside of the mounting mark,
The components can be mounted on the printed wiring board with high density.
【００３７】また、半導体チップを実装するのに必須な
スクリーン印刷した部品搭載マークを設けたもので、材
料費が高い特別のダム等を必要としないので、低コスト
である。Further, since the screen-printed component mounting mark essential for mounting the semiconductor chip is provided, a special dam or the like having a high material cost is not required, so that the cost is low.
【図１】 本発明の実施例の図で、(A) は断面図 (B) は平面図FIG. 1 is a diagram of an embodiment of the present invention, in which (A) is a sectional view and (B) is a plan view.
【図２】 本発明の作用を説明する図FIG. 2 is a diagram for explaining the operation of the present invention.
【図３】 本発明の他の実施例の平面図FIG. 3 is a plan view of another embodiment of the present invention.
【図４】 従来例の断面図FIG. 4 is a sectional view of a conventional example.
１ 印刷配線板 ２ ダイパ
ッド ３ ダイボンディング接着剤 ４ パッド ５ 導体パターン ６ ソルダ
レジスト膜 ８ 合成樹脂 ９ ダム 10 半導体チップ 20 孔 30 部品搭載マーク1 Printed wiring board 2 Die pad 3 Die bonding adhesive 4 Pad 5 Conductor pattern 6 Solder resist film 8 Synthetic resin 9 Dam 10 Semiconductor chip 20 Hole 30 Component mounting mark
Claims (2)
ィングした合成樹脂(8) で封止する印刷配線板におい
て、 該半導体チップ(10)の実装領域が開口するよう、該印刷
配線板(1) の表面に被着させたソルダレジスト膜(6)
と、 該ソルダレジスト膜(6) の開口部の縁にスクリーン印刷
された、該半導体チップ(10)の搭載位置を表示する枠形
の部品搭載マーク(30)と、 該部品搭載マーク(30)の内側で、該部品搭載マーク(30)
に近接した位置に穿孔された複数の孔(20)とを有するこ
とを特徴とする印刷配線板。1. A printed wiring board in which a surface-mounted semiconductor chip (10) is sealed with potted synthetic resin (8), such that the mounting area of the semiconductor chip (10) is opened. ) Solder resist film deposited on the surface of (6)
And a frame-shaped component mounting mark (30) screen-printed on the edge of the opening of the solder resist film (6) for displaying the mounting position of the semiconductor chip (10), and the component mounting mark (30) Inside of, the part mounting mark (30)
A printed wiring board having a plurality of holes (20) formed at a position close to the printed wiring board.
ーの内側、及び近接して実装する他の搭載部品(15)側の
該部品搭載マーク(30)の辺の内側に、孔(20)が近接して
配列されたことを特徴とする請求項１記載の印刷配線
板。2. A hole (20) is provided at least inside a corner of the component mounting mark (30) and inside a side of the component mounting mark (30) on the side of another mounting component (15) to be mounted in close proximity. The printed wiring board according to claim 1, wherein the printed wiring boards are arranged close to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4007927A JPH05198607A (en) | 1992-01-20 | 1992-01-20 | Printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4007927A JPH05198607A (en) | 1992-01-20 | 1992-01-20 | Printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05198607A true JPH05198607A (en) | 1993-08-06 |
Family
ID=11679160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4007927A Withdrawn JPH05198607A (en) | 1992-01-20 | 1992-01-20 | Printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05198607A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08167678A (en) * | 1994-12-09 | 1996-06-25 | Sony Corp | Semiconductor device |
| US6001671A (en) * | 1996-04-18 | 1999-12-14 | Tessera, Inc. | Methods for manufacturing a semiconductor package having a sacrificial layer |
| US6821821B2 (en) | 1996-04-18 | 2004-11-23 | Tessera, Inc. | Methods for manufacturing resistors using a sacrificial layer |
| US20130337198A1 (en) * | 2011-09-30 | 2013-12-19 | Hitachi Solutions, Ltd. | Reflection frame-equipped sheet |
-
1992
- 1992-01-20 JP JP4007927A patent/JPH05198607A/en not_active Withdrawn
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08167678A (en) * | 1994-12-09 | 1996-06-25 | Sony Corp | Semiconductor device |
| US6001671A (en) * | 1996-04-18 | 1999-12-14 | Tessera, Inc. | Methods for manufacturing a semiconductor package having a sacrificial layer |
| US6093584A (en) * | 1996-04-18 | 2000-07-25 | Tessera, Inc. | Method for encapsulating a semiconductor package having apertures through a sacrificial layer and contact pads |
| US6294830B1 (en) | 1996-04-18 | 2001-09-25 | Tessera, Inc. | Microelectronic assembly with conductive terminals having an exposed surface through a dielectric layer |
| US6821821B2 (en) | 1996-04-18 | 2004-11-23 | Tessera, Inc. | Methods for manufacturing resistors using a sacrificial layer |
| US6856235B2 (en) | 1996-04-18 | 2005-02-15 | Tessera, Inc. | Methods for manufacturing resistors using a sacrificial layer |
| US7165316B2 (en) | 1996-04-18 | 2007-01-23 | Tessera, Inc. | Methods for manufacturing resistors using a sacrificial layer |
| US20130337198A1 (en) * | 2011-09-30 | 2013-12-19 | Hitachi Solutions, Ltd. | Reflection frame-equipped sheet |
| US9044995B2 (en) * | 2011-09-30 | 2015-06-02 | Hitachi Solutions, Ltd. | Reflection frame-equipped sheet |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990408 |