JPH0519814B2 - - Google Patents

Info

Publication number
JPH0519814B2
JPH0519814B2 JP23791584A JP23791584A JPH0519814B2 JP H0519814 B2 JPH0519814 B2 JP H0519814B2 JP 23791584 A JP23791584 A JP 23791584A JP 23791584 A JP23791584 A JP 23791584A JP H0519814 B2 JPH0519814 B2 JP H0519814B2
Authority
JP
Japan
Prior art keywords
active layer
metal bumps
active
metal
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP23791584A
Other languages
Japanese (ja)
Other versions
JPS61116849A (en
Inventor
Masaaki Yasumoto
Tadayoshi Enomoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP23791584A priority Critical patent/JPS61116849A/en
Publication of JPS61116849A publication Critical patent/JPS61116849A/en
Publication of JPH0519814B2 publication Critical patent/JPH0519814B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、2種類の集積回路層(以下、能動層
と称する)を互いに接着させた多層構造集積回路
の製造方法に関する。更に詳しくは、各能動層間
の信号や電源のやりとりを行なうために異なる能
動層に設けられた金属バンプ同士を拡散溶接法を
用いて接続する半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a multilayer integrated circuit in which two types of integrated circuit layers (hereinafter referred to as active layers) are adhered to each other. More specifically, the present invention relates to a method of manufacturing a semiconductor device in which metal bumps provided on different active layers are connected using a diffusion welding method in order to exchange signals and power between the active layers.

〔従来の技術〕[Conventional technology]

多層構造集積回路はトランジスタ、抵抗および
コンデンサ等の機能素子が3次元的に配置された
集積回路である。多層構造によれば機能素子が2
次元的に配置されている従来の集積回路に比べて
集積度や回路規摸の向上、配線長の短縮による動
作速度の高速化が期待できる。多層構造集積回路
を実現する方法の1つに、機能素子を2次元的に
配置した従来の機能層を個別に製造し、これらの
能動層を順に積層する方法が考えられる。この方
法によつて多層構造回路の実現するためには前記
能動層間の配線を行なう金属バンプを前記能動層
表面に設ける必要がある。また、各能動層に設け
られた金属バンプ同士を接続する方法として拡散
溶接法がある。
A multilayer integrated circuit is an integrated circuit in which functional elements such as transistors, resistors, and capacitors are arranged three-dimensionally. According to the multilayer structure, there are two functional elements.
Compared to conventional integrated circuits that are arranged dimensionally, it is expected that the degree of integration and circuit design will be improved, and the operating speed will be faster due to shorter wiring lengths. One possible method for realizing a multilayer integrated circuit is to separately manufacture conventional functional layers in which functional elements are arranged two-dimensionally, and then stack these active layers in sequence. In order to realize a multilayer structure circuit by this method, it is necessary to provide metal bumps on the surface of the active layer for wiring between the active layers. Further, there is a diffusion welding method as a method for connecting metal bumps provided on each active layer.

第2図a〜cに多層構造集積回路の製造方法の
一例を示す。第2図aにおいて、第1の能動層1
01および第2の能動層201を個別に作製す
る。なお、図中102,103は第1の能動層1
01の構成するシリコン、ガリウム砒素、石英、
サフアイア等の基板、および機能素子層、104
は第1の能動層101の表面に形成されている金
等の第1の金属バンプである。202,203は
第2の能動層201を構成するシリコン、ガリウ
ム砒素、石英、サフアイア等の基板、および機能
素子層、204は第2の能動層201の表面に形
成されている金等の第2の金属バンプである。各
能動層の機能素子層は、通常よく知られている半
導体集積回路製造プロセス、例えばNMOS、
PMOS、CMOS、バイポーラ、あるいはガリウ
ム砒素プロセス等により作製される。また、金属
バンプは、選択メツキ法、写真喰刻法等を用いて
金属膜パターンを形成することにより得られる。
次に、第2図bに示すように、第1の能動層10
1と第2の能動層201とを、互いの表面を対向
させ、それぞれの能動層表面に設けられている金
属バンプ104,204が互いに同一位置になる
まで目合せを行なう。目合せ方法の一例として、
縮小投影露光器などに用いられるオフアクシス法
がある。この方法では、まず目合せ装置内に2個
所の目合せ場所を設ける。それぞれの目合せ場所
にはチツプあるいはウエハーを固定するステージ
と目合せ基準マークとが設けられており、この目
合せ基準マーク間の距離はあらかじめ決められて
いる。まず、第1の能動層101、第2の能動層
201をそれぞれのステージに固定した後、ステ
ージを微動させ、それぞれの目合せ基準マークと
チツプあるいはウエハーに設けられている目合せ
マークとを一致させる。
An example of a method for manufacturing a multilayer integrated circuit is shown in FIGS. 2a to 2c. In FIG. 2a, the first active layer 1
01 and the second active layer 201 are manufactured separately. In addition, 102 and 103 in the figure are the first active layer 1.
01 consists of silicon, gallium arsenide, quartz,
Substrate such as sapphire, and functional element layer, 104
are first metal bumps made of gold or the like formed on the surface of the first active layer 101. Reference numerals 202 and 203 denote substrates such as silicon, gallium arsenide, quartz, and sapphire constituting the second active layer 201, and functional element layers; 204 denotes a second substrate made of gold or the like formed on the surface of the second active layer 201; It is a metal bump. The functional element layer of each active layer is usually formed using a well-known semiconductor integrated circuit manufacturing process, such as NMOS,
Manufactured using PMOS, CMOS, bipolar, or gallium arsenide processes. Further, the metal bumps can be obtained by forming a metal film pattern using a selective plating method, a photolithography method, or the like.
Next, as shown in FIG. 2b, the first active layer 10
The first and second active layers 201 are aligned so that their surfaces face each other until the metal bumps 104 and 204 provided on the surfaces of the respective active layers are at the same position. As an example of alignment method,
There is an off-axis method used in reduction projection exposure devices. In this method, two alignment locations are first provided in the alignment device. Each alignment location is provided with a stage for fixing a chip or wafer and alignment reference marks, and the distance between the alignment reference marks is predetermined. First, after fixing the first active layer 101 and the second active layer 201 to their respective stages, the stages are moved slightly to align each alignment reference mark with the alignment mark provided on the chip or wafer. let

次に、例えば第1の能動層101が固定されて
いるステージを目合せ基準マーク間の距離だけ移
動させ、第1の能動層101が第2の能動層20
1の直下へ来るように関係位置を設定する。この
結果、両能動層101と201とは、ステージを
移動させる機械的な精度(1μm以下)で目合せ
が行なわれる。引き続き、第2図cに示したよう
に、第1の能動層101と第2の能動層201と
にそれぞれ設けられている金属バンプ104およ
び204の表面を互いに接触させ、所定の圧力で
加熱し、両金属バンプ104と204との間で拡
散溶接を起こさせ、第1の能動層101と第2の
能動層201を一体に接着させる。以上の工程が
終了すれば、2層構造集積回路が実現される。以
上示した製造方法で重要な工程は拡散溶接法であ
る。
Next, for example, the stage on which the first active layer 101 is fixed is moved by the distance between the alignment reference marks, so that the first active layer 101 is fixed to the second active layer 20.
Set the relative position so that it is directly below 1. As a result, both active layers 101 and 201 are aligned with mechanical precision (1 μm or less) by moving the stage. Subsequently, as shown in FIG. 2c, the surfaces of the metal bumps 104 and 204 provided on the first active layer 101 and the second active layer 201, respectively, are brought into contact with each other and heated at a predetermined pressure. , diffusion welding is caused between both metal bumps 104 and 204 to bond the first active layer 101 and the second active layer 201 together. When the above steps are completed, a two-layer integrated circuit is realized. An important process in the manufacturing method shown above is the diffusion welding method.

拡散溶接法は300℃前後に加熱した2種類ある
いは、同種類の金属の接触面に数Kg力/mm2の圧力
を加え、接触面での両金属分子の固相拡散により
両金属を接着させる方法で、他の接着法、例えば
導電接着剤を用いる方法や、半田等の低融点金属
を溶かして接着させる方法に比べて、接着部の電
気抵抗が小さい、微細パターンの接着も可能であ
る、接着力が強い等の特徴がある。このため、拡
散溶接法は、集積回路チツプ内のパツドとパツケ
ージのリード線の接着(ボンデイング)等、集積
回路の実装工程で広く使用されている。ところ
で、従来のボンデイングは、パツド1個(面積は
約0.01mm2)に対するものであるから、圧力をかけ
る方法が容易である〔電子材料、1972年12月号、
152〜161ページ〕。また、複数のパツドに対して
同時にボンデイングを行なう方法としてビームリ
ード方式も知られている〔電子材料、1973年2月
号、159〜162ページ〕。複数のパツドを同時にボ
ンデイングするためには各パツドに加わる圧力が
均一でなければならない。このため本方式ではビ
ーム・リードに弾力性を持たせることにより、各
ビーム・リードとパツド間の圧力が均一になるよ
うにしている。
In the diffusion welding method, a pressure of several kilograms/ mm2 is applied to the contact surfaces of two types of metals or of the same type heated to around 300℃, and the two metals are bonded by solid phase diffusion of the molecules of both metals at the contact surfaces. Compared to other bonding methods, such as methods using conductive adhesives or methods that bond by melting low-melting point metals such as solder, this method has a lower electrical resistance at the bonded part and is also capable of bonding fine patterns. It has characteristics such as strong adhesive strength. For this reason, the diffusion welding method is widely used in integrated circuit mounting processes, such as bonding between pads within an integrated circuit chip and lead wires of a package. By the way, since conventional bonding is for one pad (area approximately 0.01 mm 2 ), it is easy to apply pressure [Electronic Materials, December 1972 issue,
Pages 152-161]. A beam lead method is also known as a method for simultaneously bonding multiple pads [Electronic Materials, February 1973 issue, pages 159-162]. In order to bond multiple pads simultaneously, the pressure applied to each pad must be uniform. For this reason, in this system, the beam leads are given elasticity so that the pressure between each beam lead and the pad is made uniform.

第2図cの拡散溶接も複数の第1および第2の
金属バンプに対して同時にボンデイングを行なう
から第1の能動層101と第2の能動層201の
接触面に垂直でしかも均一な圧力をかける必要が
ある。
The diffusion welding shown in FIG. 2c also involves bonding a plurality of first and second metal bumps at the same time, so a uniform pressure is applied perpendicularly to the contact surface between the first active layer 101 and the second active layer 201. I need to put it on.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところが、能動層101,201がいずれもシ
リコン単結晶、ガリウム砒素単結晶、石英、サフ
アイア等の硬い基板上に形成されているから、先
に述べたボンデイングやビームリード方式におけ
る加圧法では、殆ど均一に圧力をかけることがで
きない。この結果、各機能層表面に設けられた金
属バンプ同士が全面にわたつて十分で拡散溶接さ
れず、部分的に各機能層間が電気的に接続されな
かつたり接合面の抵抗が不均一になるといつた問
題が発生しやすい。
However, since the active layers 101 and 201 are both formed on hard substrates such as silicon single crystal, gallium arsenide single crystal, quartz, sapphire, etc., the bonding and beam lead methods described above can hardly uniformly coat the active layers 101 and 201. can't put pressure on it. As a result, the metal bumps provided on the surface of each functional layer are not sufficiently spread welded over the entire surface, and if there is a partial electrical connection between each functional layer or the resistance of the bonding surface becomes uneven, problems are likely to occur.

本発明は上記欠点を解消し、各能動層表面に設
けられた複数の金属バンプ同士を完全に拡散溶接
するために均一に圧力を加える方法を提供するも
のである。
The present invention solves the above drawbacks and provides a method for uniformly applying pressure to completely diffusion weld a plurality of metal bumps provided on the surface of each active layer.

〔問題点を解決するための手段〕[Means for solving problems]

本発明はトランジスタ、抵抗、コンデンサ等の
機能素子が形成されている第1および第2の能動
層の表面にそれぞれ複数個の第1および第2の金
属バンプを設け、次に該第1の能動層と該第2の
能動層との表面を互いに対向させて対応する第1
および第2の金属バンプの位置を目合わせにより
一致させ、第1および第2の金属バンプを拡散溶
接法により接着して多層構造集積回路を製造する
工程において固定支持具に設けた平坦面上に、す
でに前記工程にて目合せが施工された第1および
第2の能動層を第1の能動層が下になるように上
下に設置し、次に第1の能動層の上に設けられて
いる第2の能動層の表面上に、上下面が平行な平
坦面を持つ緩衝ブロツクを配置し、さらに、該緩
衝ブロツクの上面に硬球を介して可動支持具を設
置し、しかる後、固定支持具と可能支持具の間に
圧力をかけながら加熱することを特徴とする半導
体装置の製造方法である。
The present invention provides a plurality of first and second metal bumps on the surfaces of the first and second active layers, respectively, on which functional elements such as transistors, resistors, and capacitors are formed, and then The surfaces of the layer and the second active layer are opposed to each other to form a corresponding first active layer.
and on a flat surface provided on a fixing support in the process of manufacturing a multilayer integrated circuit by aligning the positions of the second metal bumps and bonding the first and second metal bumps by diffusion welding. , the first and second active layers, which have already been aligned in the above step, are installed one above the other so that the first active layer is on the bottom, and then the first and second active layers are placed on top of the first active layer. A buffer block having a flat surface with parallel upper and lower surfaces is placed on the surface of the second active layer, and a movable support is placed on the top surface of the buffer block via a hard ball, and then a fixed support is placed on the top surface of the second active layer. This method of manufacturing a semiconductor device is characterized in that heating is performed while applying pressure between a tool and a supporting tool.

〔実施例〕〔Example〕

以下、図面を用いて本発明の実施例を詳細に説
明する。第1図は、本発明による拡散溶接方法を
断面図を用いて示したものである、第1図aは、
第2図bの工程において、目合せ後互いに接触さ
せた第1の能動層101および第2の能動層20
1を固定支持具301に設置した図である。鉄な
どでできた固定支持具301上は、その表面が研
磨等により平坦に仕上げられており、第1の機能
層101の裏面と301の表面とが十分密着でき
るようになつている。また301の表面に第1の
能動層101等を固定する真空チヤツク孔やガイ
ド治具等が設けられていてもよい。次に第1図b
に示すように、第2の能動層201の裏面に少な
くとも第2の能動層裏面全面を覆う鉄、あるいは
ステンレス等の緩衝金属ブロツク302を設置
し、さらに緩衝金属ブロツク302上に鉄などの
硬球303を設置する。緩衝金属ブロツク302
の第2の能動層201の裏面と接触する面および
硬球303と接触する面とは互い平行でしかも平
坦に仕上げられている必要がある。また、緩衝金
属ブロツク302と硬球303との接触点は、第
2の能動層201の裏面中央付近になるように関
係位置を設定する。最後に、第1図cに示すよう
に、硬球303の上から可動支持具304を介し
て圧力装置305を圧下して硬球303を押しつ
けながら、所定時間加熱する。圧力装置305
に、ねじの締めつけトルク力を用いるものや、空
圧、油圧コンプレツサを用いれば、圧力を自由に
加圧力を制御できる。金属バンプ104,204
が金でできている場合の圧力、温度、時間の一例
としては、それぞれ、3Kg/mm2、300℃、30分で
ある。
Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows the diffusion welding method according to the present invention using a cross-sectional view.
In the step of FIG. 2b, the first active layer 101 and the second active layer 20 are brought into contact with each other after alignment.
1 installed on a fixed support 301. The surface of the fixing support 301 made of iron or the like is finished flat by polishing or the like, so that the back surface of the first functional layer 101 and the surface of the first functional layer 301 can be brought into close contact with each other. Further, a vacuum chuck hole, a guide jig, etc., for fixing the first active layer 101 and the like may be provided on the surface of the layer 301. Next, Figure 1b
As shown in FIG. 2, a buffer metal block 302 made of iron or stainless steel is installed on the back surface of the second active layer 201 to cover at least the entire back surface of the second active layer, and a hard ball 303 made of iron or the like is placed on the buffer metal block 302. Set up. Buffer metal block 302
The surface that contacts the back surface of the second active layer 201 and the surface that contacts the hard ball 303 need to be parallel to each other and finished flat. Further, the relative position is set so that the contact point between the buffer metal block 302 and the hard ball 303 is near the center of the back surface of the second active layer 201. Finally, as shown in FIG. 1c, the pressure device 305 is pressed down from above the hard ball 303 via the movable support 304 to press the hard ball 303 and heat it for a predetermined period of time. Pressure device 305
In addition, if a screw tightening torque is used, or a pneumatic or hydraulic compressor is used, the pressure can be freely controlled. Metal bumps 104, 204
Examples of pressure, temperature, and time when the material is made of gold are 3 Kg/mm 2 , 300° C., and 30 minutes, respectively.

以上述べた方法の特徴は、硬球303と緩衝金
属ブロツク302とが接触する部分が常に一点で
あるため、圧力装置305の加圧方向が第2の能
動層201の裏面に垂直でなくとも、緩衝金属ブ
ロツク302では、圧力の方向が201の裏面に
垂直な方向に修正されること、更に、緩衝金属ブ
ロツク302と硬球303との接触点に集中され
ていた圧力が、第2の能動層201の裏面と、緩
衝金属ブロツク302との接触面において一様に
分散されることにある。この結果、第1の能動層
と第2の能動層との接触面には常に垂直でしかも
一様な圧力がかかるから第1および第2の能動層
表面に設けられた複数の金属バンプが一様に拡散
溶接される。
The feature of the method described above is that the hard ball 303 and the buffer metal block 302 always contact at one point, so even if the pressure direction of the pressure device 305 is not perpendicular to the back surface of the second active layer 201, In the metal block 302, the direction of the pressure is corrected to a direction perpendicular to the back surface of the metal block 201, and furthermore, the pressure concentrated at the contact point between the buffer metal block 302 and the hard ball 303 is transferred to the second active layer 201. It is to be uniformly distributed on the contact surface between the back surface and the buffer metal block 302. As a result, since a vertical and uniform pressure is always applied to the contact surface between the first and second active layers, the plurality of metal bumps provided on the surfaces of the first and second active layers are Diffusion welding is done in the same way.

以上の説明では一例として特定の材料について
示したが、これに限らない。例えば、金属バンプ
としては、金の外に、アルミニウム、銅等が考え
られる。また、固定支持台、緩衝ブロツク、硬球
等の材質としては、鉄やステンレスの他に、黄
銅、チタン合金、フアインセラミツクス等も適し
ている。更に、第1および第2の能動層を、一層
の機能素子層として説明したが、シリコン・オ
ン・インシユレータ(SOI)等を用いた2層以上
の機能素子層が設けられていてもかまわない。
In the above description, a specific material was described as an example, but the material is not limited to this. For example, as the metal bump, in addition to gold, aluminum, copper, etc. can be considered. In addition to iron and stainless steel, brass, titanium alloy, fine ceramics, and the like are also suitable as materials for the fixed support base, buffer block, hard ball, etc. Furthermore, although the first and second active layers have been described as one functional element layer, two or more functional element layers using silicon on insulator (SOI) or the like may be provided.

〔発明の効果〕〔Effect of the invention〕

以上述べた様に、本発明方法によれば広い面積
にわたつて一様に圧力をかけながら、加熱し、2
つの能動層表面の金属バンプ同士を均一に接着さ
れた多層構造集積回路が実現できる。また、本発
明によれば、2種類の硬い基板上に形成された金
属バンプ同士の接続を可能とするため、例えば、
配線パターンのみ形成されているセラミツク基板
上に複数の集積回路チツプを実装する高密度実装
技術に広く応用できる効果を有するものである。
As described above, according to the method of the present invention, heating is performed while applying pressure uniformly over a wide area, and
A multilayer integrated circuit in which metal bumps on the surfaces of two active layers are evenly bonded to each other can be realized. Further, according to the present invention, in order to enable connection between metal bumps formed on two types of hard substrates, for example,
This has an effect that can be widely applied to high-density mounting technology in which a plurality of integrated circuit chips are mounted on a ceramic substrate on which only a wiring pattern is formed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図a〜cは、本発明の製造方法を工程順に
示す断面図、第2図a〜cは従来の多層構造集積
回路の製造工程を示す断面図である。 101は第1の能動層、102,103,10
4は、それぞれ第1の能動層101を構成する基
板、機能素子層、および第1の金属バンプ、20
1は第2の能動層、202,203,204はそ
れぞれ第2の能動層201を構成する基板、機能
素子層、および第2の金属バンプ、301は固定
支持具、302は緩衝金属ブロツク、303は硬
球、304は可動支持具、305は圧力装置であ
る。
1A to 1C are cross-sectional views showing the manufacturing method of the present invention in order of process, and FIGS. 2A to 2C are cross-sectional views showing the manufacturing process of a conventional multilayer integrated circuit. 101 is the first active layer, 102, 103, 10
4 are a substrate, a functional element layer, and a first metal bump, respectively constituting the first active layer 101;
1 is a second active layer; 202, 203, and 204 are a substrate, a functional element layer, and a second metal bump constituting the second active layer 201, respectively; 301 is a fixing support; 302 is a buffer metal block; 303 304 is a hard ball, 304 is a movable support, and 305 is a pressure device.

Claims (1)

【特許請求の範囲】[Claims] 1 トランジスタ、抵抗、コンデンサ等の機能素
子が形成されている第1および第2の能動層の表
面にそれぞれ複数個の第1および第2の金属バン
プを設け、次に該第1の能動層と該第2の能動層
との表面を互いに対向させて対応する第1および
第2の金属バンプの位置を目合せにより一致さ
せ、第1および第2の金属バンプを拡散溶接法に
より接着して多層構造集積回路を製造する工程に
おいて、固定支持具に設けた平坦面上に、すでに
前記工程にて目合せが施された第1および第2の
能動層を第1の能動層が下になるように上下に設
置し、次に第1の能動層の上に設けられている第
2の能動層の裏面上に、上下面が平行な平坦面を
持つ緩衝金属ブロツクを設置し、さらに、該緩衝
金属ブロツクの上面に硬球を介して可動支持具を
設置し、しかる後、固定支持具と可動支持具の間
に圧力をかけながら加熱することを特徴とする半
導体装置の製造方法。
1. A plurality of first and second metal bumps are respectively provided on the surfaces of the first and second active layers on which functional elements such as transistors, resistors, capacitors, etc. are formed, and then The surfaces of the second active layer are made to face each other, the positions of the corresponding first and second metal bumps are matched by alignment, and the first and second metal bumps are bonded by diffusion welding to form a multilayer. In the process of manufacturing a structural integrated circuit, the first and second active layers, which have already been aligned in the process, are placed on a flat surface provided on a fixing support so that the first active layer is on the bottom. A buffer metal block having a flat surface with parallel upper and lower surfaces is installed on the back surface of the second active layer provided on the first active layer, and 1. A method for manufacturing a semiconductor device, which comprises: installing a movable support on the top surface of a metal block via a hard ball; and then heating while applying pressure between the fixed support and the movable support.
JP23791584A 1984-11-12 1984-11-12 Manufacture of semiconductor device Granted JPS61116849A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23791584A JPS61116849A (en) 1984-11-12 1984-11-12 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23791584A JPS61116849A (en) 1984-11-12 1984-11-12 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS61116849A JPS61116849A (en) 1986-06-04
JPH0519814B2 true JPH0519814B2 (en) 1993-03-17

Family

ID=17022328

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23791584A Granted JPS61116849A (en) 1984-11-12 1984-11-12 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61116849A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02252250A (en) * 1989-03-27 1990-10-11 Nippon Telegr & Teleph Corp <Ntt> Film for semiconductor chip terminal connection and connection method for semiconductor chip terminal

Also Published As

Publication number Publication date
JPS61116849A (en) 1986-06-04

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