JP3003423B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP3003423B2
JP3003423B2 JP4265994A JP26599492A JP3003423B2 JP 3003423 B2 JP3003423 B2 JP 3003423B2 JP 4265994 A JP4265994 A JP 4265994A JP 26599492 A JP26599492 A JP 26599492A JP 3003423 B2 JP3003423 B2 JP 3003423B2
Authority
JP
Japan
Prior art keywords
semiconductor element
metal
insulating substrate
temperature
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP4265994A
Other languages
Japanese (ja)
Other versions
JPH06120228A (en
Inventor
哲浩 山本
博昭 藤本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP4265994A priority Critical patent/JP3003423B2/en
Publication of JPH06120228A publication Critical patent/JPH06120228A/en
Application granted granted Critical
Publication of JP3003423B2 publication Critical patent/JP3003423B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1143Manufacturing methods by blanket deposition of the material of the bump connector in solid form
    • H01L2224/11436Lamination of a preform, e.g. foil, sheet or layer

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、半導体実装に関する半
導体素子の電極上へのバンプ形成に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the formation of bumps on electrodes of a semiconductor device for semiconductor mounting.

【0002】[0002]

【従来の技術】近年、多ピン・狭ピッチLSIの実装方
式として、TAB方式やフリップチップ方式が実用化さ
れている。これらの方式は、いずれも半導体素子の電極
上にバンプ(金属突起)を必要とし、バンプの形成方法
が重要な技術となっている。バンプ形成方法としては、
ウエハー段階でめっき法により形成する方法が一般的で
あるが、設備費等の点でコストが高い。この方法に対し
て、バンプを別基板に形成し、そのバンプを半導体素子
の電極上に転写する方法がある。以下この転写によるバ
ンプ形成方法について説明する。
2. Description of the Related Art In recent years, a TAB method and a flip chip method have been put to practical use as a mounting method of a multi-pin, narrow-pitch LSI. Each of these methods requires a bump (metal projection) on an electrode of a semiconductor element, and the method of forming the bump is an important technique. As the bump formation method,
Although a method of forming by a plating method at a wafer stage is generally used, the cost is high in terms of equipment costs and the like. In contrast to this method, there is a method in which a bump is formed on another substrate and the bump is transferred onto an electrode of a semiconductor element. Hereinafter, a method of forming a bump by this transfer will be described.

【0003】図4は、従来のガラス基板上に形成した金
属突起を半導体素子の電極上へ転写する方法による半導
体素子へのバンプ形成方法を示した工程図である。
FIG. 4 is a process diagram showing a conventional method for forming a bump on a semiconductor device by transferring a metal projection formed on a glass substrate onto an electrode of the semiconductor device.

【0004】以下図4を用いて、従来の半導体素子への
バンプ形成方法について説明する。図4(a)に示すよ
うに、導電膜13を全面に蒸着したガラス等の絶縁性基
板14上にフォトレジスト等により開口部11を有する
絶縁膜12(マスク部)を形成する。次に図4(b)に
示すように、絶縁膜12をマスクとして、開口部11に
電解めっき法を用いてAu,Cu等の金属突起5を形成
する。次に図4(c)に示すように、絶縁膜12を除去
して絶縁性基板基板14が形成される。
[0004] A conventional method for forming a bump on a semiconductor device will be described with reference to FIG. As shown in FIG. 4A, an insulating film 12 (mask portion) having an opening 11 is formed by a photoresist or the like on an insulating substrate 14 of glass or the like on which a conductive film 13 is deposited on the entire surface. Next, as shown in FIG. 4B, using the insulating film 12 as a mask, metal projections 5 of Au, Cu, or the like are formed in the openings 11 by electrolytic plating. Next, as shown in FIG. 4C, the insulating film 12 is removed, and an insulating substrate 14 is formed.

【0005】以降図4(d)〜図4(h)は、図4
(a)〜図4(c)ようにして製造した従来の転写用金
属突起基板15を用いた半導体素子上への金属突起形成
方法を素子収納まで含めて示したものである。
[0005] FIG. 4D to FIG.
4 (a) to 4 (c) show a method of forming metal projections on a semiconductor device using a conventional metal projection substrate 15 for transfer manufactured as shown in FIG.

【0006】まず図4(d)に示すように、半導体素子
1の電極2と転写用金属突起基板15上の金属突起3と
を位置合わせする。次に図4(e)に示すように、加圧
冶具9を用いて半導体素子1の電極2と金属突起3とを
加圧・加熱し、電極2と金属突起3との間に共晶合金を
形成して電極2と金属突起3とを接続させる。この時、
金属突起3と電極2との接合強度は金属突起3と絶縁性
基板14上の導電膜13との密着力よりも大きいため金
属突起3は半導体素子1へ転写されることになる。次に
図4(f)に示すように、加圧冶具9の微孔からN2
を軽く噴出することにより金属突起3を有する半導体素
子を転写用金属突起基板15上に残留させる。次に図4
(g)に示すように、真空吸着冶具7を用いて金属突起
を有する半導体素子を転写用金属突起基板から移動させ
る。次に図4(h)に示すように、金属突起3を有する
半導体素子1を真空吸着冶具7を用いてチップトレー1
5に収納する。
First, as shown in FIG. 4D, the electrodes 2 of the semiconductor element 1 and the metal projections 3 on the transfer metal projection substrate 15 are aligned. Next, as shown in FIG. 4 (e), the electrode 2 and the metal protrusion 3 of the semiconductor element 1 are pressed and heated using a pressing jig 9, and a eutectic alloy is formed between the electrode 2 and the metal protrusion 3. Is formed to connect the electrode 2 and the metal protrusion 3. At this time,
Since the bonding strength between the metal protrusion 3 and the electrode 2 is larger than the adhesion between the metal protrusion 3 and the conductive film 13 on the insulating substrate 14, the metal protrusion 3 is transferred to the semiconductor element 1. Next, as shown in FIG. 4 (f), the semiconductor element having the metal protrusion 3 is left on the transfer metal protrusion substrate 15 by gently blowing N 2 or the like from the fine hole of the pressing jig 9. Next, FIG.
As shown in (g), the semiconductor element having the metal projection is moved from the transfer metal projection substrate using the vacuum suction jig 7. Next, as shown in FIG. 4 (h), the semiconductor element 1 having the metal projections 3 is attached to the chip tray 1 using a vacuum suction jig 7.
Store in 5.

【0007】[0007]

【発明が解決しようとする課題】しかしながら上記のよ
うな方法では、加熱した加圧冶具が半導体素子に直接接
触するためにその半導体素子自体にかなりの熱が加わる
ことになるので素子の特性を変化させてしまうなどの不
良が生じ歩留まりが低下するという問題点を有してい
た。
However, in the above-described method, since the heated pressing jig directly contacts the semiconductor element, considerable heat is applied to the semiconductor element itself, so that the characteristics of the element are changed. However, there is a problem that a defect such as the occurrence of a defect is caused and the yield is reduced.

【0008】本発明は上記問題点に鑑み、半導体素子に
その特性を変化させるだけの熱を与えることなく、基板
上の金属突起と半導体素子の電極に共晶合金を形成する
ために十分な熱を与える半導体装置の製造方法を提供す
るものである。
SUMMARY OF THE INVENTION In view of the above problems, the present invention provides sufficient heat to form a eutectic alloy between a metal projection on a substrate and an electrode of a semiconductor element without applying heat to the semiconductor element to change its characteristics. And a method for manufacturing a semiconductor device.

【0009】[0009]

【課題を解決するための手段】上記問題点を解決するた
めに本発明の半導体装置製造方法は、絶縁性基板上に
形成された金属突起と半導体素子の電極とを位置合わせ
し、前記半導体素子を前記金属突起上に設置する工程
と、前記半導体素子及び前記絶縁性基板を加熱し、前記
半導体素子を前記絶縁性基板に加圧し、前記半導体素子
の電極と前記金属突起を接合し、前記半導体素子の温度
が前記絶縁性基板の温度よりも低くなるように前記半導
体素子と前記絶縁性基板を加熱して、前記金属突起を前
記絶縁性基板から前記半導体素子の電極へ転写する工程
とよりなる半導体装置の製造方法であって、前記金属突
起を半導体素子の電極へ転写する工程は、前記半導体素
子の特性変化を防止するために、前記半導体素子の温度
が前記半導体素子の電極と前記金属突起との接続面の温
度よりも低くなるように前記半導体素子と前記絶縁性基
板とを加熱して、前記金属突起を前記絶縁性基板から前
記半導体素子の電極へ転写する工程である。
In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention comprises: aligning a metal projection formed on an insulating substrate with an electrode of a semiconductor element; Placing an element on the metal protrusion
Heating the semiconductor element and the insulating substrate,
Pressing a semiconductor element against the insulating substrate;
Electrode and the metal protrusion are joined together, and the temperature of the semiconductor element is
So that the temperature is lower than the temperature of the insulating substrate.
The body element and the insulating substrate are heated so that the metal protrusions
Transferring from the insulating substrate to the electrode of the semiconductor element
A method of manufacturing a semiconductor device comprising:
The step of transferring the protrusions to the electrodes of the semiconductor
Temperature of the semiconductor element to prevent the characteristics of the semiconductor element from changing.
Is the temperature of the connection surface between the electrode of the semiconductor element and the metal protrusion.
The semiconductor element and the insulating group
And heating the plate so that the metal protrusions are in front of the insulating substrate.
This is a step of transferring to the electrodes of the semiconductor element.

【0010】[0010]

【作用】本発明は上記した構成によって金属突起を半導
体素子に転写する際に、半導体素子の温度が共晶合金を
形成する金属突起と素子の配線電極との接続面の温度よ
りも低くなるために、半導体素子の特性変化などの不良
なしで高い歩留まりの金属突起の半導体素子への転写を
行うことができることとなる。
According to the present invention, the temperature of the semiconductor element is lower than the temperature of the connection surface between the metal projection forming the eutectic alloy and the wiring electrode of the element when the metal projection is transferred to the semiconductor element by the above structure. In addition, it is possible to transfer the metal projections with high yield to the semiconductor element without a defect such as a change in the characteristics of the semiconductor element.

【0011】[0011]

【実施例】以下本発明の一実施例の半導体装置製造方
法について、図面を参照しながら説明する。
A method for manufacturing a semiconductor device of an embodiment of EXAMPLES Hereinafter the present invention will be described with reference to the drawings.

【0012】(図1)は本発明の第1の実施例における
半導体装置の製造方法の工程を示すものである。図1に
おいて、1は半導体素子、2は半導体素子の配線電極、
3は金属突起、4はバンプ形成用基板で導電膜が全面に
蒸着形成されている。5は第1の加熱ツール、6は第2
の加熱ツール、7はチップ搬送用の真空冶具である。
FIG. 1 shows the steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. In FIG. 1, 1 is a semiconductor element, 2 is a wiring electrode of the semiconductor element,
Reference numeral 3 denotes a metal protrusion, and reference numeral 4 denotes a bump-forming substrate on which a conductive film is formed by evaporation. 5 is the first heating tool, 6 is the second heating tool
A heating tool 7 is a vacuum jig for transporting chips.

【0013】まず(図1)の(a)のように、半導体素
子1の配線電極2とバンプ形成用基板4上の導電膜上に
形成された金属突起3を位置合わせする。次に(図1)
のように、半導体素子1の配線電極2とバンプ形成用基
板4上の金属突起3とをコンタクトさせる。次に(図
1)の(c)の用に300℃程度に加熱した第1の加熱
ツール5を半導体素子1側から、450℃程度に加熱し
た第2の加熱ツール6をバンプ形成用基板4側から半導
体素子1と転写用基板3とをはさむようにして加圧およ
び加熱して、バンプ形成用基板4上の金属突起3を半導
体素子1の配線電極2に転写させる。次に(図1)の
(d)の用に、第1の加熱ツールの微孔からN2を噴出
して金属突起3を転写した半導体素子1をバンプ形成用
基板4上に残留させる。次に(図1)の(e)のように
バンプ形成用基板4上に残留させてある半導体素子1を
チップ搬送用の真空冶具7を用いてチップコレットに収
納する。
First, as shown in FIG. 1A, the wiring electrodes 2 of the semiconductor element 1 and the metal projections 3 formed on the conductive film on the bump forming substrate 4 are aligned. Next (Fig. 1)
As described above, the wiring electrode 2 of the semiconductor element 1 is brought into contact with the metal protrusion 3 on the bump forming substrate 4. Next, the first heating tool 5 heated to about 300 ° C. for (c) of FIG. 1 is transferred from the semiconductor element 1 side to the second heating tool 6 heated to about 450 ° C. for the bump forming substrate 4. The metal element 3 on the bump forming substrate 4 is transferred to the wiring electrode 2 of the semiconductor element 1 by pressing and heating the semiconductor element 1 and the transfer substrate 3 so as to sandwich the semiconductor element 1 from the side. Next, for (d) of FIG. 1, N2 is ejected from the fine holes of the first heating tool, and the semiconductor element 1 to which the metal protrusions 3 have been transferred is left on the bump forming substrate 4. Next, as shown in (e) of FIG. 1, the semiconductor element 1 remaining on the bump forming substrate 4 is housed in a chip collet using a vacuum jig 7 for chip transportation.

【0014】以上のように温度の低い第1の加熱ツール
を半導体素子1側から温度の高い第2の加熱ツールをバ
ンプ形成用基板4側からそれぞれ用いて加圧することに
より、半導体素子1に高い温度をかけることなく、信頼
性の高い金属突起3の半導体素子1への転写を行うこと
ができる。また、平面度の高いツール2つを用いて、さ
らにその2つのツール間のギャップを精度よくコントロ
ールすることにより、チップ内及びチップ間の転写後の
金属突起の高さのばらつきを抑えることができる。
As described above, the first heating tool having a low temperature is applied from the side of the semiconductor element 1 and the second heating tool having a high temperature is applied from the side of the bump forming substrate 4 so that the semiconductor element 1 has a high temperature. The highly reliable transfer of the metal protrusions 3 to the semiconductor element 1 can be performed without applying a temperature. In addition, by using two tools having high flatness and controlling the gap between the two tools with high accuracy, it is possible to suppress the variation in the height of the metal projections in the chip and after the transfer between the chips. .

【0015】(図2)は本発明の第1の実施例における
効果を説明するものである。例えば(図2)のようにバ
ンプ形成用基板側から高い温度の冶具で加圧することに
より、接合部の温度のほうが半導体素子の温度よりも高
くなるような転写の工程を行うことができる。
FIG. 2 illustrates the effect of the first embodiment of the present invention. For example, as shown in FIG. 2, by applying pressure from a bump forming substrate side using a high-temperature jig, a transfer process can be performed such that the temperature of the bonding portion is higher than the temperature of the semiconductor element.

【0016】(図3)は本発明の第2の実施例における
半導体装置の製造方法の工程を示した断面図である。
FIG. 3 is a sectional view showing steps of a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

【0017】(図3)において、8は加熱ステージ、9
は加熱ツールである。(図3)を用いて、本発明の第2
の実施例の半導体装置の製造方法について説明する。
In FIG. 3, reference numeral 8 denotes a heating stage;
Is a heating tool. Using FIG. 3, the second embodiment of the present invention will be described.
A method of manufacturing the semiconductor device according to the third embodiment will be described.

【0018】まず(図3)の(a)のように 、300
度程度に加熱されたステージ上に真空で固定された半導
体素子1の配線電極2とバンプ形成用基板上4の金属突
起3とを位置合わせする。次に(図3)の(b)のよう
に、バンプ形成用基板4上の金属突起を半導体素子1の
配線電極にコンタクトさせる。次に(図3)の(c)の
ように、約450℃に加熱した加熱ツール9を用いてバ
ンプ形成用基板4側から加圧及び加熱して、バンプ形成
用基板4上の金属突起3を半導体素子1の配線電極2に
転写させる。次に(図3)の(d)のように、加熱ツー
ル9による加圧が終わってバンプ形成用基板と加圧ツー
ル9が上がると金属突起3を転写した半導体素子1が加
熱ステージ8上に残留する。次に(図3)の(e)のよ
うに加熱ステージ8上に残留させてある半導体素子1を
チップ搬送用の真空冶具7を用いてチップコレットに収
納する。
First, as shown in FIG.
The wiring electrode 2 of the semiconductor element 1 and the metal projection 3 on the bump forming substrate 4 fixed on a stage heated to about 4 degrees by vacuum are aligned. Next, as shown in (b) of FIG. 3, the metal protrusion on the bump forming substrate 4 is brought into contact with the wiring electrode of the semiconductor element 1. Next, as shown in (c) of FIG. 3, the metal projections 3 on the bump forming substrate 4 are pressed and heated from the bump forming substrate 4 side using a heating tool 9 heated to about 450 ° C. Is transferred to the wiring electrode 2 of the semiconductor element 1. Next, as shown in (d) of FIG. 3, when the pressing by the heating tool 9 is completed and the bump forming substrate and the pressing tool 9 are raised, the semiconductor element 1 on which the metal protrusions 3 are transferred is placed on the heating stage 8. Remains. Next, as shown in FIG. 3E, the semiconductor element 1 remaining on the heating stage 8 is housed in a chip collet by using a vacuum jig 7 for chip transportation.

【0019】以上のようにバンプ形成用基板4を通して
加熱及び加圧することにより半導体素子1に高い温度を
かけることなく、信頼性の高い金属突起3の半導体素子
1への転写を行うことができる。
As described above, by applying heat and pressure through the bump forming substrate 4, highly reliable transfer of the metal projections 3 to the semiconductor element 1 can be performed without applying a high temperature to the semiconductor element 1.

【0020】[0020]

【発明の効果】以上のように本発明は転写時に、半導体
素子よりもバンプ形成用基板の温度を高くして転写に必
要な熱を突起電極と半導体素子の配線電極の接合面にか
けることにより、半導体素子に弊害を与えるような温度
をかけることなく高い歩留まりの金属突起の半導体素子
への転写をすることができる。
As described above, according to the present invention, at the time of transfer, the temperature of the bump forming substrate is set higher than that of the semiconductor element, and the heat required for transfer is applied to the joint surface between the projecting electrode and the wiring electrode of the semiconductor element. , it is possible to transfer to the semiconductor element of the metal protrusions high yield without applying a temperature which gives the Hay harm to the semiconductor element.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施例の金属突起の転写におけ
る工程の断面図
FIG. 1 is a cross-sectional view of a step in transferring a metal protrusion according to a first embodiment of the present invention.

【図2】本発明の第1の実施例の効果説明のための断面
FIG. 2 is a sectional view for explaining effects of the first embodiment of the present invention.

【図3】本発明の第2の実施例の金属突起の転写におけ
る工程の断面図
FIG. 3 is a cross-sectional view of a step in the transfer of a metal protrusion according to a second embodiment of the present invention.

【図4】従来の金属突起の転写における工程の断面図FIG. 4 is a cross-sectional view of a step in the transfer of a conventional metal projection.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 半導体素子の配線電極 3 金属突起 4 バンプ形成用基板 5 第1の加熱ツール 6 第2の加熱ツール 7 真空冶具 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Wiring electrode of semiconductor element 3 Metal projection 4 Substrate for bump formation 5 First heating tool 6 Second heating tool 7 Vacuum jig

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 絶縁性基板上に形成された金属突起と半
導体素子の電極とを位置合わせし、前記半導体素子を前
記金属突起上に設置する工程、前記半導体素子及び前
記絶縁性基板を加熱し、前記半導体素子を前記絶縁性基
板に加圧し、前記半導体素子の電極と前記金属突起を接
合し、前記半導体素子の温度が前記絶縁性基板の温度よ
りも低くなるように前記半導体素子と前記絶縁性基板を
加熱して、前記金属突起を前記絶縁性基板から前記半導
体素子の電極へ転写する工程よりなる半導体装置の製
造方法であって、前記金属突起を半導体素子の電極へ転
写する工程は、前記半導体素子の特性変化を防止するた
めに、前記半導体素子の温度が前記半導体素子の電極と
前記金属突起との接続面の温度よりも低くなるように前
記半導体素子と前記絶縁性基板とを加熱して、前記金属
突起を前記絶縁性基板から前記半導体素子の電極へ転写
する工程であることを特徴とする半導体装置の製造方
法。
1. A aligning the electrodes of the metal projection and a semiconductor element formed on an insulating substrate, heating the steps of placing the semiconductor element on the metal protrusion, said semiconductor element and said insulating substrate Then, the semiconductor element is pressed against the insulating substrate, the electrode of the semiconductor element is bonded to the metal protrusion, and the semiconductor element and the metal element are connected such that the temperature of the semiconductor element is lower than the temperature of the insulating substrate. by heating the insulating substrate, rolling the metal protrusion from said insulating substrate said method of manufacturing a semiconductor semiconductors device that Na more and a step of transferring to the electrode of the element, the metal protrusion into the electrode of the semiconductor element
The step of copying is performed to prevent a change in the characteristics of the semiconductor element.
In order for the temperature of the semiconductor device to be
So that the temperature is lower than the temperature of the connection surface with the metal protrusion.
Heating the semiconductor element and the insulating substrate to form the metal
Transfer the protrusion from the insulating substrate to the electrode of the semiconductor element
Semiconductor device manufacturing method characterized by the following steps:
Law.
JP4265994A 1992-10-05 1992-10-05 Method for manufacturing semiconductor device Expired - Fee Related JP3003423B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4265994A JP3003423B2 (en) 1992-10-05 1992-10-05 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4265994A JP3003423B2 (en) 1992-10-05 1992-10-05 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH06120228A JPH06120228A (en) 1994-04-28
JP3003423B2 true JP3003423B2 (en) 2000-01-31

Family

ID=17424894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4265994A Expired - Fee Related JP3003423B2 (en) 1992-10-05 1992-10-05 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3003423B2 (en)

Also Published As

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