JPH05197524A - Adder - Google Patents

Abstract

PURPOSE:To eliminate a noise due to the conduction between transistors(TR) by providing a transfer gate which insulates the drains from each other while a common signal varies. CONSTITUTION:When an input signal C is switched to a high or low level to turn off the TR Q4 and turn on the TR Q5, both the TRs Q4 and Q5 conduct temporarily. At this time, a low-level pulse which is as wide as the delay time of a delay circuit G11 is inputted to the gates of TRs Q3 and Q6 through the delay circuit G11 and an exclusive OR circuit consisting of inverters G9 and G10 and TRs Q7 and Q8. Therefore, the TRs Q3 and Q6 are turned off for the time corresponding to the width of the low-level pulse and both the TRs Q4 and Q5 are turned on temporarily to prevent the noise from being generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adder, and more particularly to a circuit in which all or part of the circuit is composed of a transfer gate and an inverter, the drains of two transfer gates are connected to each other, and one of the transfer gates receives a common signal. The present invention relates to an adder configured to give the gate of a gate and the other transfer gate a state opposite to each other, and to prevent noise due to signal wraparound that occurs while a common signal is changing.

[0002]

2. Description of the Related Art In FIG. 3, a full adder in which a part of a conventional circuit is composed of a transfer gate and an inverter is
Input signals F, G, and H are input, output signals e and f are output, and four inverters G17 to G20, four N channel MOS transistors Q17 to Q20, and two-input OR
Gate G21 and three 2-input NAND gates G22-
And G24.

In FIG. 4, a half adder in which the entire conventional circuit is composed of a transfer gate and an inverter is 2
Inverters G25, G26 and four N-channel M
The OS transistors Q21 to Q24 are provided, the input signals I and J are input, and the output signals g and h are output.

The whole (FIG. 4) or part (FIG. 3) of the conventional circuit is composed of a transfer gate and an inverter, the drains of two transfer gates are connected to each other, and one of the transfer gates is connected by a common signal. The adder configured to give the gate and the gate of the other transfer gate to the opposite states can reduce the number of elements as compared with the adder configured by the combination of the basic circuits as shown in FIG. 3 or 4. One of the transfer gates changes from the conductive state to the isolated state due to the change in the common signal,
When the other transfer gate changes from the insulated state to the conductive state, both transfer gates are temporarily brought into the conductive state.

[0005]

In an adder in which the whole or part of such a conventional circuit is composed of a transfer gate and an inverter, one of the transfer gates changes from a conductive state to an insulated state due to a change in a common signal. When the other transfer gate changes from the insulated state to the conductive state, both transfer gates temporarily turn on to generate noise, which causes a latch output to the circuit that outputs the addend input and the augend input. If the flip-flop output is used as it is, there is a problem that the latched value may change due to the influence of this noise.

An object of the present invention is to solve the above problems and provide an adder in which noise due to conduction of both transistors is not generated.

[0007]

According to the structure of the present invention, the whole or part of a circuit is composed of a plurality of transfer gates and a plurality of inverters, and the drains of a pair of transfer gates are connected to each other like the transfer gates. In the adder in which one of the transfer gates and the other of the transfer gates are provided with a contradictory state by a common signal, the drains are insulated from each other only while the common signal is changing. Of the transfer gate is interposed on a signal line connecting the drains of the pair of transfer gates.

[0008]

1 is a circuit diagram showing an adder according to an embodiment of the present invention.

In FIG. 1, in the full adder according to the embodiment of the present invention, an input signal C passes through the gate of the transistor Q4 and the inverter G4 and enters the gate of the transistor Q5. When the input signal C is set high, the gate of the transistor Q4 is set high and the gate of the transistor Q5 is set low. In this state, the transistor Q4 is set to the conductive state and the transistor Q5 is set to the insulated state.

At this time, when the input signal C is high, the delay circuit G
11, inverters G9 and G10, transistor Q
Since the gates of the transistors Q3 and Q6 enter the gates of the transistors Q3 and Q6 through the exclusive OR circuit composed of Q7 and Q7, the transistors Q3 and Q6 become conductive.

The input signal C switches from high to low,
When the transistor Q4 is about to change from the conducting state to the insulating state and the transistor Q5 is about to change from the insulating state to the conducting state, both the transistors Q4 and Q5 are temporarily brought into the conducting state. At this time, the delay signal G11 is delayed from the input signal C. A low-level pulse having a width corresponding to the delay time of the delay circuit G11 passes through the exclusive OR circuit composed of the inverters G9, G10, and the transistors Q7, Q8, and the transistor Q3.
To the gates of Q6 and Q6 and to prevent noise caused by the transistors Q3 and Q6 being in an isolated state for the duration of the pulse width of this row, so that both transistors Q4 and Q5 are temporarily made conductive. .

The adder of this embodiment has input signals A, B,
C is input and output signals a and b are output.

FIG. 2 is a circuit diagram of a half adder according to another embodiment of the present invention. In FIG. 2, in this embodiment, the input signal D
Enters the gates of the transistors Q9 and Q10 through the gates of the transistors Q11 and Q12 and the inverter G12. When the input signal D is set to high, the gates of the transistors Q11 and Q12 are high and the transistor Q is high.
The gates of 9 and Q10 are set low. In this state, the transistors Q11 and Q12 are set to the conductive state and the transistors Q9 and Q10 are set to the insulated state. At this time, the high level of the input signal D passes through the exclusive OR circuit including the transistor Q16, the inverters G14 and G15, and the transistors Q14 and Q15, and the transistor Q13.
, And the gates of Q14, so that this gate goes high and transistors Q13 and Q14 become conductive.

The input signal D switches from high to low,
When the transistors Q11 and Q12 are about to change from the conducting state to the insulating state and the transistors Q9 and Q10 are about to change from the insulating state to the conducting state, the transistors Q9 and Q10 are temporarily changed.
11. Both the transistors Q10 and Q12 become conductive, but at this time, the input signal D is delayed by the delay circuit G16 and the inverters G14 and G15 and the transistors Q14 and Q15.
The delay circuit G passes through the exclusive OR circuit composed of 15
A pulse of a row having a width of 16 delay times enters the gates of the transistors Q13 and Q14, and the transistors Q13 and Q14 are insulated for the time of the width of the pulse of the row, so that the transistors Q9 and Q11, The noise generated when both the transistors Q10 and Q12 are temporarily turned on is prevented.

As described above, in this embodiment, the entire circuit (FIG. 4) or a part (FIG. 3) of the circuit is composed of the transfer gate and the inverter, and the drains of the two transfer gates are connected to each other and are in common. In an adder configured to give opposite states to the gates of one transfer gate and the other transfer gate by a signal, one transfer gate is in a conductive state and the other transfer gate is in an insulated state, and a common signal changes , When one of the transfer gates changes from the conductive state to the insulated state and the other transfer gate changes from the insulated state to the conductive state, noise due to signal wraparound caused by temporarily turning both transfer gates on To prevent this, a clock signal automatically generated by a common signal change. Accordingly, only while the common signal changes, another transfer gate consisting insulated, characterized in that it comprises on the signal line connecting the drains of two transfer gates.

[0016]

As described above, according to the present invention, in the adder in which the whole or a part of the circuit is composed of the transfer gate and the inverter, these two transfer gates are connected on the signal line connecting the drains of the two transfer gates. By providing another transfer gate that is isolated only while the common signal is changing, especially by a clock signal that is automatically generated by a change in the common signal that sets the gates in opposite states, these two When one of the transfer gates changes from the conductive state to the insulating state and the other changes from the insulating state to the conductive state, the effect of temporarily preventing the noise generated when both transfer gates become the conductive state is obtained, This makes it possible to reduce the number of elements and to stabilize the adder composed of a combination of basic circuits. Effect adder for the operation is obtained also obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a full adder according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a half adder according to another embodiment of the present invention.

FIG. 3 is a circuit diagram showing a full adder in which a part of a conventional circuit is composed of a transfer gate and an inverter.

FIG. 4 is a circuit diagram showing a half adder in which the entire conventional circuit is composed of a transfer gate and an inverter.

[Explanation of symbols]

G1, G2, G3, G4, G9, G10, G12, G1
3, G14, G15, G17, G18, G19, G2
0, G25, G26 Inverters G6, G7, G8, G22, G23, G24, G33,
G35, G36 2-input NAND gate G28, G29, G31, G32 2-input NOR gate G27, G30, G38 2-input AND gate G5, G21, G34 2-input OR gate G37 EXCLUSIVE OR gate G11, G16 Delay circuit Q1, Q2, Q3 , Q4, Q5, Q6, Q7, Q8, Q
9, Q10, Q11, Q12, Q13, Q14, Q1
5, Q16, Q17, Q18, Q19, Q20, Q2
1, Q22, Q23, Q24 N-channel type transistor

Claims (1)

[Claims] 1. A whole or part of a circuit is composed of a plurality of transfer gates and a plurality of inverters, the drains of a pair of transfer gates are connected to each other like the transfer gates, and one transfer gate is connected by a common signal. In the adder configured to give a contradictory state to the other transfer gate, another transfer gate for insulating the drains from each other only while the common signal is changing is a pair of the transfer gates. An adder characterized by being interposed on the signal line connecting the drains of the.